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Rev | Author | Line No. | Line |
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2 | lvd | 1 | module ram( |
2 | addr, |
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3 | data, |
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4 | ce_n,oe_n,we_n |
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5 | ); |
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6 | |||
7 | input [15:0] addr; |
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8 | inout [7:0] data; |
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9 | wire [7:0] data; |
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10 | input ce_n,oe_n,we_n; |
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11 | reg [7:0] array [0:65535]; |
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12 | |||
13 | reg [7:0] dou; |
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14 | |||
15 | |||
16 | integer i; |
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17 | |||
18 | initial |
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19 | begin |
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20 | for(i=0;i<65536;i=i+1) |
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21 | array[i] = 8'd0; |
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22 | end |
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23 | |||
24 | |||
25 | assign data = dou; |
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26 | |||
27 | |||
28 | always @* |
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29 | begin |
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30 | if( !ce_n && !oe_n && we_n ) |
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31 | dou <= array[addr]; |
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32 | else |
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33 | dou <= 8'bZZZZZZZZ; |
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34 | |||
35 | |||
36 | if( !ce_n && !we_n ) |
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37 | array[addr] <= data; |
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38 | |||
39 | |||
40 | end |
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41 | |||
42 | |||
43 | |||
44 | |||
45 | endmodule |
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46 |