WebSVN – ngs – Blame – //fpga/current/tb/mp3.v

Rev	Author	Line No.	Line
99	lvd	1	// (c) NedoPC 2013
		2	//
		3	// MP3 data receiver for testing MP3 and SD dmas
		4
		5	`timescale 1ns/100ps
		6
		7	module mp3
		8	(
		9	input wire clk,
		10	input wire sync,
		11	input wire data,
		12
		13	output reg req
		14	);
		15
		16	integer bitcnt;
		17
		18	reg [7:0] buffer;
		19	reg [7:0] tmp;
		20
		21
100	lvd	22	int waitcnt;
99	lvd	23
		24
		25
		26	initial req = 1'b1;
		27
		28
		29	always @(posedge clk)
		30	begin
		31	if( sync )
		32	bitcnt = 7;
		33
		34	if( sync && !req )
		35	begin
		36	$display("mp3: byte started while req=0!");
		37	$stop;
		38	end
		39
		40	if( !(bitcnt<=7 && bitcnt>=0) )
		41	begin
		42	$display("mp3: sync error!");
		43	$stop;
		44	end
		45
		46	buffer[bitcnt] = data;
		47
		48	if( bitcnt=='d0 )
		49	begin
		50	tmp = tb.sdmp3_chk.pop_front();
		51
		52	if( tmp!==buffer )
		53	begin
		54	$display("mp3: data mismatch!");
		55	$stop;
		56	end
		57	end
		58
		59	bitcnt = bitcnt - 1;
		60	end
		61
		62
		63
		64	always @(negedge clk)
		65	begin
		66	if( bitcnt=='d0 )
		67	begin
102	lvd	68	if( $random>32'hd000_0000 )
99	lvd	69	begin
		70	req <= 1'b0;
		71
100	lvd	72	waitcnt = 1+($random&63);
99	lvd	73
		74	repeat( waitcnt ) @(posedge tb.clk_fpga);
		75
		76	req <= 1'b1;
		77	end
		78	end
		79	end
		80
		81
		82	endmodule
		83
		84

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