WebSVN – ngs – Blame – //fpga/current/tb/page_test.s

Rev	Author	Line No.	Line
94	lvd	1
		2	CPU Z80UNDOC
		3	RELAXED ON
		4
		5	include "ports.inc"
		6
		7
		8
		9
		10	LFSR MACRO
		11
		12	;23bit lfsr, bits 22,17 -- 0100_0010__0000_0000__0000_0000
		13	;
		14	; regs BDE
		15
		16	srl b
		17	rr d
		18	rr e
		19	sbc a,a
		20	and 0x42
		21	xor b
		22	ld b,a
		23
		24	ENDM
		25
103	lvd	26	TSTRAM4 MACRO
94	lvd	27
		28	push bc
		29	push de
		30
		31	.wrloop
		32	ld a,ixl
		33	out (c),a
		34	LFSR
		35	ld (hl),a
		36	inc ixl
		37	jr nz,.wrloop
		38
		39
		40	pop de
		41	pop bc
		42
		43	.rdloop
		44	ld a,ixl
		45	out (c),a
		46	LFSR
		47	cp (hl)
		48	jr nz,.error
		49	inc ixl
		50	jr nz,.rdloop
		51	jr .end
		52
		53	.error
103	lvd	54	ld a,3
		55	out (WIN1),a
		56	ld sp,0x8000
		57	jp $+3
		58	jp start2
		59
		60	.end
		61	ENDM
		62
		63
		64	TSTRAM2 MACRO
		65
		66	push bc
		67	push de
		68
		69	ld ixl,0
		70	.wrloop
		71	ld a,ixl
		72	out (c),a
		73	LFSR
		74	ld (hl),a
		75	inc ixl
		76	ld a,ixl
		77	add a,a
		78	jr nc,.wrloop
		79
		80
		81	pop de
		82	pop bc
		83
		84	ld ixl,0
		85	.rdloop
		86	ld a,ixl
		87	out (c),a
		88	LFSR
		89	cp (hl)
		90	jr nz,.error
		91	inc ixl
		92	ld a,ixl
		93	add a,a
		94	jr nc,.rdloop
		95	jr .end
		96
		97	.error
94	lvd	98	inc a
		99	out (LEDCTR),a
		100	jr .error
		101
		102	.end
		103	ENDM
		104
		105
108	lvd	106	TSTRM22 MACRO
94	lvd	107
108	lvd	108	push bc
		109	push de
		110
		111	ld ixl,0
		112	.wrloop
		113	ld a,ixl
		114	rrca
		115	out (c),a
		116	LFSR
		117	ld (hl),a
		118	inc ixl
		119	ld a,ixl
		120	add a,a
		121	jr nc,.wrloop
		122
		123
		124	pop de
		125	pop bc
		126
		127	ld ixl,0
		128	.rdloop
		129	ld a,ixl
		130	rrca
		131	out (c),a
		132	LFSR
		133	cp (hl)
		134	jr nz,.error
		135	inc ixl
		136	ld a,ixl
		137	add a,a
		138	jr nc,.rdloop
		139	jr .end
		140
		141	.error
		142	inc a
		143	out (LEDCTR),a
		144	jr .error
		145
		146	.end
		147	ENDM
		148
		149
		150
		151
94	lvd	152	org 0x4000
		153	; we are in 3rd 16k page now
		154
		155	; norom, no ramro, 24mhz
		156
		157	ld a,M_NOROM+C_24MHZ+M_EXPAG
		158	out (GSCFG0),a
		159
		160
		161	xor a
		162	ld (led),a
		163
		164	ld l,a
		165	ld ixl,a
		166
		167	ld b,0xcc
		168	ld de,0x5aa5
		169
		170	testloop
		171	ld a,(led)
		172	inc a
		173	ld (led),a
108	lvd	174	rrca
		175	rrca
94	lvd	176	out (LEDCTR),a
		177
		178
		179	ld h,0xE0
		180	ld c,WIN3
103	lvd	181	TSTRAM4
94	lvd	182
		183
		184	ld h,0xA0
		185	ld c,WIN2
103	lvd	186	TSTRAM4
94	lvd	187
		188
		189	ld a,3
		190	out (WIN2),a
		191	ld sp,0xc000
		192	jp $+0x4000+3
		193
		194	ld h,0x60
		195	ld c,WIN1
103	lvd	196	TSTRAM4
94	lvd	197
		198	ld a,3
		199	out (WIN1),a
		200	ld sp,0x8000
		201	jp $+3
		202
		203
		204	ld h,0x20
		205	ld c,WIN0
103	lvd	206	TSTRAM4
94	lvd	207
		208
		209	ld h,0xA0
		210	ld c,MPAG
103	lvd	211	TSTRAM4
94	lvd	212
		213	ld h,0xE0
		214	ld c,MPAGEX
103	lvd	215	TSTRAM4
94	lvd	216
103	lvd	217	jp testloop
94	lvd	218
103	lvd	219	start2
		220	xor a
		221	ld (led),a
		222	ld l,a
94	lvd	223
103	lvd	224	loop2
		225	ld a,(led)
		226	inc a
		227	ld (led),a
108	lvd	228	rrca
		229	rrca
		230	rrca
103	lvd	231	out (LEDCTR),a
94	lvd	232
103	lvd	233	ld h,0xE0
		234	ld c,WIN3
		235	TSTRAM2
94	lvd	236
103	lvd	237
		238	ld h,0xA0
		239	ld c,WIN2
		240	TSTRAM2
		241
		242
		243	ld a,3
		244	out (WIN2),a
		245	ld sp,0xc000
		246	jp $+0x4000+3
		247
		248	ld h,0x60
		249	ld c,WIN1
		250	TSTRAM2
		251
		252	ld a,3
		253	out (WIN1),a
		254	ld sp,0x8000
		255	jp $+3
		256
		257
		258	ld h,0x20
		259	ld c,WIN0
		260	TSTRAM2
		261
		262
		263	ld h,0xA0
108	lvd	264	ld c,MPAG ;128 values for each port -- only 64 for mpag!!!
		265	TSTRM22
103	lvd	266
		267	ld h,0xE0
		268	ld c,MPAGEX
108	lvd	269	TSTRM22
103	lvd	270
		271	jp loop2
		272
		273
		274
94	lvd	275	led equ $
		276

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(root)//fpga/current/tb/page_test.s – Rev 108