WebSVN – ngs – Blame – //fpga/current/tb/timer_test.s

Rev	Author	Line No.	Line
93	lvd	1
		2	CPU Z80UNDOC
		3	RELAXED ON
		4
		5	include "ports.inc"
		6
		7
		8	halfper equ 3000000
		9
		10	org 0x4000
		11
		12
94	lvd	13	ld a,M_NOROM+C_24MHZ
93	lvd	14	out (GSCFG0),a
		15
94	lvd	16	im 0
		17
		18	ld hl,0x28
93	lvd	19	ld (hl),0xc3
		20	inc l
94	lvd	21	ld (hl),cnt1&255
		22	inc l
		23	ld (hl),cnt1/256
		24
		25	ld l,0x30
		26	ld (hl),0xc3
		27	inc l
		28	ld (hl),cnt2&255
		29	inc l
		30	ld (hl),cnt2/256
		31
		32	ld a,0x7F
		33	out (INTENA),a
		34	out (INTREQ),a
		35
		36	ld a,M_SETNCLR+M_MP3_DMA_INT
		37	out (INTENA),a
		38	out (INTREQ),a
		39	ei
		40	jr $
		41	cnt1
		42	ld a,M_MP3_DMA_INT
		43	out (INTENA),a
		44
		45	ld a,M_SETNCLR+M_SD_DMA_INT
		46	out (INTENA),a
		47	out (INTREQ),a
		48	ei
		49	jr $
		50	cnt2
		51	ld a,M_SD_DMA_INT
		52	out (INTENA),a
		53
		54	ld a,M_SETNCLR+M_TIMER_INT
		55	out (INTENA),a
		56	ld a,0x7F
		57	out (INTREQ),a
		58
		59
		60	ld l,0x38
		61	ld (hl),0xc3
		62	inc l
93	lvd	63	ld (hl),intt&255
		64	inc l
		65	ld (hl),intt/256
		66
94	lvd	67
93	lvd	68	ld hl,0
		69	ld (counter),hl
		70	xor a
		71	ld (counter+2),a
		72	ld (mode),a
		73
		74
		75	ei
		76
		77
		78	loop
		79	ld hl,65535
		80	ld d,h
		81	ld e,l
		82	wai
		83	ld b,15
		84	djnz $
		85	add hl,de
		86	jp c,wai
		87
		88	ld a,(mode)
		89	inc a
		90	and 7
		91	ld (mode),a
		92	out (TIM_FRQ),a
		93
		94	jr loop
		95
		96
		97	intt
		98	exx
		99	ex af,af'
		100
		101	ld a,(mode)
		102	add a,a
		103	add a,a
		104	add a,tbladd&255
		105	ld e,a
		106	adc a,tbladd/256
		107	sub e
		108	ld d,a
		109
		110	ld hl,counter
		111
		112	ld a,(de)
		113	add a,(hl)
		114	ld (hl),a
		115	inc de
		116	inc hl
		117	ld a,(de)
		118	adc a,(hl)
		119	ld (hl),a
		120	inc de
		121	inc hl
		122	ld a,(de)
		123	adc a,(hl)
		124	ld (hl),a
		125
		126	dec hl
		127	dec hl
		128
		129	ld a,(hl)
		130	sub halfper&255
		131	ld c,a
		132	inc hl
		133	ld a,(hl)
		134	sbc a,(halfper>>8)&255
		135	ld b,a
		136	inc hl
		137	ld a,(hl)
		138	sbc a,(halfper>>16)&255
		139
		140	jp c,eintt
		141
		142	ld (hl),a
		143	dec hl
		144	ld (hl),b
		145	dec hl
		146	ld (hl),c
		147
		148	ld a,0
		149	inc a
		150	ld ($-2),a
		151	out (LEDCTR),a
		152
		153	eintt
		154	exx
		155	ex af,af'
		156	ei
		157	ret
		158
		159	tbladd
		160	dw 640,0
		161	dw 1280,0
		162	dw 2560,0
		163	dw 5120,0
		164	dw 10240,0
		165	dw 40960,0
		166	dw 32768,2
		167	dw 0,10
		168
		169
		170	counter equ $
		171
		172	mode equ counter+3
		173
		174

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(root)//fpga/current/tb/timer_test.s – Rev 94