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| 92 | lvd | 1 | // |
| 2 | // TV80 8-Bit Microprocessor Core |
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| 3 | // Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
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| 4 | // |
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| 5 | // Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) |
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| 6 | // |
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| 7 | // Permission is hereby granted, free of charge, to any person obtaining a |
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| 8 | // copy of this software and associated documentation files (the "Software"), |
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| 9 | // to deal in the Software without restriction, including without limitation |
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| 10 | // the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 11 | // and/or sell copies of the Software, and to permit persons to whom the |
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| 12 | // Software is furnished to do so, subject to the following conditions: |
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| 13 | // |
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| 14 | // The above copyright notice and this permission notice shall be included |
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| 15 | // in all copies or substantial portions of the Software. |
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| 16 | // |
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| 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 18 | // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 19 | // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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| 20 | // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
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| 21 | // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 22 | // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 23 | // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 24 | |||
| 25 | module tv80_alu (/*AUTOARG*/ |
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| 26 | // Outputs |
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| 27 | Q, F_Out, |
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| 28 | // Inputs |
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| 29 | Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In |
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| 30 | ); |
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| 31 | |||
| 32 | parameter Mode = 0; |
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| 33 | parameter Flag_C = 0; |
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| 34 | parameter Flag_N = 1; |
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| 35 | parameter Flag_P = 2; |
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| 36 | parameter Flag_X = 3; |
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| 37 | parameter Flag_H = 4; |
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| 38 | parameter Flag_Y = 5; |
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| 39 | parameter Flag_Z = 6; |
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| 40 | parameter Flag_S = 7; |
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| 41 | |||
| 42 | input Arith16; |
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| 43 | input Z16; |
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| 44 | input [3:0] ALU_Op ; |
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| 45 | input [5:0] IR; |
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| 46 | input [1:0] ISet; |
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| 47 | input [7:0] BusA; |
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| 48 | input [7:0] BusB; |
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| 49 | input [7:0] F_In; |
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| 50 | output [7:0] Q; |
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| 51 | output [7:0] F_Out; |
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| 52 | reg [7:0] Q; |
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| 53 | reg [7:0] F_Out; |
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| 54 | |||
| 55 | function [4:0] AddSub4; |
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| 56 | input [3:0] A; |
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| 57 | input [3:0] B; |
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| 58 | input Sub; |
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| 59 | input Carry_In; |
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| 60 | begin |
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| 61 | AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In}; |
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| 62 | end |
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| 63 | endfunction // AddSub4 |
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| 64 | |||
| 65 | function [3:0] AddSub3; |
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| 66 | input [2:0] A; |
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| 67 | input [2:0] B; |
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| 68 | input Sub; |
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| 69 | input Carry_In; |
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| 70 | begin |
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| 71 | AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In}; |
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| 72 | end |
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| 73 | endfunction // AddSub4 |
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| 74 | |||
| 75 | function [1:0] AddSub1; |
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| 76 | input A; |
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| 77 | input B; |
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| 78 | input Sub; |
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| 79 | input Carry_In; |
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| 80 | begin |
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| 81 | AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In}; |
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| 82 | end |
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| 83 | endfunction // AddSub4 |
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| 84 | |||
| 85 | // AddSub variables (temporary signals) |
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| 86 | reg UseCarry; |
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| 87 | reg Carry7_v; |
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| 88 | reg OverFlow_v; |
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| 89 | reg HalfCarry_v; |
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| 90 | reg Carry_v; |
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| 91 | reg [7:0] Q_v; |
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| 92 | |||
| 93 | reg [7:0] BitMask; |
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| 94 | |||
| 95 | |||
| 96 | always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR) |
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| 97 | begin |
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| 98 | case (IR[5:3]) |
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| 99 | 3'b000 : BitMask = 8'b00000001; |
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| 100 | 3'b001 : BitMask = 8'b00000010; |
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| 101 | 3'b010 : BitMask = 8'b00000100; |
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| 102 | 3'b011 : BitMask = 8'b00001000; |
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| 103 | 3'b100 : BitMask = 8'b00010000; |
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| 104 | 3'b101 : BitMask = 8'b00100000; |
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| 105 | 3'b110 : BitMask = 8'b01000000; |
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| 106 | default: BitMask = 8'b10000000; |
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| 107 | endcase // case(IR[5:3]) |
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| 108 | |||
| 109 | UseCarry = ~ ALU_Op[2] && ALU_Op[0]; |
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| 110 | { HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) ); |
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| 111 | { Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v); |
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| 112 | { Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v); |
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| 113 | OverFlow_v = Carry_v ^ Carry7_v; |
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| 114 | end // always @ * |
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| 115 | |||
| 116 | reg [7:0] Q_t; |
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| 117 | reg [8:0] DAA_Q; |
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| 118 | |||
| 119 | always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB |
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| 120 | or Carry_v or F_In or HalfCarry_v or IR or ISet |
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| 121 | or OverFlow_v or Q_v or Z16) |
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| 122 | begin |
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| 123 | Q_t = 8'hxx; |
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| 124 | DAA_Q = {9{1'bx}}; |
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| 125 | |||
| 126 | F_Out = F_In; |
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| 127 | case (ALU_Op) |
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| 128 | 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 : |
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| 129 | begin |
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| 130 | F_Out[Flag_N] = 1'b0; |
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| 131 | F_Out[Flag_C] = 1'b0; |
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| 132 | |||
| 133 | case (ALU_Op[2:0]) |
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| 134 | |||
| 135 | 3'b000, 3'b001 : // ADD, ADC |
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| 136 | begin |
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| 137 | Q_t = Q_v; |
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| 138 | F_Out[Flag_C] = Carry_v; |
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| 139 | F_Out[Flag_H] = HalfCarry_v; |
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| 140 | F_Out[Flag_P] = OverFlow_v; |
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| 141 | end |
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| 142 | |||
| 143 | 3'b010, 3'b011, 3'b111 : // SUB, SBC, CP |
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| 144 | begin |
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| 145 | Q_t = Q_v; |
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| 146 | F_Out[Flag_N] = 1'b1; |
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| 147 | F_Out[Flag_C] = ~ Carry_v; |
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| 148 | F_Out[Flag_H] = ~ HalfCarry_v; |
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| 149 | F_Out[Flag_P] = OverFlow_v; |
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| 150 | end |
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| 151 | |||
| 152 | 3'b100 : // AND |
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| 153 | begin |
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| 154 | Q_t[7:0] = BusA & BusB; |
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| 155 | F_Out[Flag_H] = 1'b1; |
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| 156 | end |
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| 157 | |||
| 158 | 3'b101 : // XOR |
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| 159 | begin |
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| 160 | Q_t[7:0] = BusA ^ BusB; |
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| 161 | F_Out[Flag_H] = 1'b0; |
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| 162 | end |
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| 163 | |||
| 164 | default : // OR 3'b110 |
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| 165 | begin |
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| 166 | Q_t[7:0] = BusA | BusB; |
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| 167 | F_Out[Flag_H] = 1'b0; |
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| 168 | end |
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| 169 | |||
| 170 | endcase // case(ALU_OP[2:0]) |
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| 171 | |||
| 172 | if (ALU_Op[2:0] == 3'b111 ) |
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| 173 | begin // CP |
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| 174 | F_Out[Flag_X] = BusB[3]; |
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| 175 | F_Out[Flag_Y] = BusB[5]; |
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| 176 | end |
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| 177 | else |
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| 178 | begin |
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| 179 | F_Out[Flag_X] = Q_t[3]; |
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| 180 | F_Out[Flag_Y] = Q_t[5]; |
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| 181 | end |
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| 182 | |||
| 183 | if (Q_t[7:0] == 8'b00000000 ) |
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| 184 | begin |
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| 185 | F_Out[Flag_Z] = 1'b1; |
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| 186 | if (Z16 == 1'b1 ) |
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| 187 | begin |
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| 188 | F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC |
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| 189 | end |
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| 190 | end |
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| 191 | else |
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| 192 | begin |
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| 193 | F_Out[Flag_Z] = 1'b0; |
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| 194 | end // else: !if(Q_t[7:0] == 8'b00000000 ) |
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| 195 | |||
| 196 | F_Out[Flag_S] = Q_t[7]; |
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| 197 | case (ALU_Op[2:0]) |
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| 198 | 3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP |
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| 199 | ; |
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| 200 | |||
| 201 | default : |
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| 202 | F_Out[Flag_P] = ~(^Q_t); |
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| 203 | endcase // case(ALU_Op[2:0]) |
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| 204 | |||
| 205 | if (Arith16 == 1'b1 ) |
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| 206 | begin |
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| 207 | F_Out[Flag_S] = F_In[Flag_S]; |
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| 208 | F_Out[Flag_Z] = F_In[Flag_Z]; |
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| 209 | F_Out[Flag_P] = F_In[Flag_P]; |
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| 210 | end |
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| 211 | end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 |
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| 212 | |||
| 213 | 4'b1100 : |
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| 214 | begin |
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| 215 | // DAA |
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| 216 | F_Out[Flag_H] = F_In[Flag_H]; |
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| 217 | F_Out[Flag_C] = F_In[Flag_C]; |
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| 218 | DAA_Q[7:0] = BusA; |
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| 219 | DAA_Q[8] = 1'b0; |
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| 220 | if (F_In[Flag_N] == 1'b0 ) |
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| 221 | begin |
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| 222 | // After addition |
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| 223 | // Alow > 9 || H == 1 |
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| 224 | if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) |
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| 225 | begin |
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| 226 | if ((DAA_Q[3:0] > 9) ) |
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| 227 | begin |
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| 228 | F_Out[Flag_H] = 1'b1; |
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| 229 | end |
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| 230 | else |
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| 231 | begin |
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| 232 | F_Out[Flag_H] = 1'b0; |
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| 233 | end |
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| 234 | DAA_Q = DAA_Q + 6; |
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| 235 | end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) |
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| 236 | |||
| 237 | // new Ahigh > 9 || C == 1 |
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| 238 | if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 ) |
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| 239 | begin |
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| 240 | DAA_Q = DAA_Q + 96; // 0x60 |
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| 241 | end |
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| 242 | end |
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| 243 | else |
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| 244 | begin |
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| 245 | // After subtraction |
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| 246 | if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 ) |
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| 247 | begin |
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| 248 | if (DAA_Q[3:0] > 5 ) |
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| 249 | begin |
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| 250 | F_Out[Flag_H] = 1'b0; |
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| 251 | end |
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| 252 | DAA_Q[7:0] = DAA_Q[7:0] - 6; |
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| 253 | end |
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| 254 | if (BusA > 153 || F_In[Flag_C] == 1'b1 ) |
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| 255 | begin |
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| 256 | DAA_Q = DAA_Q - 352; // 0x160 |
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| 257 | end |
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| 258 | end // else: !if(F_In[Flag_N] == 1'b0 ) |
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| 259 | |||
| 260 | F_Out[Flag_X] = DAA_Q[3]; |
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| 261 | F_Out[Flag_Y] = DAA_Q[5]; |
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| 262 | F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8]; |
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| 263 | Q_t = DAA_Q[7:0]; |
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| 264 | |||
| 265 | if (DAA_Q[7:0] == 8'b00000000 ) |
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| 266 | begin |
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| 267 | F_Out[Flag_Z] = 1'b1; |
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| 268 | end |
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| 269 | else |
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| 270 | begin |
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| 271 | F_Out[Flag_Z] = 1'b0; |
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| 272 | end |
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| 273 | |||
| 274 | F_Out[Flag_S] = DAA_Q[7]; |
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| 275 | F_Out[Flag_P] = ~ (^DAA_Q); |
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| 276 | end // case: 4'b1100 |
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| 277 | |||
| 278 | 4'b1101, 4'b1110 : |
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| 279 | begin |
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| 280 | // RLD, RRD |
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| 281 | Q_t[7:4] = BusA[7:4]; |
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| 282 | if (ALU_Op[0] == 1'b1 ) |
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| 283 | begin |
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| 284 | Q_t[3:0] = BusB[7:4]; |
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| 285 | end |
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| 286 | else |
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| 287 | begin |
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| 288 | Q_t[3:0] = BusB[3:0]; |
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| 289 | end |
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| 290 | F_Out[Flag_H] = 1'b0; |
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| 291 | F_Out[Flag_N] = 1'b0; |
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| 292 | F_Out[Flag_X] = Q_t[3]; |
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| 293 | F_Out[Flag_Y] = Q_t[5]; |
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| 294 | if (Q_t[7:0] == 8'b00000000 ) |
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| 295 | begin |
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| 296 | F_Out[Flag_Z] = 1'b1; |
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| 297 | end |
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| 298 | else |
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| 299 | begin |
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| 300 | F_Out[Flag_Z] = 1'b0; |
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| 301 | end |
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| 302 | F_Out[Flag_S] = Q_t[7]; |
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| 303 | F_Out[Flag_P] = ~(^Q_t); |
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| 304 | end // case: when 4'b1101, 4'b1110 |
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| 305 | |||
| 306 | 4'b1001 : |
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| 307 | begin |
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| 308 | // BIT |
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| 309 | Q_t[7:0] = BusB & BitMask; |
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| 310 | F_Out[Flag_S] = Q_t[7]; |
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| 311 | if (Q_t[7:0] == 8'b00000000 ) |
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| 312 | begin |
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| 313 | F_Out[Flag_Z] = 1'b1; |
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| 314 | F_Out[Flag_P] = 1'b1; |
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| 315 | end |
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| 316 | else |
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| 317 | begin |
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| 318 | F_Out[Flag_Z] = 1'b0; |
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| 319 | F_Out[Flag_P] = 1'b0; |
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| 320 | end |
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| 321 | F_Out[Flag_H] = 1'b1; |
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| 322 | F_Out[Flag_N] = 1'b0; |
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| 323 | F_Out[Flag_X] = 1'b0; |
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| 324 | F_Out[Flag_Y] = 1'b0; |
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| 325 | if (IR[2:0] != 3'b110 ) |
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| 326 | begin |
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| 327 | F_Out[Flag_X] = BusB[3]; |
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| 328 | F_Out[Flag_Y] = BusB[5]; |
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| 329 | end |
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| 330 | end // case: when 4'b1001 |
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| 331 | |||
| 332 | 4'b1010 : |
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| 333 | // SET |
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| 334 | Q_t[7:0] = BusB | BitMask; |
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| 335 | |||
| 336 | 4'b1011 : |
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| 337 | // RES |
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| 338 | Q_t[7:0] = BusB & ~ BitMask; |
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| 339 | |||
| 340 | 4'b1000 : |
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| 341 | begin |
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| 342 | // ROT |
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| 343 | case (IR[5:3]) |
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| 344 | 3'b000 : // RLC |
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| 345 | begin |
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| 346 | Q_t[7:1] = BusA[6:0]; |
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| 347 | Q_t[0] = BusA[7]; |
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| 348 | F_Out[Flag_C] = BusA[7]; |
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| 349 | end |
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| 350 | |||
| 351 | 3'b010 : // RL |
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| 352 | begin |
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| 353 | Q_t[7:1] = BusA[6:0]; |
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| 354 | Q_t[0] = F_In[Flag_C]; |
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| 355 | F_Out[Flag_C] = BusA[7]; |
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| 356 | end |
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| 357 | |||
| 358 | 3'b001 : // RRC |
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| 359 | begin |
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| 360 | Q_t[6:0] = BusA[7:1]; |
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| 361 | Q_t[7] = BusA[0]; |
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| 362 | F_Out[Flag_C] = BusA[0]; |
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| 363 | end |
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| 364 | |||
| 365 | 3'b011 : // RR |
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| 366 | begin |
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| 367 | Q_t[6:0] = BusA[7:1]; |
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| 368 | Q_t[7] = F_In[Flag_C]; |
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| 369 | F_Out[Flag_C] = BusA[0]; |
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| 370 | end |
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| 371 | |||
| 372 | 3'b100 : // SLA |
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| 373 | begin |
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| 374 | Q_t[7:1] = BusA[6:0]; |
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| 375 | Q_t[0] = 1'b0; |
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| 376 | F_Out[Flag_C] = BusA[7]; |
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| 377 | end |
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| 378 | |||
| 379 | 3'b110 : // SLL (Undocumented) / SWAP |
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| 380 | begin |
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| 381 | if (Mode == 3 ) |
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| 382 | begin |
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| 383 | Q_t[7:4] = BusA[3:0]; |
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| 384 | Q_t[3:0] = BusA[7:4]; |
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| 385 | F_Out[Flag_C] = 1'b0; |
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| 386 | end |
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| 387 | else |
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| 388 | begin |
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| 389 | Q_t[7:1] = BusA[6:0]; |
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| 390 | Q_t[0] = 1'b1; |
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| 391 | F_Out[Flag_C] = BusA[7]; |
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| 392 | end // else: !if(Mode == 3 ) |
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| 393 | end // case: 3'b110 |
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| 394 | |||
| 395 | 3'b101 : // SRA |
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| 396 | begin |
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| 397 | Q_t[6:0] = BusA[7:1]; |
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| 398 | Q_t[7] = BusA[7]; |
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| 399 | F_Out[Flag_C] = BusA[0]; |
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| 400 | end |
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| 401 | |||
| 402 | default : // SRL |
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| 403 | begin |
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| 404 | Q_t[6:0] = BusA[7:1]; |
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| 405 | Q_t[7] = 1'b0; |
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| 406 | F_Out[Flag_C] = BusA[0]; |
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| 407 | end |
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| 408 | endcase // case(IR[5:3]) |
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| 409 | |||
| 410 | F_Out[Flag_H] = 1'b0; |
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| 411 | F_Out[Flag_N] = 1'b0; |
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| 412 | F_Out[Flag_X] = Q_t[3]; |
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| 413 | F_Out[Flag_Y] = Q_t[5]; |
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| 414 | F_Out[Flag_S] = Q_t[7]; |
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| 415 | if (Q_t[7:0] == 8'b00000000 ) |
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| 416 | begin |
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| 417 | F_Out[Flag_Z] = 1'b1; |
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| 418 | end |
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| 419 | else |
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| 420 | begin |
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| 421 | F_Out[Flag_Z] = 1'b0; |
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| 422 | end |
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| 423 | F_Out[Flag_P] = ~(^Q_t); |
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| 424 | |||
| 425 | if (ISet == 2'b00 ) |
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| 426 | begin |
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| 427 | F_Out[Flag_P] = F_In[Flag_P]; |
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| 428 | F_Out[Flag_S] = F_In[Flag_S]; |
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| 429 | F_Out[Flag_Z] = F_In[Flag_Z]; |
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| 430 | end |
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| 431 | end // case: 4'b1000 |
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| 432 | |||
| 433 | |||
| 434 | default : |
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| 435 | ; |
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| 436 | |||
| 437 | endcase // case(ALU_Op) |
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| 438 | |||
| 439 | Q = Q_t; |
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| 440 | end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) |
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| 441 | |||
| 442 | endmodule // T80_ALU |