WebSVN – ngs – Blame – //fpga/current/tb/z80/tv80_core.v

Rev	Author	Line No.	Line
92	lvd	1	`timescale 1ps/1ps
		2
		3	//
		4	// TV80 8-Bit Microprocessor Core
		5	// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
		6	//
		7	// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
		8	//
		9	// Permission is hereby granted, free of charge, to any person obtaining a
		10	// copy of this software and associated documentation files (the "Software"),
		11	// to deal in the Software without restriction, including without limitation
		12	// the rights to use, copy, modify, merge, publish, distribute, sublicense,
		13	// and/or sell copies of the Software, and to permit persons to whom the
		14	// Software is furnished to do so, subject to the following conditions:
		15	//
		16	// The above copyright notice and this permission notice shall be included
		17	// in all copies or substantial portions of the Software.
		18	//
		19	// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
		20	// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
		21	// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
		22	// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
		23	// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
		24	// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
		25	// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
		26
		27	module tv80_core (/AUTOARG/
		28	// Outputs
		29	m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc,
		30	ts, intcycle_n, IntE, stop,
		31	// Inputs
		32	reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
		33	);
		34	// Beginning of automatic inputs (from unused autoinst inputs)
		35	// End of automatics
		36
		37	parameter Mode = 1; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
		38	parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
		39	parameter Flag_C = 0;
		40	parameter Flag_N = 1;
		41	parameter Flag_P = 2;
		42	parameter Flag_X = 3;
		43	parameter Flag_H = 4;
		44	parameter Flag_Y = 5;
		45	parameter Flag_Z = 6;
		46	parameter Flag_S = 7;
		47
		48	input reset_n;
		49	input clk;
		50	input cen;
		51	input wait_n;
		52	input int_n;
		53	input nmi_n;
		54	input busrq_n;
		55	output m1_n;
		56	output iorq;
		57	output no_read;
		58	output write;
		59	output rfsh_n;
		60	output halt_n;
		61	output busak_n;
		62	output [15:0] A;
		63	input [7:0] dinst;
		64	input [7:0] di;
		65	output [7:0] dout;
		66	output [6:0] mc;
		67	output [6:0] ts;
		68	output intcycle_n;
		69	output IntE;
		70	output stop;
		71
		72	reg m1_n;
		73	reg iorq;
		74	`ifdef TV80_REFRESH
		75	reg rfsh_n;
		76	`endif
		77	reg halt_n;
		78	reg busak_n;
		79	reg [15:0] A;
		80	reg [7:0] dout;
		81	reg [6:0] mc;
		82	reg [6:0] ts;
		83	reg intcycle_n;
		84	reg IntE;
		85	reg stop;
		86
		87	parameter aNone = 3'b111;
		88	parameter aBC = 3'b000;
		89	parameter aDE = 3'b001;
		90	parameter aXY = 3'b010;
		91	parameter aIOA = 3'b100;
		92	parameter aSP = 3'b101;
		93	parameter aZI = 3'b110;
		94
		95	// Registers
		96	reg [7:0] ACC, F;
		97	reg [7:0] Ap, Fp;
		98	reg [7:0] I;
		99	`ifdef TV80_REFRESH
		100	reg [7:0] R;
		101	`endif
		102	reg [15:0] SP, PC;
		103	reg [7:0] RegDIH;
		104	reg [7:0] RegDIL;
		105	wire [15:0] RegBusA;
		106	wire [15:0] RegBusB;
		107	wire [15:0] RegBusC;
		108	reg [2:0] RegAddrA_r;
		109	reg [2:0] RegAddrA;
		110	reg [2:0] RegAddrB_r;
		111	reg [2:0] RegAddrB;
		112	reg [2:0] RegAddrC;
		113	reg RegWEH;
		114	reg RegWEL;
		115	reg Alternate;
		116
		117	// Help Registers
		118	reg [15:0] TmpAddr; // Temporary address register
		119	reg [7:0] IR; // Instruction register
		120	reg [1:0] ISet; // Instruction set selector
		121	reg [15:0] RegBusA_r;
		122
		123	reg [15:0] ID16;
		124	reg [7:0] Save_Mux;
		125
		126	reg [6:0] tstate;
		127	reg [6:0] mcycle;
		128	reg last_mcycle, last_tstate;
		129	reg IntE_FF1;
		130	reg IntE_FF2;
		131	reg Halt_FF;
		132	reg BusReq_s;
		133	reg BusAck;
		134	reg ClkEn;
		135	reg NMI_s;
		136	reg INT_s;
		137	reg [1:0] IStatus;
		138
		139	reg [7:0] DI_Reg;
		140	reg T_Res;
		141	reg [1:0] XY_State;
		142	reg [2:0] Pre_XY_F_M;
		143	reg NextIs_XY_Fetch;
		144	reg XY_Ind;
		145	reg No_BTR;
		146	reg BTR_r;
		147	reg Auto_Wait;
		148	reg Auto_Wait_t1;
		149	reg Auto_Wait_t2;
		150	reg IncDecZ;
		151
		152	// ALU signals
		153	reg [7:0] BusB;
		154	reg [7:0] BusA;
		155	wire [7:0] ALU_Q;
		156	wire [7:0] F_Out;
		157
		158	// Registered micro code outputs
		159	reg [4:0] Read_To_Reg_r;
		160	reg Arith16_r;
		161	reg Z16_r;
		162	reg [3:0] ALU_Op_r;
		163	reg Save_ALU_r;
		164	reg PreserveC_r;
		165	reg [2:0] mcycles;
		166
		167	// Micro code outputs
		168	wire [2:0] mcycles_d;
		169	wire [2:0] tstates;
		170	reg IntCycle;
		171	reg NMICycle;
		172	wire Inc_PC;
		173	wire Inc_WZ;
		174	wire [3:0] IncDec_16;
		175	wire [1:0] Prefix;
		176	wire Read_To_Acc;
		177	wire Read_To_Reg;
		178	wire [3:0] Set_BusB_To;
		179	wire [3:0] Set_BusA_To;
		180	wire [3:0] ALU_Op;
		181	wire Save_ALU;
		182	wire PreserveC;
		183	wire Arith16;
		184	wire [2:0] Set_Addr_To;
		185	wire Jump;
		186	wire JumpE;
		187	wire JumpXY;
		188	wire Call;
		189	wire RstP;
		190	wire LDZ;
		191	wire LDW;
		192	wire LDSPHL;
		193	wire iorq_i;
		194	wire [2:0] Special_LD;
		195	wire ExchangeDH;
		196	wire ExchangeRp;
		197	wire ExchangeAF;
		198	wire ExchangeRS;
		199	wire I_DJNZ;
		200	wire I_CPL;
		201	wire I_CCF;
		202	wire I_SCF;
		203	wire I_RETN;
		204	wire I_BT;
		205	wire I_BC;
		206	wire I_BTR;
		207	wire I_RLD;
		208	wire I_RRD;
		209	wire I_INRC;
		210	wire SetDI;
		211	wire SetEI;
		212	wire [1:0] IMode;
		213	wire Halt;
		214
		215	reg [15:0] PC16;
		216	reg [15:0] PC16_B;
		217	reg [15:0] SP16, SP16_A, SP16_B;
		218	reg [15:0] ID16_B;
		219	reg Oldnmi_n;
		220
		221	tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
		222	(
		223	.IR (IR),
		224	.ISet (ISet),
		225	.MCycle (mcycle),
		226	.F (F),
		227	.NMICycle (NMICycle),
		228	.IntCycle (IntCycle),
		229	.MCycles (mcycles_d),
		230	.TStates (tstates),
		231	.Prefix (Prefix),
		232	.Inc_PC (Inc_PC),
		233	.Inc_WZ (Inc_WZ),
		234	.IncDec_16 (IncDec_16),
		235	.Read_To_Acc (Read_To_Acc),
		236	.Read_To_Reg (Read_To_Reg),
		237	.Set_BusB_To (Set_BusB_To),
		238	.Set_BusA_To (Set_BusA_To),
		239	.ALU_Op (ALU_Op),
		240	.Save_ALU (Save_ALU),
		241	.PreserveC (PreserveC),
		242	.Arith16 (Arith16),
		243	.Set_Addr_To (Set_Addr_To),
		244	.IORQ (iorq_i),
		245	.Jump (Jump),
		246	.JumpE (JumpE),
		247	.JumpXY (JumpXY),
		248	.Call (Call),
		249	.RstP (RstP),
		250	.LDZ (LDZ),
		251	.LDW (LDW),
		252	.LDSPHL (LDSPHL),
		253	.Special_LD (Special_LD),
		254	.ExchangeDH (ExchangeDH),
		255	.ExchangeRp (ExchangeRp),
		256	.ExchangeAF (ExchangeAF),
		257	.ExchangeRS (ExchangeRS),
		258	.I_DJNZ (I_DJNZ),
		259	.I_CPL (I_CPL),
		260	.I_CCF (I_CCF),
		261	.I_SCF (I_SCF),
		262	.I_RETN (I_RETN),
		263	.I_BT (I_BT),
		264	.I_BC (I_BC),
		265	.I_BTR (I_BTR),
		266	.I_RLD (I_RLD),
		267	.I_RRD (I_RRD),
		268	.I_INRC (I_INRC),
		269	.SetDI (SetDI),
		270	.SetEI (SetEI),
		271	.IMode (IMode),
		272	.Halt (Halt),
		273	.NoRead (no_read),
		274	.Write (write)
		275	);
		276
		277	tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
		278	(
		279	.Arith16 (Arith16_r),
		280	.Z16 (Z16_r),
		281	.ALU_Op (ALU_Op_r),
		282	.IR (IR[5:0]),
		283	.ISet (ISet),
		284	.BusA (BusA),
		285	.BusB (BusB),
		286	.F_In (F),
		287	.Q (ALU_Q),
		288	.F_Out (F_Out)
		289	);
		290
		291	function [6:0] number_to_bitvec;
		292	input [2:0] num;
		293	begin
		294	case (num)
		295	1 : number_to_bitvec = 7'b0000001;
		296	2 : number_to_bitvec = 7'b0000010;
		297	3 : number_to_bitvec = 7'b0000100;
		298	4 : number_to_bitvec = 7'b0001000;
		299	5 : number_to_bitvec = 7'b0010000;
		300	6 : number_to_bitvec = 7'b0100000;
		301	7 : number_to_bitvec = 7'b1000000;
		302	default : number_to_bitvec = 7'bx;
		303	endcase // case(num)
		304	end
		305	endfunction // number_to_bitvec
		306
		307	function [2:0] mcyc_to_number;
		308	input [6:0] mcyc;
		309	begin
		310	casez (mcyc)
		311	7'b1zzzzzz : mcyc_to_number = 3'h7;
		312	7'b01zzzzz : mcyc_to_number = 3'h6;
		313	7'b001zzzz : mcyc_to_number = 3'h5;
		314	7'b0001zzz : mcyc_to_number = 3'h4;
		315	7'b00001zz : mcyc_to_number = 3'h3;
		316	7'b000001z : mcyc_to_number = 3'h2;
		317	7'b0000001 : mcyc_to_number = 3'h1;
		318	default : mcyc_to_number = 3'h1;
		319	endcase
		320	end
		321	endfunction
		322
		323	always @(/AUTOSENSE/mcycle or mcycles or tstate or tstates)
		324	begin
		325	case (mcycles)
		326	1 : last_mcycle = mcycle[0];
		327	2 : last_mcycle = mcycle[1];
		328	3 : last_mcycle = mcycle[2];
		329	4 : last_mcycle = mcycle[3];
		330	5 : last_mcycle = mcycle[4];
		331	6 : last_mcycle = mcycle[5];
		332	7 : last_mcycle = mcycle[6];
		333	default : last_mcycle = 1'bx;
		334	endcase // case(mcycles)
		335
		336	case (tstates)
		337
		338	1 : last_tstate = tstate[1];
		339	2 : last_tstate = tstate[2];
		340	3 : last_tstate = tstate[3];
		341	4 : last_tstate = tstate[4];
		342	5 : last_tstate = tstate[5];
		343	6 : last_tstate = tstate[6];
		344	default : last_tstate = 1'bx;
		345	endcase
		346	end // always @ (...
		347
		348
		349	always @(/AUTOSENSE/ALU_Q or BusAck or BusB or DI_Reg
		350	or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
		351	or XY_State or cen or last_tstate or mcycle)
		352	begin
		353	ClkEn = cen && ~ BusAck;
		354
		355	if (last_tstate)
		356	T_Res = 1'b1;
		357	else T_Res = 1'b0;
		358
		359	if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
		360	((Set_Addr_To == aXY) \|\|
		361	(mcycle[0] && IR == 8'b11001011) \|\|
		362	(mcycle[0] && IR == 8'b00110110)))
		363	NextIs_XY_Fetch = 1'b1;
		364	else
		365	NextIs_XY_Fetch = 1'b0;
		366
		367	if (ExchangeRp)
		368	Save_Mux = BusB;
		369	else if (!Save_ALU_r)
		370	Save_Mux = DI_Reg;
		371	else
		372	Save_Mux = ALU_Q;
		373	end // always @ *
		374
		375	always @ (posedge clk or negedge reset_n)
		376	begin
		377	if (reset_n == 1'b0 )
		378	begin
		379	PC <= #1 0; // Program Counter
		380	A <= #1 0;
		381	TmpAddr <= #1 0;
		382	IR <= #1 8'b00000000;
		383	ISet <= #1 2'b00;
		384	XY_State <= #1 2'b00;
		385	IStatus <= #1 2'b00;
		386	mcycles <= #1 3'b000;
		387	dout <= #1 8'b00000000;
		388
		389	ACC <= #1 8'hFF;
		390	F <= #1 8'hFF;
		391	Ap <= #1 8'hFF;
		392	Fp <= #1 8'hFF;
		393	I <= #1 0;
		394	`ifdef TV80_REFRESH
		395	R <= #1 0;
		396	`endif
		397	SP <= #1 16'hFFFF;
		398	Alternate <= #1 1'b0;
		399
		400	Read_To_Reg_r <= #1 5'b00000;
		401	Arith16_r <= #1 1'b0;
		402	BTR_r <= #1 1'b0;
		403	Z16_r <= #1 1'b0;
		404	ALU_Op_r <= #1 4'b0000;
		405	Save_ALU_r <= #1 1'b0;
		406	PreserveC_r <= #1 1'b0;
		407	XY_Ind <= #1 1'b0;
		408	end
		409	else
		410	begin
		411
		412	if (ClkEn == 1'b1 )
		413	begin
		414
		415	ALU_Op_r <= #1 4'b0000;
		416	Save_ALU_r <= #1 1'b0;
		417	Read_To_Reg_r <= #1 5'b00000;
		418
		419	mcycles <= #1 mcycles_d;
		420
		421	if (IMode != 2'b11 )
		422	begin
		423	IStatus <= #1 IMode;
		424	end
		425
		426	Arith16_r <= #1 Arith16;
		427	PreserveC_r <= #1 PreserveC;
		428	if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] )
		429	begin
		430	Z16_r <= #1 1'b1;
		431	end
		432	else
		433	begin
		434	Z16_r <= #1 1'b0;
		435	end
		436
		437	if (mcycle[0] && (tstate[1] \| tstate[2] \| tstate[3] ))
		438	begin
		439	// mcycle == 1 && tstate == 1, 2, \|\| 3
		440	if (tstate[2] && wait_n == 1'b1 )
		441	begin
		442	`ifdef TV80_REFRESH
		443	if (Mode < 2 )
		444	begin
		445	A[7:0] <= #1 R;
		446	A[15:8] <= #1 I;
		447	R[6:0] <= #1 R[6:0] + 1;
		448	end
		449	`endif
		450	if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 \|\| Halt == 1'b1) )
		451	begin
		452	PC <= #1 PC16;
		453	end
		454
		455	if (IntCycle == 1'b1 && IStatus == 2'b01 )
		456	begin
		457	IR <= #1 8'b11111111;
		458	end
		459	else if (Halt_FF == 1'b1 \|\| (IntCycle == 1'b1 && IStatus == 2'b10) \|\| NMICycle == 1'b1 )
		460	begin
		461	IR <= #1 8'b00000000;
		462	TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch
		463	end
		464	else
		465	begin
		466	IR <= #1 dinst;
		467	end
		468
		469	ISet <= #1 2'b00;
		470	if (Prefix != 2'b00 )
		471	begin
		472	if (Prefix == 2'b11 )
		473	begin
		474	if (IR[5] == 1'b1 )
		475	begin
		476	XY_State <= #1 2'b10;
		477	end
		478	else
		479	begin
		480	XY_State <= #1 2'b01;
		481	end
		482	end
		483	else
		484	begin
		485	if (Prefix == 2'b10 )
		486	begin
		487	XY_State <= #1 2'b00;
		488	XY_Ind <= #1 1'b0;
		489	end
		490	ISet <= #1 Prefix;
		491	end
		492	end
		493	else
		494	begin
		495	XY_State <= #1 2'b00;
		496	XY_Ind <= #1 1'b0;
		497	end
		498	end // if (tstate == 2 && wait_n == 1'b1 )
		499
		500
		501	end
		502	else
		503	begin
		504	// either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
		505
		506	if (mcycle[5] )
		507	begin
		508	XY_Ind <= #1 1'b1;
		509	if (Prefix == 2'b01 )
		510	begin
		511	ISet <= #1 2'b01;
		512	end
		513	end
		514
		515	if (T_Res == 1'b1 )
		516	begin
		517	BTR_r <= #1 (I_BT \|\| I_BC \|\| I_BTR) && ~ No_BTR;
		518	if (Jump == 1'b1 )
		519	begin
		520	A[15:8] <= #1 DI_Reg;
		521	A[7:0] <= #1 TmpAddr[7:0];
		522	PC[15:8] <= #1 DI_Reg;
		523	PC[7:0] <= #1 TmpAddr[7:0];
		524	end
		525	else if (JumpXY == 1'b1 )
		526	begin
		527	A <= #1 RegBusC;
		528	PC <= #1 RegBusC;
		529	end else if (Call == 1'b1 \|\| RstP == 1'b1 )
		530	begin
		531	A <= #1 TmpAddr;
		532	PC <= #1 TmpAddr;
		533	end
		534	else if (last_mcycle && NMICycle == 1'b1 )
		535	begin
		536	A <= #1 16'b0000000001100110;
		537	PC <= #1 16'b0000000001100110;
		538	end
		539	else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
		540	begin
		541	A[15:8] <= #1 I;
		542	A[7:0] <= #1 TmpAddr[7:0];
		543	PC[15:8] <= #1 I;
		544	PC[7:0] <= #1 TmpAddr[7:0];
		545	end
		546	else
		547	begin
		548	case (Set_Addr_To)
		549	aXY :
		550	begin
		551	if (XY_State == 2'b00 )
		552	begin
		553	A <= #1 RegBusC;
		554	end
		555	else
		556	begin
		557	if (NextIs_XY_Fetch == 1'b1 )
		558	begin
		559	A <= #1 PC;
		560	end
		561	else
		562	begin
		563	A <= #1 TmpAddr;
		564	end
		565	end // else: !if(XY_State == 2'b00 )
		566	end // case: aXY
		567
		568	aIOA :
		569	begin
		570	if (Mode == 3 )
		571	begin
		572	// Memory map I/O on GBZ80
		573	A[15:8] <= #1 8'hFF;
		574	end
		575	else if (Mode == 2 )
		576	begin
		577	// Duplicate I/O address on 8080
		578	A[15:8] <= #1 DI_Reg;
		579	end
		580	else
		581	begin
		582	A[15:8] <= #1 ACC;
		583	end
		584	A[7:0] <= #1 DI_Reg;
		585	end // case: aIOA
		586
		587
		588	aSP :
		589	begin
		590	A <= #1 SP;
		591	end
		592
		593	aBC :
		594	begin
		595	if (Mode == 3 && iorq_i == 1'b1 )
		596	begin
		597	// Memory map I/O on GBZ80
		598	A[15:8] <= #1 8'hFF;
		599	A[7:0] <= #1 RegBusC[7:0];
		600	end
		601	else
		602	begin
		603	A <= #1 RegBusC;
		604	end
		605	end // case: aBC
		606
		607	aDE :
		608	begin
		609	A <= #1 RegBusC;
		610	end
		611
		612	aZI :
		613	begin
		614	if (Inc_WZ == 1'b1 )
		615	begin
		616	A <= #1 TmpAddr + 1;
		617	end
		618	else
		619	begin
		620	A[15:8] <= #1 DI_Reg;
		621	A[7:0] <= #1 TmpAddr[7:0];
		622	end
		623	end // case: aZI
		624
		625	default :
		626	begin
		627	A <= #1 PC;
		628	end
		629	endcase // case(Set_Addr_To)
		630
		631	end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
		632
		633
		634	Save_ALU_r <= #1 Save_ALU;
		635	ALU_Op_r <= #1 ALU_Op;
		636
		637	if (I_CPL == 1'b1 )
		638	begin
		639	// CPL
		640	ACC <= #1 ~ ACC;
		641	F[Flag_Y] <= #1 ~ ACC[5];
		642	F[Flag_H] <= #1 1'b1;
		643	F[Flag_X] <= #1 ~ ACC[3];
		644	F[Flag_N] <= #1 1'b1;
		645	end
		646	if (I_CCF == 1'b1 )
		647	begin
		648	// CCF
		649	F[Flag_C] <= #1 ~ F[Flag_C];
		650	F[Flag_Y] <= #1 ACC[5];
		651	F[Flag_H] <= #1 F[Flag_C];
		652	F[Flag_X] <= #1 ACC[3];
		653	F[Flag_N] <= #1 1'b0;
		654	end
		655	if (I_SCF == 1'b1 )
		656	begin
		657	// SCF
		658	F[Flag_C] <= #1 1'b1;
		659	F[Flag_Y] <= #1 ACC[5];
		660	F[Flag_H] <= #1 1'b0;
		661	F[Flag_X] <= #1 ACC[3];
		662	F[Flag_N] <= #1 1'b0;
		663	end
		664	end // if (T_Res == 1'b1 )
		665
		666
		667	if (tstate[2] && wait_n == 1'b1 )
		668	begin
		669	if (ISet == 2'b01 && mcycle[6] )
		670	begin
		671	IR <= #1 dinst;
		672	end
		673	if (JumpE == 1'b1 )
		674	begin
		675	PC <= #1 PC16;
		676	end
		677	else if (Inc_PC == 1'b1 )
		678	begin
		679	//PC <= #1 PC + 1;
		680	PC <= #1 PC16;
		681	end
		682	if (BTR_r == 1'b1 )
		683	begin
		684	//PC <= #1 PC - 2;
		685	PC <= #1 PC16;
		686	end
		687	if (RstP == 1'b1 )
		688	begin
		689	TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
		690	//TmpAddr <= #1 (others =>1'b0);
		691	//TmpAddr[5:3] <= #1 IR[5:3];
		692	end
		693	end
		694	if (tstate[3] && mcycle[5] )
		695	begin
		696	TmpAddr <= #1 SP16;
		697	end
		698
		699	if ((tstate[2] && wait_n == 1'b1) \|\| (tstate[4] && mcycle[0]) )
		700	begin
		701	if (IncDec_16[2:0] == 3'b111 )
		702	begin
		703	SP <= #1 SP16;
		704	end
		705	end
		706
		707	if (LDSPHL == 1'b1 )
		708	begin
		709	SP <= #1 RegBusC;
		710	end
		711	if (ExchangeAF == 1'b1 )
		712	begin
		713	Ap <= #1 ACC;
		714	ACC <= #1 Ap;
		715	Fp <= #1 F;
		716	F <= #1 Fp;
		717	end
		718	if (ExchangeRS == 1'b1 )
		719	begin
		720	Alternate <= #1 ~ Alternate;
		721	end
		722	end // else: !if(mcycle == 3'b001 && tstate(2) == 1'b0 )
		723
		724
		725	if (tstate[3] )
		726	begin
		727	if (LDZ == 1'b1 )
		728	begin
		729	TmpAddr[7:0] <= #1 DI_Reg;
		730	end
		731	if (LDW == 1'b1 )
		732	begin
		733	TmpAddr[15:8] <= #1 DI_Reg;
		734	end
		735
		736	if (Special_LD[2] == 1'b1 )
		737	begin
		738	case (Special_LD[1:0])
		739	2'b00 :
		740	begin
		741	ACC <= #1 I;
		742	F[Flag_P] <= #1 IntE_FF2;
		743	F[Flag_Z] <= (I == 0);
		744	F[Flag_S] <= I[7];
		745	F[Flag_H] <= 0;
		746	F[Flag_N] <= 0;
		747	end
		748
		749	2'b01 :
		750	begin
		751	`ifdef TV80_REFRESH
		752	ACC <= #1 R;
		753	`else
		754	ACC <= #1 0;
		755	`endif
		756	F[Flag_P] <= #1 IntE_FF2;
		757	F[Flag_Z] <= (I == 0);
		758	F[Flag_S] <= I[7];
		759	F[Flag_H] <= 0;
		760	F[Flag_N] <= 0;
		761	end
		762
		763	2'b10 :
		764	I <= #1 ACC;
		765
		766	`ifdef TV80_REFRESH
		767	default :
		768	R <= #1 ACC;
		769	`else
		770	default : ;
		771	`endif
		772	endcase
		773	end
		774	end // if (tstate == 3 )
		775
		776
		777	if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) \|\| ALU_Op_r == 4'b1001 )
		778	begin
		779	if (Mode == 3 )
		780	begin
		781	F[6] <= #1 F_Out[6];
		782	F[5] <= #1 F_Out[5];
		783	F[7] <= #1 F_Out[7];
		784	if (PreserveC_r == 1'b0 )
		785	begin
		786	F[4] <= #1 F_Out[4];
		787	end
		788	end
		789	else
		790	begin
		791	F[7:1] <= #1 F_Out[7:1];
		792	if (PreserveC_r == 1'b0 )
		793	begin
		794	F[Flag_C] <= #1 F_Out[0];
		795	end
		796	end
		797	end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) \|\| ALU_Op_r == 4'b1001 )
		798
		799	if (T_Res == 1'b1 && I_INRC == 1'b1 )
		800	begin
		801	F[Flag_H] <= #1 1'b0;
		802	F[Flag_N] <= #1 1'b0;
		803	if (DI_Reg[7:0] == 8'b00000000 )
		804	begin
		805	F[Flag_Z] <= #1 1'b1;
		806	end
		807	else
		808	begin
		809	F[Flag_Z] <= #1 1'b0;
		810	end
		811	F[Flag_S] <= #1 DI_Reg[7];
		812	F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
		813	end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
		814
		815
		816	if (tstate[1] && Auto_Wait_t1 == 1'b0 )
		817	begin
		818	dout <= #1 BusB;
		819	if (I_RLD == 1'b1 )
		820	begin
		821	dout[3:0] <= #1 BusA[3:0];
		822	dout[7:4] <= #1 BusB[3:0];
		823	end
		824	if (I_RRD == 1'b1 )
		825	begin
		826	dout[3:0] <= #1 BusB[7:4];
		827	dout[7:4] <= #1 BusA[3:0];
		828	end
		829	end
		830
		831	if (T_Res == 1'b1 )
		832	begin
		833	Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
		834	Read_To_Reg_r[4] <= #1 Read_To_Reg;
		835	if (Read_To_Acc == 1'b1 )
		836	begin
		837	Read_To_Reg_r[3:0] <= #1 4'b0111;
		838	Read_To_Reg_r[4] <= #1 1'b1;
		839	end
		840	end
		841
		842	if (tstate[1] && I_BT == 1'b1 )
		843	begin
		844	F[Flag_X] <= #1 ALU_Q[3];
		845	F[Flag_Y] <= #1 ALU_Q[1];
		846	F[Flag_H] <= #1 1'b0;
		847	F[Flag_N] <= #1 1'b0;
		848	end
		849	if (I_BC == 1'b1 \|\| I_BT == 1'b1 )
		850	begin
		851	F[Flag_P] <= #1 IncDecZ;
		852	end
		853
		854	if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) \|\|
		855	(Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) )
		856	begin
		857	case (Read_To_Reg_r)
		858	5'b10111 :
		859	ACC <= #1 Save_Mux;
		860	5'b10110 :
		861	dout <= #1 Save_Mux;
		862	5'b11000 :
		863	SP[7:0] <= #1 Save_Mux;
		864	5'b11001 :
		865	SP[15:8] <= #1 Save_Mux;
		866	5'b11011 :
		867	F <= #1 Save_Mux;
		868	default : ;
		869	endcase
		870	end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) \|\|...
		871	end // if (ClkEn == 1'b1 )
		872	end // else: !if(reset_n == 1'b0 )
		873	end
		874
		875
		876	//-------------------------------------------------------------------------
		877	//
		878	// BC('), DE('), HL('), IX && IY
		879	//
		880	//-------------------------------------------------------------------------
		881	always @ (posedge clk)
		882	begin
		883	if (ClkEn == 1'b1 )
		884	begin
		885	// Bus A / Write
		886	RegAddrA_r <= #1 { Alternate, Set_BusA_To[2:1] };
		887	if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 )
		888	begin
		889	RegAddrA_r <= #1 { XY_State[1], 2'b11 };
		890	end
		891
		892	// Bus B
		893	RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
		894	if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 )
		895	begin
		896	RegAddrB_r <= #1 { XY_State[1], 2'b11 };
		897	end
		898
		899	// Address from register
		900	RegAddrC <= #1 { Alternate, Set_Addr_To[1:0] };
		901	// Jump (HL), LD SP,HL
		902	if ((JumpXY == 1'b1 \|\| LDSPHL == 1'b1) )
		903	begin
		904	RegAddrC <= #1 { Alternate, 2'b10 };
		905	end
		906	if (((JumpXY == 1'b1 \|\| LDSPHL == 1'b1) && XY_State != 2'b00) \|\| (mcycle[5]) )
		907	begin
		908	RegAddrC <= #1 { XY_State[1], 2'b11 };
		909	end
		910
		911	if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 )
		912	begin
		913	IncDecZ <= #1 F_Out[Flag_Z];
		914	end
		915	if ((tstate[2] \|\| (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 )
		916	begin
		917	if (ID16 == 0 )
		918	begin
		919	IncDecZ <= #1 1'b0;
		920	end
		921	else
		922	begin
		923	IncDecZ <= #1 1'b1;
		924	end
		925	end
		926
		927	RegBusA_r <= #1 RegBusA;
		928	end
		929
		930	end // always @ (posedge clk)
		931
		932
		933	always @(/AUTOSENSE/Alternate or ExchangeDH or IncDec_16
		934	or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
		935	begin
		936	if ((tstate[2] \|\| (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
		937	RegAddrA = { Alternate, IncDec_16[1:0] };
		938	else if ((tstate[2] \|\| (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
		939	RegAddrA = { XY_State[1], 2'b11 };
		940	else if (ExchangeDH == 1'b1 && tstate[3])
		941	RegAddrA = { Alternate, 2'b10 };
		942	else if (ExchangeDH == 1'b1 && tstate[4])
		943	RegAddrA = { Alternate, 2'b01 };
		944	else
		945	RegAddrA = RegAddrA_r;
		946
		947	if (ExchangeDH == 1'b1 && tstate[3])
		948	RegAddrB = { Alternate, 2'b01 };
		949	else
		950	RegAddrB = RegAddrB_r;
		951	end // always @ *
		952
		953
		954	always @(/AUTOSENSE/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
		955	or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
		956	or tstate or wait_n)
		957	begin
		958	RegWEH = 1'b0;
		959	RegWEL = 1'b0;
		960	if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) \|\|
		961	(Save_ALU_r && (ALU_Op_r != 4'b0111)) )
		962	begin
		963	case (Read_To_Reg_r)
		964	5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
		965	begin
		966	RegWEH = ~ Read_To_Reg_r[0];
		967	RegWEL = Read_To_Reg_r[0];
		968	end // UNMATCHED !!
		969	default : ;
		970	endcase // case(Read_To_Reg_r)
		971
		972	end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) \|\|...
		973
		974
		975	if (ExchangeDH && (tstate[3] \|\| tstate[4]) )
		976	begin
		977	RegWEH = 1'b1;
		978	RegWEL = 1'b1;
		979	end
		980
		981	if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) \|\| (tstate[3] && mcycle[0])) )
		982	begin
		983	case (IncDec_16[1:0])
		984	2'b00 , 2'b01 , 2'b10 :
		985	begin
		986	RegWEH = 1'b1;
		987	RegWEL = 1'b1;
		988	end // UNMATCHED !!
		989	default : ;
		990	endcase
		991	end
		992	end // always @ *
		993
		994
		995	always @(/AUTOSENSE/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
		996	or RegBusB or Save_Mux or mcycle or tstate)
		997	begin
		998	RegDIH = Save_Mux;
		999	RegDIL = Save_Mux;
		1000
		1001	if (ExchangeDH == 1'b1 && tstate[3] )
		1002	begin
		1003	RegDIH = RegBusB[15:8];
		1004	RegDIL = RegBusB[7:0];
		1005	end
		1006	else if (ExchangeDH == 1'b1 && tstate[4] )
		1007	begin
		1008	RegDIH = RegBusA_r[15:8];
		1009	RegDIL = RegBusA_r[7:0];
		1010	end
		1011	else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) \|\| (tstate[3] && mcycle[0])) )
		1012	begin
		1013	RegDIH = ID16[15:8];
		1014	RegDIL = ID16[7:0];
		1015	end
		1016	end
		1017
		1018	tv80_reg i_reg
		1019	(
		1020	.clk (clk),
		1021	.CEN (ClkEn),
		1022	.WEH (RegWEH),
		1023	.WEL (RegWEL),
		1024	.AddrA (RegAddrA),
		1025	.AddrB (RegAddrB),
		1026	.AddrC (RegAddrC),
		1027	.DIH (RegDIH),
		1028	.DIL (RegDIL),
		1029	.DOAH (RegBusA[15:8]),
		1030	.DOAL (RegBusA[7:0]),
		1031	.DOBH (RegBusB[15:8]),
		1032	.DOBL (RegBusB[7:0]),
		1033	.DOCH (RegBusC[15:8]),
		1034	.DOCL (RegBusC[7:0])
		1035	);
		1036
		1037	//-------------------------------------------------------------------------
		1038	//
		1039	// Buses
		1040	//
		1041	//-------------------------------------------------------------------------
		1042
		1043	always @ (posedge clk)
		1044	begin
		1045	if (ClkEn == 1'b1 )
		1046	begin
		1047	case (Set_BusB_To)
		1048	4'b0111 :
		1049	BusB <= #1 ACC;
		1050	4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
		1051	begin
		1052	if (Set_BusB_To[0] == 1'b1 )
		1053	begin
		1054	BusB <= #1 RegBusB[7:0];
		1055	end
		1056	else
		1057	begin
		1058	BusB <= #1 RegBusB[15:8];
		1059	end
		1060	end
		1061	4'b0110 :
		1062	BusB <= #1 DI_Reg;
		1063	4'b1000 :
		1064	BusB <= #1 SP[7:0];
		1065	4'b1001 :
		1066	BusB <= #1 SP[15:8];
		1067	4'b1010 :
		1068	BusB <= #1 8'b00000001;
		1069	4'b1011 :
		1070	BusB <= #1 F;
		1071	4'b1100 :
		1072	BusB <= #1 PC[7:0];
		1073	4'b1101 :
		1074	BusB <= #1 PC[15:8];
		1075	4'b1110 :
		1076	BusB <= #1 8'b00000000;
		1077	default :
		1078	BusB <= #1 8'h0;
		1079	endcase
		1080
		1081	case (Set_BusA_To)
		1082	4'b0111 :
		1083	BusA <= #1 ACC;
		1084	4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
		1085	begin
		1086	if (Set_BusA_To[0] == 1'b1 )
		1087	begin
		1088	BusA <= #1 RegBusA[7:0];
		1089	end
		1090	else
		1091	begin
		1092	BusA <= #1 RegBusA[15:8];
		1093	end
		1094	end
		1095	4'b0110 :
		1096	BusA <= #1 DI_Reg;
		1097	4'b1000 :
		1098	BusA <= #1 SP[7:0];
		1099	4'b1001 :
		1100	BusA <= #1 SP[15:8];
		1101	4'b1010 :
		1102	BusA <= #1 8'b00000000;
		1103	default :
		1104	BusA <= #1 8'h0;
		1105	endcase
		1106	end
		1107	end
		1108
		1109	//-------------------------------------------------------------------------
		1110	//
		1111	// Generate external control signals
		1112	//
		1113	//-------------------------------------------------------------------------
		1114	`ifdef TV80_REFRESH
		1115	always @ (posedge clk or negedge reset_n)
		1116	begin
		1117	if (reset_n == 1'b0 )
		1118	begin
		1119	rfsh_n <= #1 1'b1;
		1120	end
		1121	else
		1122	begin
		1123	if (cen == 1'b1 )
		1124	begin
		1125	if (mcycle[0] && ((tstate[2] && wait_n == 1'b1) \|\| tstate[3]) )
		1126	begin
		1127	rfsh_n <= #1 1'b0;
		1128	end
		1129	else
		1130	begin
		1131	rfsh_n <= #1 1'b1;
		1132	end
		1133	end
		1134	end
		1135	end // always @ (posedge clk or negedge reset_n)
		1136	`else // !`ifdef TV80_REFRESH
		1137	assign rfsh_n = 1'b1;
		1138	`endif
		1139
		1140	always @(/AUTOSENSE/BusAck or Halt_FF or I_DJNZ or IntCycle
		1141	or IntE_FF1 or di or iorq_i or mcycle or tstate)
		1142	begin
		1143	mc = mcycle;
		1144	ts = tstate;
		1145	DI_Reg = di;
		1146	halt_n = ~ Halt_FF;
		1147	busak_n = ~ BusAck;
		1148	intcycle_n = ~ IntCycle;
		1149	IntE = IntE_FF1;
		1150	iorq = iorq_i;
		1151	stop = I_DJNZ;
		1152	end
		1153
		1154	//-----------------------------------------------------------------------
		1155	//
		1156	// Syncronise inputs
		1157	//
		1158	//-----------------------------------------------------------------------
		1159
		1160	always @ (posedge clk or negedge reset_n)
		1161	begin : sync_inputs
		1162	if (~reset_n)
		1163	begin
		1164	BusReq_s <= #1 1'b0;
		1165	INT_s <= #1 1'b0;
		1166	NMI_s <= #1 1'b0;
		1167	Oldnmi_n <= #1 1'b0;
		1168	end
		1169	else
		1170	begin
		1171	if (cen == 1'b1 )
		1172	begin
		1173	BusReq_s <= #1 ~ busrq_n;
		1174	INT_s <= #1 ~ int_n;
		1175	if (NMICycle == 1'b1 )
		1176	begin
		1177	NMI_s <= #1 1'b0;
		1178	end
		1179	else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 )
		1180	begin
		1181	NMI_s <= #1 1'b1;
		1182	end
		1183	Oldnmi_n <= #1 nmi_n;
		1184	end
		1185	end
		1186	end
		1187
		1188	//-----------------------------------------------------------------------
		1189	//
		1190	// Main state machine
		1191	//
		1192	//-----------------------------------------------------------------------
		1193
		1194	always @ (posedge clk or negedge reset_n)
		1195	begin
		1196	if (reset_n == 1'b0 )
		1197	begin
		1198	mcycle <= #1 7'b0000001;
		1199	tstate <= #1 7'b0000001;
		1200	Pre_XY_F_M <= #1 3'b000;
		1201	Halt_FF <= #1 1'b0;
		1202	BusAck <= #1 1'b0;
		1203	NMICycle <= #1 1'b0;
		1204	IntCycle <= #1 1'b0;
		1205	IntE_FF1 <= #1 1'b0;
		1206	IntE_FF2 <= #1 1'b0;
		1207	No_BTR <= #1 1'b0;
		1208	Auto_Wait_t1 <= #1 1'b0;
		1209	Auto_Wait_t2 <= #1 1'b0;
		1210	m1_n <= #1 1'b1;
		1211	end
		1212	else
		1213	begin
		1214	if (cen == 1'b1 )
		1215	begin
		1216	if (T_Res == 1'b1 )
		1217	begin
		1218	Auto_Wait_t1 <= #1 1'b0;
		1219	end
		1220	else
		1221	begin
		1222	Auto_Wait_t1 <= #1 Auto_Wait \|\| (iorq_i & ~Auto_Wait_t2);
		1223	end
		1224	Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res;
		1225	No_BTR <= #1 (I_BT && (~ IR[4] \|\| ~ F[Flag_P])) \|\|
		1226	(I_BC && (~ IR[4] \|\| F[Flag_Z] \|\| ~ F[Flag_P])) \|\|
		1227	(I_BTR && (~ IR[4] \|\| F[Flag_Z]));
		1228	if (tstate[2] )
		1229	begin
		1230	if (SetEI == 1'b1 )
		1231	begin
		1232	if (!NMICycle)
		1233	IntE_FF1 <= #1 1'b1;
		1234	IntE_FF2 <= #1 1'b1;
		1235	end
		1236	if (I_RETN == 1'b1 )
		1237	begin
		1238	IntE_FF1 <= #1 IntE_FF2;
		1239	end
		1240	end
		1241	if (tstate[3] )
		1242	begin
		1243	if (SetDI == 1'b1 )
		1244	begin
		1245	IntE_FF1 <= #1 1'b0;
		1246	IntE_FF2 <= #1 1'b0;
		1247	end
		1248	end
		1249	if (IntCycle == 1'b1 \|\| NMICycle == 1'b1 )
		1250	begin
		1251	Halt_FF <= #1 1'b0;
		1252	end
		1253	if (mcycle[0] && tstate[2] && wait_n == 1'b1 )
		1254	begin
		1255	m1_n <= #1 1'b1;
		1256	end
		1257	if (BusReq_s == 1'b1 && BusAck == 1'b1 )
		1258	begin
		1259	end
		1260	else
		1261	begin
		1262	BusAck <= #1 1'b0;
		1263	if (tstate[2] && wait_n == 1'b0 )
		1264	begin
		1265	end
		1266	else if (T_Res == 1'b1 )
		1267	begin
		1268	if (Halt == 1'b1 )
		1269	begin
		1270	Halt_FF <= #1 1'b1;
		1271	end
		1272	if (BusReq_s == 1'b1 )
		1273	begin
		1274	BusAck <= #1 1'b1;
		1275	end
		1276	else
		1277	begin
		1278	tstate <= #1 7'b0000010;
		1279	if (NextIs_XY_Fetch == 1'b1 )
		1280	begin
		1281	mcycle <= #1 7'b0100000;
		1282	Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
		1283	if (IR == 8'b00110110 && Mode == 0 )
		1284	begin
		1285	Pre_XY_F_M <= #1 3'b010;
		1286	end
		1287	end
		1288	else if ((mcycle[6]) \|\| (mcycle[5] && Mode == 1 && ISet != 2'b01) )
		1289	begin
		1290	mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
		1291	end
		1292	else if ((last_mcycle) \|\|
		1293	No_BTR == 1'b1 \|\|
		1294	(mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) )
		1295	begin
		1296	m1_n <= #1 1'b0;
		1297	mcycle <= #1 7'b0000001;
		1298	IntCycle <= #1 1'b0;
		1299	NMICycle <= #1 1'b0;
		1300	if (NMI_s == 1'b1 && Prefix == 2'b00 )
		1301	begin
		1302	NMICycle <= #1 1'b1;
		1303	IntE_FF1 <= #1 1'b0;
		1304	end
		1305	else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 )
		1306	begin
		1307	IntCycle <= #1 1'b1;
		1308	IntE_FF1 <= #1 1'b0;
		1309	IntE_FF2 <= #1 1'b0;
		1310	end
		1311	end
		1312	else
		1313	begin
		1314	mcycle <= #1 { mcycle[5:0], mcycle[6] };
		1315	end
		1316	end
		1317	end
		1318	else
		1319	begin // verilog has no "nor" operator
		1320	if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
		1321	~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) )
		1322	begin
		1323	tstate <= #1 { tstate[5:0], tstate[6] };
		1324	end
		1325	end
		1326	end
		1327	if (tstate[0])
		1328	begin
		1329	m1_n <= #1 1'b0;
		1330	end
		1331	end
		1332	end
		1333	end
		1334
		1335	always @(/AUTOSENSE/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
		1336	or RegBusA or RegBusC or SP or tstate)
		1337	begin
		1338	if (JumpE == 1'b1 )
		1339	begin
		1340	PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
		1341	end
		1342	else if (BTR_r == 1'b1 )
		1343	begin
		1344	PC16_B = -2;
		1345	end
		1346	else
		1347	begin
		1348	PC16_B = 1;
		1349	end
		1350
		1351	if (tstate[3])
		1352	begin
		1353	SP16_A = RegBusC;
		1354	SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
		1355	end
		1356	else
		1357	begin
		1358	// suspect that ID16 and SP16 could be shared
		1359	SP16_A = SP;
		1360
		1361	if (IncDec_16[3] == 1'b1)
		1362	SP16_B = -1;
		1363	else
		1364	SP16_B = 1;
		1365	end
		1366
		1367	if (IncDec_16[3])
		1368	ID16_B = -1;
		1369	else
		1370	ID16_B = 1;
		1371
		1372	ID16 = RegBusA + ID16_B;
		1373	PC16 = PC + PC16_B;
		1374	SP16 = SP16_A + SP16_B;
		1375	end // always @ *
		1376
		1377
		1378	always @(/AUTOSENSE/IntCycle or NMICycle or mcycle)
		1379	begin
		1380	Auto_Wait = 1'b0;
		1381	if (IntCycle == 1'b1 \|\| NMICycle == 1'b1 )
		1382	begin
		1383	if (mcycle[0] )
		1384	begin
		1385	Auto_Wait = 1'b1;
		1386	end
		1387	end
		1388	end // always @ *
		1389
		1390	endmodule // T80
		1391

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(root)//fpga/current/tb/z80/tv80_core.v – Rev 92