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| Rev | Author | Line No. | Line |
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| 92 | lvd | 1 | // |
| 2 | // TV80 8-Bit Microprocessor Core |
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| 3 | // Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
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| 4 | // |
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| 5 | // Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) |
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| 6 | // |
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| 7 | // Permission is hereby granted, free of charge, to any person obtaining a |
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| 8 | // copy of this software and associated documentation files (the "Software"), |
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| 9 | // to deal in the Software without restriction, including without limitation |
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| 10 | // the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 11 | // and/or sell copies of the Software, and to permit persons to whom the |
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| 12 | // Software is furnished to do so, subject to the following conditions: |
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| 13 | // |
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| 14 | // The above copyright notice and this permission notice shall be included |
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| 15 | // in all copies or substantial portions of the Software. |
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| 16 | // |
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| 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 18 | // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 19 | // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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| 20 | // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
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| 21 | // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 22 | // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 23 | // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 24 | |||
| 25 | module tv80_reg (/*AUTOARG*/ |
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| 26 | // Outputs |
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| 27 | DOBH, DOAL, DOCL, DOBL, DOCH, DOAH, |
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| 28 | // Inputs |
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| 29 | AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL |
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| 30 | ); |
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| 31 | input [2:0] AddrC; |
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| 32 | output [7:0] DOBH; |
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| 33 | input [2:0] AddrA; |
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| 34 | input [2:0] AddrB; |
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| 35 | input [7:0] DIH; |
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| 36 | output [7:0] DOAL; |
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| 37 | output [7:0] DOCL; |
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| 38 | input [7:0] DIL; |
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| 39 | output [7:0] DOBL; |
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| 40 | output [7:0] DOCH; |
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| 41 | output [7:0] DOAH; |
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| 42 | input clk, CEN, WEH, WEL; |
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| 43 | |||
| 44 | reg [7:0] RegsH [0:7]; |
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| 45 | reg [7:0] RegsL [0:7]; |
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| 46 | |||
| 47 | always @(posedge clk) |
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| 48 | begin |
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| 49 | if (CEN) |
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| 50 | begin |
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| 51 | if (WEH) RegsH[AddrA] <= DIH; |
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| 52 | if (WEL) RegsL[AddrA] <= DIL; |
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| 53 | end |
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| 54 | end |
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| 55 | |||
| 56 | assign DOAH = RegsH[AddrA]; |
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| 57 | assign DOAL = RegsL[AddrA]; |
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| 58 | assign DOBH = RegsH[AddrB]; |
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| 59 | assign DOBL = RegsL[AddrB]; |
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| 60 | assign DOCH = RegsH[AddrC]; |
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| 61 | assign DOCL = RegsL[AddrC]; |
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| 62 | |||
| 63 | // break out ram bits for waveform debug |
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| 64 | // synopsys translate_off |
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| 65 | wire [7:0] B = RegsH[0]; |
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| 66 | wire [7:0] C = RegsL[0]; |
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| 67 | wire [7:0] D = RegsH[1]; |
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| 68 | wire [7:0] E = RegsL[1]; |
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| 69 | wire [7:0] H = RegsH[2]; |
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| 70 | wire [7:0] L = RegsL[2]; |
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| 71 | |||
| 72 | wire [15:0] IX = { RegsH[3], RegsL[3] }; |
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| 73 | wire [15:0] IY = { RegsH[7], RegsL[7] }; |
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| 74 | // synopsys translate_on |
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| 75 | |||
| 76 | endmodule |
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| 77 |