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| Rev | Author | Line No. | Line |
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| 92 | lvd | 1 | `timescale 1ps/1ps |
| 2 | |||
| 3 | // |
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| 4 | // TV80 8-Bit Microprocessor Core |
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| 5 | // Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
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| 6 | // |
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| 7 | // Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org) |
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| 8 | // |
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| 9 | // Permission is hereby granted, free of charge, to any person obtaining a |
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| 10 | // copy of this software and associated documentation files (the "Software"), |
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| 11 | // to deal in the Software without restriction, including without limitation |
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| 12 | // the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 13 | // and/or sell copies of the Software, and to permit persons to whom the |
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| 14 | // Software is furnished to do so, subject to the following conditions: |
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| 15 | // |
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| 16 | // The above copyright notice and this permission notice shall be included |
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| 17 | // in all copies or substantial portions of the Software. |
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| 18 | // |
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| 19 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 20 | // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 21 | // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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| 22 | // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
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| 23 | // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 24 | // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 25 | // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 26 | |||
| 27 | module tv80s (/*AUTOARG*/ |
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| 28 | // Outputs |
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| 29 | m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, |
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| 30 | // Inputs |
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| 31 | reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di |
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| 32 | ); |
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| 33 | |||
| 34 | parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB |
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| 35 | parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2 |
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| 36 | parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle |
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| 37 | |||
| 38 | |||
| 39 | input reset_n; |
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| 40 | input clk; |
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| 41 | input wait_n; |
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| 42 | input int_n; |
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| 43 | input nmi_n; |
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| 44 | input busrq_n; |
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| 45 | output m1_n; |
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| 46 | output mreq_n; |
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| 47 | output iorq_n; |
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| 48 | output rd_n; |
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| 49 | output wr_n; |
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| 50 | output rfsh_n; |
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| 51 | output halt_n; |
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| 52 | output busak_n; |
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| 53 | output [15:0] A; |
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| 54 | input [7:0] di; |
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| 55 | output [7:0] dout; |
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| 56 | |||
| 57 | reg mreq_n; |
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| 58 | reg iorq_n; |
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| 59 | reg rd_n; |
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| 60 | reg wr_n; |
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| 61 | |||
| 62 | wire cen; |
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| 63 | wire intcycle_n; |
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| 64 | wire no_read; |
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| 65 | wire write; |
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| 66 | wire iorq; |
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| 67 | reg [7:0] di_reg; |
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| 68 | wire [6:0] mcycle; |
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| 69 | wire [6:0] tstate; |
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| 70 | |||
| 71 | assign cen = 1; |
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| 72 | |||
| 73 | tv80_core #(Mode, IOWait) i_tv80_core |
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| 74 | ( |
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| 75 | .cen (cen), |
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| 76 | .m1_n (m1_n), |
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| 77 | .iorq (iorq), |
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| 78 | .no_read (no_read), |
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| 79 | .write (write), |
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| 80 | .rfsh_n (rfsh_n), |
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| 81 | .halt_n (halt_n), |
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| 82 | .wait_n (wait_n), |
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| 83 | .int_n (int_n), |
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| 84 | .nmi_n (nmi_n), |
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| 85 | .reset_n (reset_n), |
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| 86 | .busrq_n (busrq_n), |
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| 87 | .busak_n (busak_n), |
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| 88 | .clk (clk), |
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| 89 | .IntE (), |
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| 90 | .stop (), |
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| 91 | .A (A), |
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| 92 | .dinst (di), |
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| 93 | .di (di_reg), |
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| 94 | .dout (dout), |
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| 95 | .mc (mcycle), |
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| 96 | .ts (tstate), |
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| 97 | .intcycle_n (intcycle_n) |
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| 98 | ); |
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| 99 | |||
| 100 | always @(posedge clk or negedge reset_n) |
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| 101 | begin |
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| 102 | if (!reset_n) |
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| 103 | begin |
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| 104 | rd_n <= #1 1'b1; |
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| 105 | wr_n <= #1 1'b1; |
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| 106 | iorq_n <= #1 1'b1; |
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| 107 | mreq_n <= #1 1'b1; |
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| 108 | di_reg <= #1 0; |
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| 109 | end |
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| 110 | else |
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| 111 | begin |
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| 112 | rd_n <= #1 1'b1; |
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| 113 | wr_n <= #1 1'b1; |
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| 114 | iorq_n <= #1 1'b1; |
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| 115 | mreq_n <= #1 1'b1; |
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| 116 | if (mcycle[0]) |
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| 117 | begin |
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| 118 | if (tstate[1] || (tstate[2] && wait_n == 1'b0)) |
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| 119 | begin |
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| 120 | rd_n <= #1 ~ intcycle_n; |
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| 121 | mreq_n <= #1 ~ intcycle_n; |
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| 122 | iorq_n <= #1 intcycle_n; |
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| 123 | end |
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| 124 | `ifdef TV80_REFRESH |
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| 125 | if (tstate[3]) |
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| 126 | mreq_n <= #1 1'b0; |
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| 127 | `endif |
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| 128 | end // if (mcycle[0]) |
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| 129 | else |
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| 130 | begin |
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| 131 | if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0) |
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| 132 | begin |
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| 133 | rd_n <= #1 1'b0; |
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| 134 | iorq_n <= #1 ~ iorq; |
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| 135 | mreq_n <= #1 iorq; |
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| 136 | end |
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| 137 | if (T2Write == 0) |
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| 138 | begin |
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| 139 | if (tstate[2] && write == 1'b1) |
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| 140 | begin |
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| 141 | wr_n <= #1 1'b0; |
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| 142 | iorq_n <= #1 ~ iorq; |
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| 143 | mreq_n <= #1 iorq; |
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| 144 | end |
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| 145 | end |
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| 146 | else |
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| 147 | begin |
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| 148 | if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1) |
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| 149 | begin |
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| 150 | wr_n <= #1 1'b0; |
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| 151 | iorq_n <= #1 ~ iorq; |
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| 152 | mreq_n <= #1 iorq; |
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| 153 | end |
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| 154 | end // else: !if(T2write == 0) |
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| 155 | |||
| 156 | end // else: !if(mcycle[0]) |
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| 157 | |||
| 158 | if (tstate[2] && wait_n == 1'b1) |
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| 159 | di_reg <= #1 di; |
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| 160 | end // else: !if(!reset_n) |
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| 161 | end // always @ (posedge clk or negedge reset_n) |
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| 162 | |||
| 163 | endmodule // t80s |
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| 164 |