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// part of NeoGS project (c) 2007-2008 NedoPC
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//
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// memmap is memory mapper for NGS. Physical memory divided in 16kb pages.
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// At (a15=0,a14=0) there is always zero page of MEM, at (a15=0,a14=1) there is
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// always third page of RAM, at (a15=1,a14=0) there is page of MEM determined by
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// mode_pg0 input bus, at (a15=1,a14=1) - page of MEM determined by mode_pg1 input.
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// When mode_norom=0, MEM is ROM, otherwise MEM is RAM.
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// When mode_ramro=1, zero and first pages of RAM are read-only.
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// Memory addressed by mema14..mema18 (total 512kb) and then by either
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// romcs_n (only 512kb of ROM) or ram0cs_n..ram3cs_n (2Mb of RAM).
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// Memory decoding is static - it depends on only a14,a15 and mode_pg0,1 inputs.
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// memoe_n and memwe_n generated from only mreq_n, rd_n and wr_n with the
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// exception of read-only page of RAM (no memwe_n). ROM is always read/write (flash).
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module memmap(
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        a15,a14, // Z80 address signals
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        mreq_n, // Z80 bus control signals
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        rd_n,   //
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        wr_n,   //
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        mema14,mema15, // memory addresses
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        mema16,mema17, //
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        mema18,        // (512kB max)
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        ram0cs_n, // four RAM /CS'es
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        ram1cs_n, //
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        ram2cs_n, //
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        ram3cs_n, // (total 512kb * 4 = 2Mb)
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        romcs_n, // ROM (flash) /CS
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        memoe_n, // memory /OE and /WE
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        memwe_n, //
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        mode_ramro, // 1 - zero page (32k) of ram is R/O
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        mode_norom, // 0 - ROM instead of RAM at everything except $4000-$7FFF
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        mode_pg0,   // page at $8000-$BFFF
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        mode_pg1    // page at $C000-$FFFF (128x16kb = 2Mb max)
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);
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// inputs and outputs
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        input a15,a14;
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        input mreq_n,rd_n,wr_n;
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        output reg mema14,mema15,mema16,mema17,mema18;
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        output reg ram0cs_n,ram1cs_n,ram2cs_n,ram3cs_n;
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        output reg romcs_n;
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        output reg memoe_n,memwe_n;
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        input mode_ramro,mode_norom;
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        input [6:0] mode_pg0,mode_pg1;
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// internal vars and regs
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        reg [6:0] high_addr;
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// addresses mapping
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        always @*
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        begin
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        case( {a15,a14} )
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                        2'b00: // $0000-$3FFF
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                                high_addr <= 7'b0000000;
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                        2'b01: // $4000-$7FFF
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                                high_addr <= 7'b0000011;
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                        2'b10: // $8000-$BFFF
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                                high_addr <= mode_pg0;
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                        2'b11: // $C000-$FFFF
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                                high_addr <= mode_pg1;
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        endcase
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        end
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// memory addresses
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        always @*
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        begin
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                { mema18,mema17,mema16,mema15,mema14 } <= high_addr[4:0];
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        end
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// memory chip selects
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        always @*
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        begin
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                if( (mode_norom==1'b0) && ( {a15,a14}!=2'b01 ) ) // ROM selected
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                begin
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                        romcs_n <= 1'b0;
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                        ram0cs_n <= 1'b1;
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                        ram1cs_n <= 1'b1;
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                        ram2cs_n <= 1'b1;
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                        ram3cs_n <= 1'b1;
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                end
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                else // RAM
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                begin
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                        romcs_n <= 1'b1;
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                        ram0cs_n <= ( high_addr[6:5]==2'b00 ) ? 1'b0 : 1'b1;
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                        ram1cs_n <= ( high_addr[6:5]==2'b01 ) ? 1'b0 : 1'b1;
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                        ram2cs_n <= ( high_addr[6:5]==2'b10 ) ? 1'b0 : 1'b1;
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                        ram3cs_n <= ( high_addr[6:5]==2'b11 ) ? 1'b0 : 1'b1;
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                end
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        end
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// memory /OE and /WE
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        always @*
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        begin
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                memoe_n <= mreq_n | rd_n;
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                if( (high_addr[6:1] == 6'd0) && (mode_ramro==1'b1) && (mode_norom==1'b1) ) // R/O
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                        memwe_n <= 1'b1;
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                else // no R/O
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                        memwe_n <= mreq_n | wr_n;
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        end
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endmodule
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