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Rev | Author | Line No. | Line |
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668 | lvd | 1 | // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014 |
425 | lvd | 2 | // |
3 | // frame INT generation |
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4 | |||
668 | lvd | 5 | /* |
6 | This file is part of ZX-Evo Base Configuration firmware. |
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7 | |||
8 | ZX-Evo Base Configuration firmware is free software: |
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9 | you can redistribute it and/or modify it under the terms of |
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10 | the GNU General Public License as published by |
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11 | the Free Software Foundation, either version 3 of the License, or |
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12 | (at your option) any later version. |
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13 | |||
14 | ZX-Evo Base Configuration firmware is distributed in the hope that |
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15 | it will be useful, but WITHOUT ANY WARRANTY; without even |
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16 | the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
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17 | See the GNU General Public License for more details. |
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18 | |||
19 | You should have received a copy of the GNU General Public License |
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20 | along with ZX-Evo Base Configuration firmware. |
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21 | If not, see <http://www.gnu.org/licenses/>. |
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22 | */ |
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23 | |||
30 | lvd | 24 | `include "../include/tune.v" |
25 | |||
425 | lvd | 26 | module zint |
27 | ( |
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28 | input wire fclk, |
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4 | lvd | 29 | |
425 | lvd | 30 | input wire zpos, |
31 | input wire zneg, |
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4 | lvd | 32 | |
425 | lvd | 33 | input wire int_start, |
34 | |||
35 | input wire iorq_n, |
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36 | input wire m1_n, |
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37 | |||
651 | lvd | 38 | input wire wait_n, |
39 | |||
425 | lvd | 40 | output reg int_n |
4 | lvd | 41 | ); |
42 | |||
43 | wire intend; |
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44 | |||
438 | lvd | 45 | reg [9:0] intctr; |
4 | lvd | 46 | |
651 | lvd | 47 | reg [1:0] wr; |
4 | lvd | 48 | |
30 | lvd | 49 | |
50 | `ifdef SIMULATE |
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51 | initial |
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52 | begin |
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438 | lvd | 53 | intctr = 10'b1100000000; |
30 | lvd | 54 | end |
55 | `endif |
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56 | |||
651 | lvd | 57 | always @(posedge fclk) |
58 | wr[1:0] <= { wr[0], wait_n }; |
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30 | lvd | 59 | |
4 | lvd | 60 | always @(posedge fclk) |
61 | begin |
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62 | if( int_start ) |
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438 | lvd | 63 | intctr <= 10'd0; |
651 | lvd | 64 | else if( !intctr[9:8] && wr[1] ) |
438 | lvd | 65 | intctr <= intctr + 10'd1; |
4 | lvd | 66 | end |
67 | |||
68 | |||
438 | lvd | 69 | assign intend = intctr[9:8] || ( (!iorq_n) && (!m1_n) && zneg ); |
4 | lvd | 70 | |
71 | |||
425 | lvd | 72 | always @(posedge fclk) |
4 | lvd | 73 | begin |
425 | lvd | 74 | if( int_start ) |
4 | lvd | 75 | int_n <= 1'b0; |
76 | else if( intend ) |
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425 | lvd | 77 | int_n <= 1'bZ; |
4 | lvd | 78 | end |
79 | |||
80 | |||
81 | |||
82 | |||
83 | |||
84 | endmodule |
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85 |