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Rev | Author | Line No. | Line |
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1029 | chrv | 1 | ; |
2 | ;-------------------------------------- |
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3 | ; |
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4 | .EQU RTC_ADDRESS =$A0 ; Address of PCF8583 RTC chip. |
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5 | .EQU RTC_COMMON_MODE_REG =$FE ; RTC's register for common modes. |
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6 | ;.EQU MODE_VGA =$01 ; VGA mode (0 - not set/1 - set). |
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7 | |||
8 | .EQU TW_START =$08 |
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9 | .EQU TW_REP_START =$10 |
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10 | .EQU TW_MT_SLA_ACK =$18 |
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11 | .EQU TW_MT_DATA_ACK =$28 |
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12 | .EQU TW_MR_SLA_ACK =$40 |
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13 | |||
14 | .MACRO TW_SEND_STOP |
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15 | LDI TEMP,(1<<TWINT)|(1<<TWEN)|(1<<TWSTO) |
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16 | STS TWCR,TEMP |
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17 | .ENDMACRO |
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18 | ; |
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19 | ;-------------------------------------- |
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20 | ;out: DATA == mode (bit.0 - CLR == TV mode, SET == VGA mode) |
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21 | NVRAM_READ_MODE: |
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22 | ;init i2c |
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23 | ;SCL frequency = CPU clk/ ( 16 + 2* (TWBR) * 4^(TWPS) ) |
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24 | ;11052000 / (16 + 2*48 ) = 98678,5Hz (100000Hz recommended for PCF8583) |
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25 | STS TWSR,NULL |
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26 | LDI TEMP,48 |
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27 | STS TWBR,TEMP |
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28 | |||
29 | ;reset RTC |
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30 | ;write 0 to control/status register [0] on PCF8583 |
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31 | |||
32 | RCALL TW_SEND_START |
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33 | ANDI DATA,TW_START|TW_REP_START |
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34 | BREQ RTC_ERROR1 |
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35 | |||
36 | LDI DATA,RTC_ADDRESS |
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37 | RCALL TW_SEND_ADDR |
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38 | CPI DATA,TW_MT_SLA_ACK |
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39 | BRNE RTC_ERROR1 |
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40 | |||
41 | LDI DATA,0 |
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42 | RCALL TW_SEND_DATA |
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43 | CPI DATA,TW_MT_DATA_ACK |
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44 | BRNE RTC_ERROR1 |
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45 | |||
46 | LDI DATA,0 |
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47 | RCALL TW_SEND_DATA |
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48 | RTC_ERROR1: |
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49 | TW_SEND_STOP |
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50 | |||
51 | ;restore mode register from NVRAM |
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52 | |||
53 | RCALL TW_SEND_START |
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54 | ANDI DATA,TW_START|TW_REP_START |
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55 | BREQ RTC_ERROR2 |
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56 | |||
57 | LDI DATA,RTC_ADDRESS |
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58 | RCALL TW_SEND_ADDR |
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59 | CPI DATA,TW_MT_SLA_ACK |
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60 | BRNE RTC_ERROR2 |
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61 | |||
62 | LDI DATA,RTC_COMMON_MODE_REG |
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63 | RCALL TW_SEND_DATA |
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64 | CPI DATA,TW_MT_DATA_ACK |
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65 | BRNE RTC_ERROR2 |
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66 | |||
67 | RCALL TW_SEND_START |
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68 | CPI DATA,TW_REP_START |
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69 | |||
70 | LDI DATA,RTC_ADDRESS|$01 |
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71 | RCALL TW_SEND_ADDR |
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72 | CPI DATA,TW_MR_SLA_ACK |
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73 | BRNE RTC_ERROR2 |
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74 | |||
75 | RCALL TW_READ_DATA |
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76 | RJMP RTC_OK2 |
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77 | RTC_ERROR2: |
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78 | LDI DATA,0 |
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79 | RTC_OK2: |
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80 | TW_SEND_STOP |
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81 | RET |
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82 | ; |
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83 | ;-------------------------------------- |
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84 | ;out: DATA == i2c status |
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85 | TW_SEND_START: |
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86 | ;start transmit |
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87 | LDI DATA,(1<<TWINT)|(1<<TWSTA)|(1<<TWEN) |
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88 | STS TWCR,DATA |
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89 | ;wait for flag |
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90 | TW_SS_WAIT: |
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91 | LDS DATA,TWCR |
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92 | SBRS DATA,TWINT |
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93 | RJMP TW_SS_WAIT |
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94 | ;return status |
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95 | LDS DATA,TWSR |
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96 | ANDI DATA,$F8 |
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97 | RET |
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98 | ; |
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99 | ;-------------------------------------- |
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100 | ;in: DATA == data/address |
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101 | ;out: DATA == i2c status |
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102 | TW_SEND_ADDR: |
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103 | TW_SEND_DATA: |
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104 | ;set data/address |
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105 | STS TWDR,DATA |
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106 | ;enable transmit |
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107 | LDI DATA,(1<<TWINT)|(1<<TWEN) |
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108 | STS TWCR,DATA |
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109 | ;wait for end transmit |
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110 | TW_SD_WAIT: |
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111 | LDS DATA,TWCR |
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112 | SBRS DATA,TWINT |
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113 | RJMP TW_SD_WAIT |
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114 | ;return status |
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115 | LDS DATA,TWSR |
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116 | ANDI DATA,$F8 |
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117 | RET |
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118 | ; |
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119 | ;-------------------------------------- |
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120 | ;out: DATA == data |
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121 | TW_READ_DATA: |
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122 | ;enable transmit |
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123 | LDI DATA,(1<<TWINT)|(1<<TWEN) |
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124 | STS TWCR,DATA |
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125 | ;wait for flag set |
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126 | TW_RD_WAIT: |
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127 | LDS DATA,TWCR |
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128 | SBRS DATA,TWINT |
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129 | RJMP TW_RD_WAIT |
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130 | ;get data |
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131 | LDS DATA,TWDR |
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132 | ;NOT return status |
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133 | ; LDS DATA,TWSR |
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134 | ; ANDI DATA,$F8 |
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135 | RET |
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136 | ; |
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137 | ;-------------------------------------- |
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138 | ; |