WebSVN – pentevo – Blame – //tools/asl/asl-current/include/avr/reg8535.inc

Rev	Author	Line No.	Line
1186	savelij	1	ifndef __reg8535inc
		2	__reg8535inc equ 1
		3	save
		4	listing off ; kein Listing ueber diesen File
		5
		6	;****************************************************************************
		7	;* *
		8	;* AS 1.42 - File REG8535.INC *
		9	;* *
		10	;* Contains Bit & Register Definitions for AT90S8535 *
		11	;* *
		12	;****************************************************************************
		13
		14	;----------------------------------------------------------------------------
		15	; Memory Limits
		16
		17	E2END equ 511
		18	RAMSTART equ 0x60,data
		19	RAMEND equ 0x25f,data
		20	FLASHEND label 0x1fff
		21
		22	;----------------------------------------------------------------------------
		23	; Chip Configuration
		24
		25	MCUCR port 0x35 ; MCU General Control Register
		26	SM avrbit MCUCR,4 ; Choose Idle/Power-Down Mode
		27	SE avrbit MCUCR,5 ; Enable Sleep Mode
		28
		29	MCUSR port 0x34 ; MCU General Status Register
		30	EXTRF avrbit MCUSR,1 ; External Reset Occured
		31	PORF avrbit MCUSR,0 ; Power-on Reset Occured
		32
		33
		34	;----------------------------------------------------------------------------
		35	; EEPROM
		36
		37	include "ee90.inc"
		38
		39	EEMWE avrbit EECR,2 ; EEPROM Master Write Enable
		40	EERIE avrbit EECR,3 ; EEPROM Interrupt Enable
		41
		42	;----------------------------------------------------------------------------
		43	; GPIO
		44
		45	PINA port 0x19 ; Port A @ 0x19 (IO) ff.
		46	PINB port 0x16 ; Port B @ 0x16 (IO) ff.
		47	PINC port 0x13 ; Port C @ 0x13 (IO) ff.
		48	PIND port 0x10 ; Port D @ 0x10 (IO) ff.
		49
		50	;----------------------------------------------------------------------------
		51	; Interrupt Vectors
		52
		53	enumconf 1,code
		54	enum INT0_vect=1 ; External Interrupt Request 0
		55	nextenum INT1_vect ; External Interrupt Request 1
		56	nextenum TIMER2_COMP ; Timer/Counter 2 Compare Match
		57	nextenum TIMER2_OVF ; Timer/Counter 2 Overflow
		58	nextenum TIMER1_CAPT_vect ; Timer/Counter 1 Capture Event
		59	nextenum TIMER1_COMPA_vect ; Timer/Counter 1 Compare Match A
		60	nextenum TIMER1_COMPB_vect ; Timer/Counter 1 Compare Match B
		61	nextenum TIMER1_OVF_vect ; Timer/Counter 1 Overflow
		62	nextenum TIMER0_OVF_vect ; Timer/Counter 0 Overflow
		63	nextenum SPI_STC_vect ; SPI Serial Transfer Complete
		64	nextenum UART_RX_vect ; UART Rx Complete
		65	nextenum UART_UDRE_vect ; UART Data Register Empty
		66	nextenum UART_TX_vect ; UART Tx Complete
		67	nextenum ADC_vect ; A/D Converter
		68	nextenum EE_RDY_vect ; EEPROM Ready
		69	nextenum ANA_COMP_vect ; Analog Comparator
		70
		71	;----------------------------------------------------------------------------
		72	; External Interrupts
		73
		74	; bits in MCUCR
		75	ISC00 avrbit MCUCR,0 ; External Interrupt 0 Sense Control
		76	ISC01 avrbit MCUCR,1
		77	ISC10 avrbit MCUCR,2 ; External Interrupt 1 Sense Control
		78	ISC11 avrbit MCUCR,3
		79
		80	GIMSK port 0x3b ; General Interrupt Mask Register
		81	INT0 avrbit GIMSK,6 ; Enable External Interrupt 0
		82	INT1 avrbit GIMSK,7 ; Enable External Interrupt 1
		83
		84	GIFR port 0x3a ; General Interrupt Flag Register
		85	INTF0 avrbit GIFR,6 ; External Interrupt 0 Occured
		86	INTF1 avrbit GIFR,7 ; External Interrupt 1 Occured
		87
		88	;----------------------------------------------------------------------------
		89	; Timers
		90
		91	TCCR0 port 0x33 ; Timer/Counter 0 Control Register
		92	CS00 avrbit TCCR0,0 ; Timer/Counter 0 Clock Select
		93	CS01 avrbit TCCR0,1
		94	CS02 avrbit TCCR0,2
		95	TCNT0 port 0x32 ; Timer/Counter 0 Value
		96
		97	TCCR1A port 0x2f ; Timer/Counter 1 Control Register A
		98	PWM10 avrbit TCCR1A,0 ; Mode of Pulse Width Modulator
		99	PWM11 avrbit TCCR1A,1
		100	COM1B0 avrbit TCCR1A,4 ; Timer/Counter 1 Compare Mode B
		101	COM1B1 avrbit TCCR1A,5
		102	COM1A0 avrbit TCCR1A,6 ; Timer/Counter 1 Compare Mode A
		103	COM1A1 avrbit TCCR1A,7
		104	TCCR1B port 0x2e ; Timer/Counter 1 Control Register B
		105	CS10 avrbit TCCR1B,0 ; Timer/Counter 1 Clock Select
		106	CS11 avrbit TCCR1B,1
		107	CS12 avrbit TCCR1B,2
		108	CTC1 avrbit TCCR1B,3 ; Clear after Equality?
		109	ICES1 avrbit TCCR1B,6 ; Capture Slope Selection
		110	ICNC1 avrbit TCCR1B,7 ; Capture Noise Filter
		111	TCNT1L port 0x2c ; Timer/Counter 1 Value LSB
		112	TCNT1H port 0x2d ; Timer/Counter 1 Value MSB
		113	OCR1AL port 0x2a ; Timer/Counter 1 Output Compare Value A LSB
		114	OCR1AH port 0x2b ; Timer/Counter 1 Output Compare Value A MSB
		115	OCR1BL port 0x28 ; Timer/Counter 1 Output Compare Value B LSB
		116	OCR1BH port 0x29 ; Timer/Counter 1 Output Compare Value B MSB
		117	ICR1L port 0x27 ; Timer/Counter 1 Input Capture Value LSB
		118	ICR1H port 0x26 ; Timer/Counter 1 Input Capture Value MSB
		119
		120	TCCR2 port 0x25 ; Timer/Counter 2 Control Register
		121	CS20 avrbit TCCR2,0 ; Timer/Counter 2 Clock Select
		122	CS21 avrbit TCCR2,1
		123	CS22 avrbit TCCR2,2
		124	CTC2 avrbit TCCR2,3 ; Timer/Counter 2 Clear Timer/Counter on Compare Match
		125	COM20 avrbit TCCR2,4 ; Timer/Counter 2 Compare Output Mode
		126	COM21 avrbit TCCR2,5
		127	PWM2 avrbit TCCR2,6 ; Timer/Counter 2 Pulse Width Modulator Enable
		128	TCNT2 port 0x24 ; Timer/Counter 2 Value
		129	OCR2 port 0x23 ; Timer/Counter 2 Output Compare Value
		130
		131	TIMSK port 0x39 ; Timer Interrupt Mask Register
		132	TOIE0 avrbit TIMSK,0 ; Timer/Counter 0 Overflow Interrupt Enable
		133	TOIE1 avrbit TIMSK,2 ; Timer/Counter 1 Overflow Interrupt Enable
		134	OCIE1B avrbit TIMSK,3 ; Timer/Counter 1 Output Compare Interrupt B Enable
		135	OCIE1A avrbit TIMSK,4 ; Timer/Counter 1 Output Compare Interrupt A Enable
		136	TICIE1 avrbit TIMSK,5 ; Timer/Counter 1 Input Capture Interrupt Enable
		137	TOIE2 avrbit TIMSK,6 ; Timer/Counter 2 Overflow Interrupt Enable
		138	OCIE2 avrbit TIMSK,7 ; Timer/Counter 2 Output Compare Interrupt Enable
		139
		140	TIFR port 0x38 ; Timer Interrupt Flag Register
		141
		142	ASSR port 0x22 ; Asynchronous Status Register
		143	AS2 avrbit ASSR,3 ; Asynchronous Timer/Counter2
		144	TCN2UB avrbit ASSR,2 ; Timer/Counter2 Update Busy
		145	OCR2UB avrbit ASSR,1 ; Output Compare Register 2 Update Busy
		146	TCR2UB avrbit ASSR,0 ; Timer/Counter Control Register 2 Update Busy
		147
		148	;----------------------------------------------------------------------------
		149	; Watchdog Timer
		150
		151	include "wdm21.inc"
		152	WDTOE avrbit WDTCR,4 ; Turn-Off Enable
		153
		154	;----------------------------------------------------------------------------
		155	; UART
		156
		157	include "uart90.inc"
		158
		159	;----------------------------------------------------------------------------
		160	; SPI
		161
		162	include "spi90.inc"
		163
		164	;----------------------------------------------------------------------------
		165	; Analog Comparator
		166
		167	include "ac90.inc"
		168
		169	;----------------------------------------------------------------------------
		170	; A/D Converter
		171
		172	ADMUX port 0x07 ; Multiplexer Selection
		173	MUX2 avrbit ADMUX,2 ; Analog Channel Select Bits
		174	MUX1 avrbit ADMUX,1
		175	MUX0 avrbit ADMUX,0
		176
		177	ADCSR port 0x06 ; Control/Status Register
		178	ADEN avrbit ADCSR,7 ; Enable ADC
		179	ADSC avrbit ADCSR,6 ; Start Conversion
		180	ADFR avrbit ADCSR,5 ; Free Running Select
		181	ADIF avrbit ADCSR,4 ; Interrupt Flag
		182	ADIE avrbit ADCSR,3 ; Interrupt Enable
		183	ADPS2 avrbit ADCSR,2 ; Prescaler Select
		184	ADPS1 avrbit ADCSR,1
		185	ADPS0 avrbit ADCSR,0
		186
		187	ADCH port 0x05 ; Data Register
		188	ADCL port 0x04
		189
		190	restore
		191
		192	endif ; __reg8535inc

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(root)//tools/asl/asl-current/include/avr/reg8535.inc – Rev 1186