WebSVN – pentevo – Blame – //tools/asl/asl-current/include/avr/regtnx4.inc

Rev	Author	Line No.	Line
1186	savelij	1	ifndef __regtnx4inc
		2	__regtnx4inc equ 1
		3	save
		4	listing off ; no listing over this file
		5
		6	;****************************************************************************
		7	;* *
		8	;* AS 1.42 - File REGTNX4.INC *
		9	;* *
		10	;* Contains Common Bit & Register Definitions for ATtiny24(A)/44(A)/84(A) *
		11	;* *
		12	;****************************************************************************
		13
		14	;----------------------------------------------------------------------------
		15	; Chip Configuration
		16
		17	MCUCR port 0x35 ; MCU General Control Register
		18	BODSE avrbit MCUCR,2 ; BOD Sleep
		19	SM0 avrbit MCUCR,3 ; Sleep Mode Select
		20	SM1 avrbit MCUCR,4
		21	SE avrbit MCUCR,5 ; Sleep Enable
		22	BODS avrbit MCUCR,7 ; BOD Sleep Enable
		23
		24	MCUSR port 0x34 ; MCU Status Register
		25	WDRF avrbit MCUSR,3 ; Watchdog Reset Flag
		26	BORF avrbit MCUSR,2 ; Brown-out Reset Flag
		27	EXTRF avrbit MCUSR,1 ; External Reset Flag
		28	PORF avrbit MCUSR,0 ; Power-On Reset Flag
		29
		30	OSCCAL port 0x31 ; Oscillator Calibration
		31
		32	CLKPR port 0x26 ; Clock Prescaler
		33	CLKPS0 avrbit CLKPR,0 ; Prescaler Select
		34	CLKPS1 avrbit CLKPR,1
		35	CLKPS2 avrbit CLKPR,2
		36	CLKPS3 avrbit CLKPR,3
		37	CLKPCE avrbit CLKPR,7 ; Clock Prescaler Change Enable
		38
		39	PRR port 0x00 ; Power Reduction Register
		40	PRADC avrbit PRR,0 ; Power Reduction AD Converter
		41	PRUSI avrbit PRR,1 ; Power Reduction USI
		42	PRTIM0 avrbit PRR,2 ; Power Reduction Timer/Counter 0
		43	PRTIM1 avrbit PRR,3 ; Power Reduction Timer/Counter 1
		44
		45	;----------------------------------------------------------------------------
		46	; EEPROM/Flash Access
		47
		48	EEARL port 0x1e ; EEPROM Address Register Low
		49	EEARH port 0x1f ; EEPROM Address Register High
		50	EEDR port 0x1d ; EEPROM Data Register
		51	EECR port 0x1c ; EEPROM Control Register
		52	EEPM1 avrbit EECR,5 ; EEPROM Program Mode
		53	EEPM0 avrbit EECR,4
		54	EERIE avrbit EECR,3 ; EEPROM Ready Interrupt Enable
		55	EEMPE avrbit EECR,2 ; EEPROM Master Write Enable
		56	EEPE avrbit EECR,1 ; EEPROM Write Enable
		57	EERE avrbit EECR,0 ; EEPROM Read Enable
		58
		59	SPMCSR port 0x37 ; Store Program Memory Control/Status Register
		60	CTPB avrbit SPMCSR,4 ; Clear Temporary Page Buffer
		61	RFLB avrbit SPMCSR,3 ; Read Fuse and Lock Bits
		62	PGWRT avrbit SPMCSR,2 ; Page Write
		63	PGERS avrbit SPMCSR,1 ; Page Erase
		64	SPMEN avrbit SPMCSR,0 ; Self Programming Enable
		65
		66	;----------------------------------------------------------------------------
		67	; JTAG etc.
		68
		69	DWDR port 0x27 ; debugWire Data Register
		70
		71	;----------------------------------------------------------------------------
		72	; GPIO
		73
		74	PUD avrbit MCUCR,6 ; Pull-Up Disable
		75
		76	PINA port 0x19 ; Port A @ 0x19 (IO) ff.
		77	PINB port 0x16 ; Port B @ 0x16 (IO) ff. (bit 0..3)
		78
		79	GPIOR0 port 0x13 ; General Purpose I/O Register 0
		80	GPIOR1 port 0x14 ; General Purpose I/O Register 1
		81	GPIOR2 port 0x15 ; General Purpose I/O Register 2
		82
		83	DIDR0 port 0x01 ; Digital Input Disable Register 0
		84	ADC0D avrbit DIDR0,0 ; ADC0 Digital Input Disable
		85	ADC1D avrbit DIDR0,1 ; ADC1 Digital Input Disable
		86	ADC2D avrbit DIDR0,2 ; ADC2 Digital Input Disable
		87	ADC3D avrbit DIDR0,3 ; ADC3 Digital Input Disable
		88	ADC4D avrbit DIDR0,4 ; ADC4 Digital Input Disable
		89	ADC5D avrbit DIDR0,5 ; ADC5 Digital Input Disable
		90	ADC6D avrbit DIDR0,6 ; ADC6 Digital Input Disable
		91	ADC7D avrbit DIDR0,7 ; ADC7 Digital Input Disable
		92
		93	PCMSK0 port 0x12 ; Pin Change Interrupt Mask 0
		94	PCMSK1 port 0x20 ; Pin Change Interrupt Mask 1
		95	PCINT8 avrbit PCMSK1,0 ; Enable Pin Change Interrupt 8
		96	PCINT9 avrbit PCMSK1,1 ; Enable Pin Change Interrupt 9
		97	PCINT10 avrbit PCMSK1,2 ; Enable Pin Change Interrupt 10
		98	PCINT11 avrbit PCMSK1,3 ; Enable Pin Change Interrupt 11
		99
		100	;----------------------------------------------------------------------------
		101	; Interrupt Vectors
		102
		103	enumconf 1,code
		104	enum INT0_vect=1 ; External Interrupt Request 0
		105	nextenum PCINT0_vect ; Pin Change Interrupt 0
		106	nextenum PCINT1_vect ; Pin Change Interrupt 1
		107	nextenum WDT_vect ; Watchdog Time-Out
		108	nextenum TIMER1_CAPT_vect ; Timer/Counter 1 Capture Event
		109	nextenum TIMER1_COMPA_vect ; Timer/Counter 1 Compare Match A
		110	nextenum TIMER1_COMPB_vect ; Timer/Counter 1 Compare Match B
		111	nextenum TIMER1_OVF_vect ; Timer/Counter 1 Overflow
		112	nextenum TIMER0_COMPA_vect ; Timer/Counter 0 Compare Match A
		113	nextenum TIMER0_COMPB_vect ; Timer/Counter 0 Compare Match B
		114	nextenum TIMER0_OVF_vect ; Timer/Counter 0 Overflow
		115	nextenum ANA_COMP_vect ; Analog Comparator
		116	nextenum ADC_vect ; ADC Conversion Complete
		117	nextenum EE_RDY_vect ; EEPROM Ready
		118	nextenum USI_START_vect ; USI Start
		119	nextenum USI_OVF_vect ; USI Overflow
		120
		121	;----------------------------------------------------------------------------
		122	; External Interrupts
		123
		124	ISC00 avrbit MCUCR,0 ; External Interrupt 0 Sense Control
		125	ISC01 avrbit MCUCR,1
		126
		127	GIMSK port 0x3b ; General Interrupt Mask Register
		128	INT0 avrbit GIMSK,6 ; Enable External Interrupt 0
		129	PCIE1 avrbit GIMSK,5 ; Pin Change Interrupt Enable 1
		130	PCIE0 avrbit GIMSK,4 ; Pin Change Interrupt Enable 0
		131
		132	GIFR port 0x3a ; General Interrupt Flag Register
		133	INTF0 avrbit GIFR,6 ; External Interrupt 0 Occured
		134	PCIF1 avrbit GIFR,5 ; Pin Change Interrupt 1 Occured
		135	PCIF0 avrbit GIFR,4 ; Pin Change Interrupt 0 Occured
		136
		137	;----------------------------------------------------------------------------
		138	; Timers
		139
		140	TCCR0A port 0x30 ; Timer/Counter 0 Control Register A
		141	WGM00 avrbit TCCR0A,0 ; Timer/Counter 0 Waveform Generation Mode
		142	WGM01 avrbit TCCR0A,1
		143	COM0B0 avrbit TCCR0A,4 ; Timer/Counter 0 Output Compare Mode B
		144	COM0B1 avrbit TCCR0A,5
		145	COM0A0 avrbit TCCR0A,6 ; Timer/Counter 0 Output Compare Mode A
		146	COM0A1 avrbit TCCR0A,7
		147	TCCR0B port 0x33 ; Timer/Counter 0 Control Register B
		148	CS00 avrbit TCCR0B,0 ; Timer/Counter 0 Clock Select
		149	CS01 avrbit TCCR0B,1
		150	CS02 avrbit TCCR0B,2
		151	WGM02 avrbit TCCR0B,3
		152	FOC0B avrbit TCCR0B,6 ; Timer/Counter 0 Force Output Compare B
		153	FOC0A avrbit TCCR0B,7 ; Timer/Counter 0 Force Output Compare A
		154	TCNT0 port 0x32 ; Timer/Counter 0 Value
		155	OCR0A port 0x36 ; Timer/Counter 0 Output Compare Value A
		156	OCR0B port 0x3c ; Timer/Counter 0 Output Compare Value B
		157
		158	TCCR1A port 0x2f ; Timer/Counter 1 Control Register A
		159	WGM10 avrbit TCCR1A,0 ; Timer/Counter 1 Waveform Generation Mode
		160	WGM11 avrbit TCCR1A,1
		161	COM1B0 avrbit TCCR1A,4 ; Timer/Counter 1 Output Compare Mode B
		162	COM1B1 avrbit TCCR1A,5
		163	COM1A0 avrbit TCCR1A,6 ; Timer/Counter 1 Output Compare Mode A
		164	COM1A1 avrbit TCCR1A,7
		165	TCCR1B port 0x2e ; Timer/Counter 1 Control Register B
		166	CS10 avrbit TCCR1B,0 ; Timer/Counter 1 Clock Select
		167	CS11 avrbit TCCR1B,1
		168	CS12 avrbit TCCR1B,2
		169	WGM12 avrbit TCCR1B,3
		170	WGM13 avrbit TCCR1B,4
		171	ICES1 avrbit TCCR1B,6 ; Timer/Counter 1 Input Capture Edge Select
		172	ICNC1 avrbit TCCR1B,7 ; Timer/Counter 1 Input Capture Noise Canceling
		173	TCCR1C port 0x22 ; Timer/Counter 1 Control Register C
		174	FOC1B avrbit TCCR1C,6 ; Timer/Counter 1 Force Output Compare B
		175	FOC1A avrbit TCCR1C,7 ; Timer/Counter 1 Force Output Compare A
		176	TCNT1L port 0x2c ; Timer/Counter 1 Value LSB
		177	TCNT1H port 0x2d ; Timer/Counter 1 Value MSB
		178	OCR1AL port 0x2a ; Timer/Counter 1 Output Compare Value A LSB
		179	OCR1AH port 0x2b ; Timer/Counter 1 Output Compare Value A MSB
		180	OCR1BL port 0x28 ; Timer/Counter 1 Output Compare Value B LSB
		181	OCR1BH port 0x29 ; Timer/Counter 1 Output Compare Value B MSB
		182	ICR1L port 0x24 ; Timer/Counter 1 Input Capture Value LSB
		183	ICR1H port 0x25 ; Timer/Counter 1 Input Capture Value MSB
		184
		185	TIMSK0 port 0x39 ; Timer/Counter Interrupt Mask Register 0
		186	TOIE0 avrbit TIMSK0,0 ; Timer/Counter 0 Overflow Interrupt Enable
		187	OCIE0A avrbit TIMSK0,1 ; Timer/Counter 0 Output Compare Interrupt Enable A
		188	OCIE0B avrbit TIMSK0,2 ; Timer/Counter 0 Output Compare Interrupt Enable B
		189
		190	TIMSK1 port 0x0c ; Timer/Counter Interrupt Mask Register 1
		191	TOIE1 avrbit TIMSK1,0 ; Timer/Counter 1 Overflow Interrupt Enable
		192	OCIE1A avrbit TIMSK1,1 ; Timer/Counter 1 Output Compare Interrupt Enable A
		193	OCIE1B avrbit TIMSK1,2 ; Timer/Counter 1 Output Compare Interrupt Enable B
		194	ICIE1 avrbit TIMSK1,5 ; Timer/Counter 1 Input Capture Interrupt Enable
		195
		196	TIFR0 port 0x38 ; Timer Interrupt Status Register 0
		197	TIFR1 port 0x0b ; Timer Interrupt Status Register 1
		198
		199	GTCCR port 0x23 ; General Timer/Counter Control 1 Register
		200	PSR10 avrbit GTCCR,0 ; Prescaler Reset Timer/Counter 0/1
		201	TSM avrbit GTCCR,7 ; Timer/Counter Synchronization Mode
		202
		203	;----------------------------------------------------------------------------
		204	; Watchdog Timer
		205
		206	include "wdm21.inc"
		207
		208	WDCE avrbit WDTCR,4 ; Change Enable
		209	WDP3 avrbit WDTCR,5
		210	WDIE avrbit WDTCR,6 ; Enable Watchdog Interrupt
		211	WDIF avrbit WDTCR,7 ; Watchdog Interrupt Occured?
		212
		213	;----------------------------------------------------------------------------
		214	; Analog Comparator
		215
		216	include "acm.inc"
		217
		218	;----------------------------------------------------------------------------
		219	; A/D Converter
		220
		221	ADMUX port 0x07 ; Multiplexer Selection
		222	REFS1 avrbit ADMUX,7 ; Reference Selection Bits
		223	REFS0 avrbit ADMUX,6
		224	MUX5 avrbit ADMUX,5 ; Multiplexer
		225	MUX4 avrbit ADMUX,4
		226	MUX3 avrbit ADMUX,3
		227	MUX2 avrbit ADMUX,2
		228	MUX1 avrbit ADMUX,1
		229	MUX0 avrbit ADMUX,0
		230
		231	ADCSRA port 0x06 ; Control/Status Register A
		232	ADEN avrbit ADCSRA,7 ; Enable ADC
		233	ADSC avrbit ADCSRA,6 ; Start Conversion
		234	ADATE avrbit ADCSRA,5 ; ADC Auto Trigger Enable
		235	ADIF avrbit ADCSRA,4 ; Interrupt Flag
		236	ADIE avrbit ADCSRA,3 ; Interrupt Enable
		237	ADPS2 avrbit ADCSRA,2 ; Prescaler Select
		238	ADPS1 avrbit ADCSRA,1
		239	ADPS0 avrbit ADCSRA,0
		240
		241	ADCSRB port 0x03 ; Control/Status Register B
		242	BIN avrbit ADCSRB,7 ; Bipolar Input Mode
		243	ACME avrbit ADCSRB,6 ; Analog Comparator Multiplexer Enable
		244	ADLAR avrbit ADCSRB,4 ; Left Adjust Right
		245	ADTS2 avrbit ADCSRB,2 ; Auto Trigger Source
		246	ADTS1 avrbit ADCSRB,1
		247	ADTS0 avrbit ADCSRB,0
		248
		249	ADCH port 0x05 ; Data Register
		250	ADCL port 0x04
		251
		252	;----------------------------------------------------------------------------
		253	; USI
		254
		255	USIDR port 0x0f ; USI Data Register
		256
		257	USISR port 0x0e ; USI Status Register
		258	USICNT0 avrbit USISR,0 ; Counter Value
		259	USICNT1 avrbit USISR,1
		260	USICNT2 avrbit USISR,2
		261	USICNT3 avrbit USISR,3
		262	USIDC avrbit USISR,4 ; Data Output Collision
		263	USIPF avrbit USISR,5 ; Stop Condition Flag
		264	USIOIF avrbit USISR,6 ; Counter Overflow Interrupt Flag
		265	USISIF avrbit USISR,7 ; Start Condition Interrupt Flag
		266
		267	USICR port 0x0d ; USI Control Register
		268	USITC avrbit USICR,0 ; Toggle Clock Port Pin
		269	USICLK avrbit USICR,1 ; Clock Strobe
		270	USICS0 avrbit USICR,2 ; Clock Source Select
		271	USICS1 avrbit USICR,3
		272	USIWM0 avrbit USICR,4 ; Wire Mode
		273	USIWM1 avrbit USICR,5
		274	USIOIE avrbit USICR,6 ; Counter Overflow Interrupt Enable
		275	USISIE avrbit USICR,7 ; Start Condition Interrupt Enable
		276
		277	USIBR port 0x10 ; USI Buffer Register
		278
		279	restore ; re-enable listing
		280
		281	endif ; __regtnx4inc

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(root)//tools/asl/asl-current/include/avr/regtnx4.inc – Rev 1186