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Rev | Author | Line No. | Line |
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1186 | savelij | 1 | ifndef __53xxuartinc ; avoid multiple inclusion |
2 | __53xxuartinc equ 1 |
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3 | |||
4 | save |
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5 | listing off ; no listing over this file |
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6 | |||
7 | ;**************************************************************************** |
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8 | ;* * |
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9 | ;* AS 1.42 - File 53XXUART.INC * |
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10 | ;* * |
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11 | ;* Contains SFR and Bit Definitions for ColdFire MCF53xx UART * |
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12 | ;* * |
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13 | ;**************************************************************************** |
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14 | |||
15 | __defuart macro n,Base |
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16 | UMR1{n} equ Base+0 ; Mode Register 1 (8b) |
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17 | RXRTS cfbit UMR1{n},7 ; Receiver Request-to-Send Control |
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18 | RXIRQ cfbit UMR1{n},6 ; Receiver Interrupt Select |
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19 | ERR cfbit UMR1{n},5 ; Error Mode |
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20 | PM cffield UMR1{n},3,2 ; Parity Mode |
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21 | PT cfbit UMR1{n},2 ; Parity Type |
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22 | BC cffield UMR1{n},0,2 ; Bits per Character |
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23 | UMR2{n} equ Base+0 ; Mode Register 2 (8b) |
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24 | CM cffield UMR2{n},6,2 ; Channel Mode |
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25 | TXRTS cfbit UMR2{n},5 ; Transmitter Ready-to-Send |
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26 | TXCTS cfbit UMR2{n},4 ; Transmitter Clear-to-Send |
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27 | SB cffield UMR2{n},0,4 ; Stop-Bit Length Control |
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28 | USR{n} equ Base+4 ; Status Register (8b) |
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29 | RB cfbit USR{n},7 ; Received Break |
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30 | FE cfbit USR{n},6 ; Framing Error |
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31 | PE cfbit USR{n},5 ; Parity Error |
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32 | OE cfbit USR{n},4 ; Overrun Error |
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33 | TXEMP cfbit USR{n},3 ; Transmitter Empty |
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34 | TXRDY cfbit USR{n},2 ; Transmitter Ready |
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35 | FFULL cfbit USR{n},1 ; FIFO Full |
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36 | RXRDY cfbit USR{n},0 ; Receiver Ready |
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37 | UCSR{n} equ Base+4 ; Clock-Select Register (8b) |
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38 | RCS cffield UCSR{n},4,4 ; Receiver Clock Select |
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39 | TCS cffield UCSR{n},0,4 ; Transmitter Clock Select |
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40 | UCR{n} equ Base+8 ; Command Register (8b) |
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41 | MISC cffield UCR{n},4,3 ; Miscellaneous Commands |
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42 | TC cffield UCR{n},2,2 ; Transmitter Commands |
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43 | RC cffield UCR{n},0,2 ; Receiver Commands |
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44 | URB{n} equ Base+$c ; Receiver Buffer (8b) |
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45 | UTB{n} equ Base+$c ; Transmitter Buffer (8b) |
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46 | UIPCR{n} equ Base+$10 ; Input Port Change Register (8b) |
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47 | COS cfbit UIPCR{n},4 ; Change-of-State |
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48 | CTS cfbit UIPCR{n},0 ; Current State |
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49 | UACR{n} equ Base+$10 ; Auxiliary Control Register (8b) |
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50 | IEC cfbit UACR{n},0 ; Input Enable Control |
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51 | UISR{n} equ Base+$14 ; Interrupt Status Register (8b) |
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52 | COS cfbit UISR{n},7 ; Change-of-State |
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53 | DB cfbit UISR{n},2 ; Delta Break |
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54 | RXRDY cfbit UISR{n},1 ; Receiver Ready or FIFO Full |
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55 | TXRDY cfbit UISR{n},0 ; Transmitter Ready |
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56 | UIMR{n} equ Base+$14 ; Interrupt Mask Register (8b) |
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57 | COS cfbit UIMR{n},7 ; Change-of-State |
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58 | DB cfbit UIMR{n},2 ; Delta Break |
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59 | FFULL cfbit UIMR{n},1 ; FIFO Full |
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60 | TXRDY cfbit UIMR{n},0 ; Transmitter Ready |
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61 | UDU{n} equ Base+$18 ; Divider Upper (8b) |
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62 | UDL{n} equ Base+$1c ; Divider Lower (8b) |
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63 | UIVR{n} equ Base+$30 ; Interrupt Vector Register (8b) |
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64 | UIP{n} equ Base+$34 ; Input Port Register (8b) |
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65 | CTS cfbit UIP{n},0 ; CTS Current State |
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66 | UOP1{n} equ Base+$38 ; Output Port Bit Set CMD (8b) |
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67 | RTS cfbit UOP1{n},0 ; set RTS |
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68 | UOP0{n} equ Base+$3c ; Output Port Bit Reset CMD (8b) |
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69 | RTS cfbit UOP0{n},0 ; reset RTS |
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70 | endm |
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71 | |||
72 | restore ; re-enable listing |
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73 | |||
74 | endif ; __53xxuartinc |