Subversion Repositories pentevo

Rev

Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
1186 savelij 1
		ifndef	__53xxuartinc		; avoid multiple inclusion
2
__53xxuartinc	equ	1
3
 
4
		save
5
		listing	off			; no listing over this file
6
 
7
;****************************************************************************
8
;*                                                                          *
9
;*   AS 1.42 - File 53XXUART.INC                                            *
10
;*                                                                          *
11
;*   Contains SFR and Bit Definitions for ColdFire MCF53xx UART             *
12
;*                                                                          *
13
;****************************************************************************
14
 
15
__defuart	macro		n,Base
16
UMR1{n}		equ		Base+0		; Mode Register 1 (8b)
17
RXRTS		cfbit		UMR1{n},7	;  Receiver Request-to-Send Control
18
RXIRQ		cfbit		UMR1{n},6	;  Receiver Interrupt Select
19
ERR		cfbit		UMR1{n},5	;  Error Mode
20
PM		cffield		UMR1{n},3,2	;  Parity Mode
21
PT		cfbit		UMR1{n},2	;  Parity Type
22
BC		cffield		UMR1{n},0,2	;  Bits per Character
23
UMR2{n}		equ		Base+0		; Mode Register 2 (8b)
24
CM		cffield		UMR2{n},6,2	;  Channel Mode
25
TXRTS		cfbit		UMR2{n},5	;  Transmitter Ready-to-Send
26
TXCTS		cfbit		UMR2{n},4	;  Transmitter Clear-to-Send
27
SB		cffield		UMR2{n},0,4	;  Stop-Bit Length Control
28
USR{n}		equ		Base+4		; Status Register (8b)
29
RB		cfbit		USR{n},7	;  Received Break
30
FE		cfbit		USR{n},6	;  Framing Error
31
PE		cfbit		USR{n},5	;  Parity Error
32
OE		cfbit		USR{n},4	;  Overrun Error
33
TXEMP		cfbit		USR{n},3	;  Transmitter Empty
34
TXRDY		cfbit		USR{n},2	;  Transmitter Ready
35
FFULL		cfbit		USR{n},1	;  FIFO Full
36
RXRDY		cfbit		USR{n},0	;  Receiver Ready
37
UCSR{n}		equ		Base+4		; Clock-Select Register (8b)
38
RCS		cffield		UCSR{n},4,4	;  Receiver Clock Select
39
TCS		cffield		UCSR{n},0,4	;  Transmitter Clock Select
40
UCR{n}		equ		Base+8		; Command Register (8b)
41
MISC		cffield		UCR{n},4,3	;  Miscellaneous Commands
42
TC		cffield		UCR{n},2,2	;  Transmitter Commands
43
RC		cffield		UCR{n},0,2	;  Receiver Commands
44
URB{n}		equ		Base+$c		; Receiver Buffer (8b)
45
UTB{n}		equ		Base+$c		; Transmitter Buffer (8b)
46
UIPCR{n}	equ		Base+$10	; Input Port Change Register (8b)
47
COS		cfbit		UIPCR{n},4	;  Change-of-State
48
CTS		cfbit		UIPCR{n},0	;  Current State
49
UACR{n}		equ		Base+$10	; Auxiliary Control Register (8b)
50
IEC		cfbit		UACR{n},0	;  Input Enable Control
51
UISR{n}		equ		Base+$14	; Interrupt Status Register (8b)
52
COS		cfbit		UISR{n},7	;  Change-of-State
53
DB		cfbit		UISR{n},2	;  Delta Break
54
RXRDY		cfbit		UISR{n},1	;  Receiver Ready or FIFO Full
55
TXRDY		cfbit		UISR{n},0	;  Transmitter Ready
56
UIMR{n}		equ		Base+$14	; Interrupt Mask Register (8b)
57
COS		cfbit		UIMR{n},7	;  Change-of-State
58
DB		cfbit		UIMR{n},2	;  Delta Break
59
FFULL		cfbit		UIMR{n},1	;  FIFO Full
60
TXRDY		cfbit		UIMR{n},0	;  Transmitter Ready
61
UDU{n}		equ		Base+$18	; Divider Upper (8b)
62
UDL{n}		equ		Base+$1c	; Divider Lower (8b)
63
UIVR{n}		equ		Base+$30	; Interrupt Vector Register (8b)
64
UIP{n}		equ		Base+$34	; Input Port Register (8b)
65
CTS		cfbit		UIP{n},0	;  CTS Current State
66
UOP1{n}		equ		Base+$38	; Output Port Bit Set CMD (8b)
67
RTS		cfbit		UOP1{n},0	;  set RTS
68
UOP0{n}		equ		Base+$3c	; Output Port Bit Reset CMD (8b)	
69
RTS		cfbit		UOP0{n},0	;  reset RTS
70
		endm
71
 
72
		restore				; re-enable listing
73
 
74
                endif                           ; __53xxuartinc