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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef __ez80uartinc |
| 2 | __ez80uartinc equ 1 |
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| 3 | |||
| 4 | __defuart macro NUM,Base |
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| 5 | UART{NUM}_RBR port Base+0 ; UART n Receive Buffer Register (r) |
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| 6 | UART{NUM}_THR port Base+0 ; UART n Transmit Holding Register (w) |
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| 7 | UART{NUM}_BRG_L port Base+0 ; UART n Baud Rate Generator - Low Byte (r/w) |
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| 8 | UART{NUM}_BRG_H port Base+1 ; UART n Baud Rate Generator - High Byte (r/w) |
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| 9 | UART{NUM}_IER port Base+1 ; UART n Interrupt Enable Register (r/w) |
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| 10 | if NUM == "0" |
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| 11 | MIIE equ 1 << 3 ; Enable edge detect modem status interrupt |
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| 12 | LSIE equ 1 << 2 ; Enable line status interrupt |
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| 13 | TIE equ 1 << 1 ; Enable transmit interrupt |
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| 14 | RIE equ 1 << 0 ; Enable receive interrupt |
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| 15 | endif |
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| 16 | UART{NUM}_IIR port Base+2 ; UART n Interrupt Identification Register (r) |
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| 17 | if NUM == "0" |
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| 18 | INTSTS_S equ 1 ; Interrupt Status Code |
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| 19 | INTSTS_M equ 7 << INTSTS_S |
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| 20 | INTSTS_RLS equ 3 << INTSTS_S ; Receiver Line Status |
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| 21 | INTSTS_RDR equ 2 << INTSTS_S ; Receiver Data Ready |
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| 22 | INTSTS_CTO equ 6 << INTSTS_S ; Character Time out |
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| 23 | INTSTS_TBE equ 1 << INTSTS_S ; Transmit buffer empty |
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| 24 | INTSTS_MS equ 0 << INTSTS_S ; Modem Status |
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| 25 | INTBIT equ 1 << 0 ; Active interrupt source |
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| 26 | endif |
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| 27 | UART{NUM}_FCTL port Base+2 ; UART n FIFO Control Register (w) |
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| 28 | if NUM == "0" |
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| 29 | TRIG_S equ 6 ; Receive FIFO Trigger Level |
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| 30 | TRIG_M equ 3 << TRIG_S |
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| 31 | CLRTXF equ 1 << 2 ; Clear Tx FIFO |
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| 32 | CLRRXF equ 1 << 1 ; Clear Rx FIFO |
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| 33 | FIFOEN equ 1 << 0 ; Enable FIFOs |
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| 34 | endif |
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| 35 | UART{NUM}_LCTL port Base+3 ; UART n Line Control Register (r/w) |
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| 36 | if NUM == "0" |
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| 37 | DLAB equ 1 << 7 ; Access baud rate registers |
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| 38 | SB equ 1 << 6 ; Send break |
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| 39 | FPE equ 1 << 5 ; Force parity error |
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| 40 | EPS equ 1 << 4 ; Use even parity |
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| 41 | PEN equ 1 << 3 ; Parity enable |
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| 42 | CHAR_S equ 0 ; Data bit count |
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| 43 | CHAR_M equ 7 << CHAR_S |
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| 44 | CHAR_5_1 equ 0 << CHAR_S ; 5x1 |
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| 45 | CHAR_6_1 equ 1 << CHAR_S ; 6x1 |
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| 46 | CHAR_7_1 equ 2 << CHAR_S ; 7x1 |
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| 47 | CHAR_8_1 equ 3 << CHAR_S ; 8x1 |
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| 48 | CHAR_5_2 equ 4 << CHAR_S ; 5x2 |
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| 49 | CHAR_6_2 equ 5 << CHAR_S ; 6x2 |
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| 50 | CHAR_7_2 equ 6 << CHAR_S ; 7x2 |
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| 51 | CHAR_8_2 equ 7 << CHAR_S ; 8x2 |
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| 52 | endif |
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| 53 | UART{NUM}_MCTL port Base+4 ; UART n Modem Control Register (r/w) |
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| 54 | if NUM == "0" |
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| 55 | LOOP equ 1 << 4 ; Enable Loopback |
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| 56 | OUT2 equ 1 << 3 ; DCD in loopback mode |
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| 57 | OUT1 equ 1 << 2 ; RI in loopback mode |
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| 58 | RTS equ 1 << 1 ; set RTS |
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| 59 | DTR equ 1 << 0 ; set DTR |
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| 60 | endif |
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| 61 | UART{NUM}_LSR port Base+5 ; UART n Line Status Register (r) |
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| 62 | if NUM == "0" |
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| 63 | ERR equ 1 << 7 ; Error detected in FIFO |
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| 64 | TEMPT equ 1 << 6 ; Transmitter empty |
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| 65 | THRE equ 1 << 5 ; Transmitter Holding Register Empty |
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| 66 | BI equ 1 << 4 ; Break Indication |
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| 67 | FE equ 1 << 3 ; Framing Error |
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| 68 | PE equ 1 << 2 ; Parity Error |
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| 69 | OE equ 1 << 1 ; Overrun Error |
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| 70 | DR equ 1 << 0 ; Data Ready |
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| 71 | endif |
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| 72 | UART{NUM}_MSR port Base+6 ; UART n Modem Status Register (r) |
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| 73 | if NUM == "0" |
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| 74 | DCD equ 1 << 7 ; Carrier Detect |
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| 75 | RI equ 1 << 6 ; Ring Indicator |
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| 76 | DSR equ 1 << 5 ; Data Set Ready |
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| 77 | CTS equ 1 << 4 ; Data Carrier Detect |
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| 78 | DDCD equ 1 << 3 ; DCD status change |
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| 79 | TERI equ 1 << 2 ; RI trailing edge |
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| 80 | DDSR equ 1 << 1 ; DSR status change |
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| 81 | DCTS equ 1 << 0 ; CTS status change |
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| 82 | endif |
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| 83 | UART{NUM}_SPR port Base+7 ; UART n Scratch Pad Register (r/w) |
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| 84 | endm ; __defuart |
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| 85 | |||
| 86 | endif ; __ez80uartinc |