Subversion Repositories pentevo

Rev

Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
1186 savelij 1
                ifndef  reg3048inc	; avoid multiple inclusion
2
reg3048inc	equ     1
3
 
4
                save
5
                listing off		; no listing over this file
6
 
7
;****************************************************************************
8
;*                                                                          *
9
;*   AS 1.42 - File REG3048.INC                                             *
10
;*   								            *
11
;*   Contains SFR, Macro, and Address Definitions for H8/3048               *
12
;* 									    *
13
;****************************************************************************
14
 
15
                if      (MOMCPUNAME<>"HD6413309")&&(MOMCPUNAME<>"H8/300H")
16
                 fatal  "wrong target selected: only H8/300H supported."
17
		endif
18
 
19
 
20
                if      MOMPASS=1
21
                 message "H8/3048 SFR Definitions, (C) 1995 Christian Stelter"
22
		endif
23
 
24
;-----------------------------------------------------------------------------
25
; MCU Operating Modes: (Sec.3 p.55-68 & Sec.20 p.615-628)
26
 
27
 
28
MDCR            equ     $fff1           ; CPU Operation Mode
29
SYSCR           equ     $fff2           ; Standby Mode Register
30
MSTCR           equ     $ff5e           ; Module Standby Control Register
31
 
32
; MDCR Register
33
 
34
MD0             equ     0
35
MD1             equ     1
36
MD2             equ     2
37
 
38
 
39
; SYSCR Register
40
 
41
SSBY            equ     7               ; Software Standby
42
STS2            equ     6               ; Standby Timer Select
43
STS1            equ     5
44
STS0            equ     4
45
UE              equ     3               ; User Bit Enable
46
NMIEG           equ     2               ; NMI Edge
47
RAME            equ     0               ; Enable Internal RAM 
48
 
49
 
50
; MSTCR Register
51
 
52
PSTOP           equ     7               ; Phi Clock Stop
53
MSTOP5          equ     5               ; Module Standby
54
MSTOP4          equ     4
55
MSTOP3          equ     3
56
MSTOP2          equ     2
57
MSTOP1          equ     1
58
MSTOP0          equ     0
59
 
60
;-----------------------------------------------------------------------------
61
; Bus Controller (Sec.6 p.107-142)
62
 
63
 
64
ABWCR           equ     $ffec           ; Bus Width Control Register
65
 
66
ASTCR           equ     $ffed           ; Access State Control Register
67
 
68
WCR             equ     $ffee           ; Wait Control Register
69
WMS0            equ     2               ; Mode
70
WMS1            equ     3
71
WC0             equ     0               ; Number of Waitstates
72
WC1             equ     1
73
 
74
WCER            equ     $ffef           ; Wait State Controller Enable Register
75
 
76
BRCR            equ     $fff3           ; Bus Release Control Register
77
A23E            equ     7               ; Address 23 Enable
78
A22E            equ     6               ;         22
79
A21E            equ     5               ;         21
80
BRLE            equ     0               ; Bus Release Enable
81
 
82
 
83
CSCR            equ     $ff5f           ; Chip Select Control Register
84
CS7E            equ     7               ; Chip Select 7 Enable
85
CS6E            equ     6
86
CS5E            equ     5
87
CS4E            equ     4
88
 
89
;-----------------------------------------------------------------------------
90
; Interrupt Controller
91
 
92
ISCR            equ     $fff4           ; IRQ Sense Control Register
93
IER             equ     $fff5           ; IRQ Enable Register
94
ISR             equ     $fff6           ; IRQ Status Register
95
IPRA            equ     $fff8           ; Priority Control
96
IPRB            equ     $fff9           ;
97
 
98
 
99
;-----------------------------------------------------------------------------
100
; Position of Exception and Interrupt Vectoren (Sec.4 p.69-78)
101
 
102
__defvec        macro   Name,Num
103
Name             equ     Num<<2
104
                endm
105
 
106
                __defvec Reset,0
107
                __defvec NMI,7
108
                __defvec TRAP0,8
109
                __defvec TRAP1,9
110
                __defvec TRAP2,10
111
                __defvec TRAP3,11
112
                __defvec IRQ0,12
113
                __defvec IRQ1,13
114
                __defvec IRQ2,14
115
                __defvec IRQ3,15
116
                __defvec IRQ4,16
117
                __defvec IRQ5,17
118
                __defvec WOVI,20
119
                __defvec CMI,21
120
                __defvec IMIA0,24
121
                __defvec IMIB0,25
122
                __defvec OVI0,26
123
                __defvec IMIA1,28
124
                __defvec IMIB1,29
125
                __defvec OVI1,30
126
                __defvec IMIA2,32
127
                __defvec IMIB2,33
128
                __defvec OVI2,34
129
                __defvec IMIA3,36
130
                __defvec IMIB3,37
131
                __defvec OVI3,38
132
                __defvec IMIA4,40
133
                __defvec IMIB4,41
134
                __defvec OVI4,42
135
                __defvec DEND0A,44
136
                ;__defvec DEND0A,45
137
                __defvec DEND1B,46
138
                ;__defvec DEND1B,47
139
                __defvec ERI0,52
140
                __defvec RXI0,53
141
                __defvec TXI0,54
142
                __defvec TEI0,55
143
                __defvec ERI1,56
144
                __defvec RXI1,57
145
                __defvec TXI1,58
146
                __defvec TEI1,59
147
                __defvec ADI,60
148
 
149
 
150
;-----------------------------------------------------------------------------
151
; DMA Controller (Sec.6 p.181-238)
152
 
153
DTEA            equ     $fff4           ; Enable Data Transfers
154
DTEB            equ     $fff5
155
DTEC            equ     $fff6
156
DTED            equ     $fff7
157
 
158
__defdma        macro   Base,Name
159
MAR{Name}AR     equ     Base            ; Memory Address Register AR
160
MAR{Name}ER     equ     Base+1          ; Memory Address Register AE
161
MAR{Name}AL     equ     Base+2          ; Memory Address Register AL
162
MAR{Name}AH     equ     Base+3          ; Memory Address Register AH
163
ETCR{Name}AH    equ     Base+4          ; Execute Transfer Count Register AH
164
ETCR{Name}AL    equ     Base+5          ;                                 AL
165
IOAR{Name}A     equ     Base+6          ; I/O Address Register A
166
DTCR{Name}A     equ     Base+7          ; Data Transfer Control Register A
167
MAR{Name}BR     equ     Base+8          ; Memory Address Register BR
168
MAR{Name}BE     equ     Base+9          ; Memory Address Register BE
169
MAR{Name}BH     equ     Base+10         ; Memory Address Register BH
170
MAR{Name}BL     equ     Base+11         ; Memory Address Register BL
171
ETCR{Name}BH    equ     Base+12         ; Execute Transfer Count Register BH
172
ETCR{Name}BL    equ     Base+13         ; Execute Transfer Count Register BL
173
IOAR{Name}B     equ     Base+14         ; I/O Address Register B
174
DTCR{Name}B     equ     Base+15         ; Data Transfer Control Register
175
                endm
176
 
177
                __defdma $ff20,"0"
178
                __defdma $ff30,"1"
179
 
180
; DTCR Register
181
 
182
; Short Address Mode
183
DTE             equ     7               ; Data Transfer Enable
184
DTSZ            equ     6               ; Data Transfer Size
185
DTID            equ     5               ; Data Transfer Inc/Dec
186
RPE             equ     4               ; Repeat Enable 
187
DTIE            equ     3               ; Data Transfer Interrupt Enable
188
DTS2            equ     2               ; Data Transfer Select
189
DTS1            equ     1
190
DTS0            equ     0
191
 
192
; Full Address Mode
193
SAID            equ     5               ; Source Address Inc/Dec
194
SAIE            equ     4               ; Source Address Inc/Dec Enable
195
DTS2A           equ     2               ; Data Transfer Select
196
DTS1A           equ     1
197
DTS0A           equ     0
198
 
199
; DTCRB Register
200
DTME            equ     7               ; Data Transfer Master Enable
201
DAID            equ     5               ; Destination Address Inc/Dec Bit
202
DAIE            equ     4               ;                             Enable
203
TMS             equ     3               ; Transfer Mode Select
204
DTS2B           equ     2               ; Data Transfer Select
205
DTS1B           equ     1
206
DTS0B           equ     0
207
 
208
;-----------------------------------------------------------------------------
209
; I/O-Ports (Sec.9 p.239-280)
210
 
211
P1DDR           equ     $ffc0           ; Data Direction Port 1
212
P1DR            equ     $ffc2           ; Data Port 1
213
 
214
P2DDR           equ     $ffc1           ; Data Direction Port 2
215
P2DR            equ     $ffc3           ; Data Port 2
216
P2PCR           equ     $ffd8           ; Input Pull Up Control Register Port 3
217
 
218
P3DDR           equ     $ffc4           ; Data Direction Port 3
219
P3DR            equ     $ffc6           ; Data Port 3
220
 
221
P4DDR           equ     $ffc5           ; Data Direction Port 4
222
P4DR            equ     $ffc7           ; Data Port 4
223
P4PCR           equ     $ffda           ; Input Pull Up Control Register Port 4
224
 
225
P5DDR           equ     $ffc8           ; Data Direction Port 5
226
P5DR            equ     $ffca           ; Data Port 5
227
P5PCR           equ     $ffcb           ; Input Pull Up Control Register Port 5
228
 
229
P6DDR           equ     $ffc9           ; Data Direction Port 6
230
P6DR            equ     $ffcb           ; Data Port 6
231
 
232
P8DDR           equ     $ffcd           ; Data Direction Port 8
233
P8DR            equ     $ffcf           ; Data Port 8
234
 
235
P9DDR           equ     $ffd0           ; Data Direction Port 9
236
P9DR            equ     $ffd2           ; Data Port 9
237
 
238
PADDR           equ     $ffd1           ; Data Direction Port A
239
PADR            equ     $ffd3           ; Data Port A
240
 
241
PBDDR           equ     $ffd4           ; Data Direction Port B
242
PBDR            equ     $ffd6           ; Data Port B
243
 
244
;------------------------------------------------------------------------------
245
;Integrated Timer Unit (ITU) (Sec.10 p.281-380)
246
 
247
;common
248
TSTR            equ     $ff60           ; Timer Start Register
249
TSNC            equ     $ff61           ; Timer Synchro Register
250
TMDR            equ     $ff62           ; Timer Mode Register
251
TFCR            equ     $ff63           ; Timer Function Control Register
252
TOER            equ     $ff90           ; Timer Output Master Enable Register
253
TOCR            equ     $ff91           ; Timer Output Control Register
254
 
255
__deftimer      macro   Base,Name
256
TCR{Name}       equ     Base            ; Timer Control Register
257
TIOR{Name}      equ     Base+1          ; Timer I/O Control Register
258
TIER{Name}      equ     Base+2          ; Timer Interrupt Enable Register
259
TSR{Name}       equ     Base+3          ; Timer Status Register
260
TCNT{Name}H     equ     Base+4          ; Timer Counter H
261
TCNT{Name}L     equ     Base+5          ; Timer Counter L
262
GRA{Name}H      equ     Base+6          ; General Register A (high)
263
GRA{Name}L      equ     Base+7          ; General Register A (low)
264
GRB{Name}H      equ     Base+8          ; General Register B (high)
265
GRB{Name}L      equ     Base+9          ; General Register B (low)
266
                endm
267
 
268
                __deftimer $ff64,"0"
269
                __deftimer $ff6e,"1"
270
                __deftimer $ff78,"2"
271
                __deftimer $ff82,"3"
272
 
273
BRA3H           equ     $ff8c           ; Buffer Register A3 (high)
274
BRA3L           equ     $ff8d           ; Buffer Register A3 (low)
275
BRB3H           equ     $ff8e           ; Buffer Register B3 (high)
276
BRB3L           equ     $ff8f           ; Buffer Register B3 (low)
277
 
278
                __deftimer $ff82,"4"
279
 
280
BRA4H           equ     $ff9c           ; Buffer Register A4 (high)
281
BRA4L           equ     $ff9d           ; Buffer Register A4 (low)
282
BRB4H           equ     $ff9e           ; Buffer Register B4 (high)
283
BRB4L           equ     $ff9f           ; Buffer Register B4 (low)
284
 
285
; TMDR Register
286
 
287
MDF             equ     6               ; Phase Counting Mode Flag
288
FDIR            equ     5               ; Flag Direction
289
PWM4            equ     4               ; PWM Mode
290
PWM3            equ     3
291
PWM2            equ     2
292
PWM1            equ     1
293
PWM0            equ     0
294
 
295
; TFCR Register
296
 
297
CMD1            equ     5               ; Combination Mode
298
CMD0            equ     4
299
BFB4            equ     3               ; Buffer Mode B4
300
BFA4            equ     2               ; Buffer Mode A4
301
BFB3            equ     1               ; Buffer Mode B3
302
BFA3            equ     0               ; Buffer Mode A3
303
 
304
; TOER Register
305
 
306
EXB4            equ     5               ; Master Enable TOCXB4
307
EXA4            equ     4               ; Master Enable TOCXA4
308
EB3             equ     3               ; Master Enable TIOCB3
309
EB4             equ     2               ; Master Enable TIOCB4
310
EA4             equ     1               ; Master Enable TIOCA4
311
EA3             equ     0               ; Master Enable TIOCA3
312
 
313
; TOCR Register
314
 
315
XTGD            equ     4               ; External trigger disable
316
OLS4            equ     1               ; Output level select 4
317
OLS3            equ     0               ; Output level select 3
318
 
319
; TCR Register
320
 
321
CCLR1           equ     6               ; Counter Clear
322
CCLR0           equ     5
323
CKEG1           equ     4               ; Counter Edge
324
CKEG0           equ     3
325
TPSC2           equ     2               ; Timer Prescaler
326
TPSC1           equ     1
327
TPSC0           equ     0
328
 
329
 
330
; TIOR Register
331
 
332
IOB2            equ     6               ; I/O Control B2
333
IOB1            equ     5               ; I/O Control B1
334
IOB0            equ     4               ; I/O Control B0
335
IOA2            equ     2               ; I/O Control A2
336
IOA1            equ     1               ; I/O Control A1
337
IOA0            equ     0               ; I/O Control A0
338
 
339
 
340
; TSR-Register
341
 
342
OVF             equ     2               ; Overflow Flag
343
IMFB            equ     1               ; Input Capture / Compare Match Flag B
344
IMFA            equ     0               ; Input Capture / Compare Match Flag A
345
 
346
 
347
; TIER-Register
348
 
349
OVIE            equ     2               ; Overflow Interrupt Enable
350
IMIEB           equ     1               ; Input Capture / Compare Match Interrupt Enable B
351
IMIEA           equ     0               ; Input Capture / Compare Match Interrupt Enable A
352
 
353
;-----------------------------------------------------------------------------
354
; Programmable Timing Pattern Controller (Sec.11 p.381-406)
355
 
356
TPMR            equ     $ffa0           ; TPC Output Mode Register
357
TPCR            equ     $ffa1           ; TPC Output Control Register
358
NDERB           equ     $ffa2           ; Next Data Enable Register B
359
NDERA           equ     $ffa3           ; Next Data Enable Register A
360
NDRA            equ     $ffa5           ; Next Data Register A
361
NDRB            equ     $ffa4           ; Next Data Register B
362
NDRA1           equ     $ffa5           ; Next Data Register A Group 1
363
NDRA0           equ     $ffa7           ; Next Data Register A Group 0
364
NDRB3           equ     $ffa4           ; Next Data Register B Group 3
365
NDRB2           equ     $ffa6           ; Next Data Register B Group 2
366
 
367
;-----------------------------------------------------------------------------
368
; Watchdog (Sec.12 p.407-422)
369
 
370
WDT_TCSR        equ     $ffa8           ; Timer Control/Status Register
371
WDT_TCNT        equ     $ffa9           ; Timer Counter
372
WDT_RSTCSR      equ     $ffab           ; Reset Control/Status Register
373
WDT_RSTCSRW     equ     $ffaa           ; ditto, for word accesses (p.415)
374
 
375
 
376
; TCSR Register
377
 
378
WDT_OVF         equ     7               ; Overflow Flag
379
WDT_WTIT        equ     6               ; Timer Mode Select
380
WDT_TME         equ     5               ; Timer Enable
381
WDT_CKS2        equ     2               ; Clock Select
382
WDT_CKS1        equ     1
383
WDT_CKS0        equ     0
384
 
385
 
386
; RSTCSR Register
387
 
388
WDT_WRST        equ     7               ; Watchdog Timer Reset
389
WDT_RSTOE       equ     6               ; Reset Output Enable
390
 
391
 
392
;-----------------------------------------------------------------------------
393
; Serial Interface (Sec.13 p.423-482)
394
 
395
__defSCI        macro   Base,Name
396
SMR{Name}       equ     Base            ; Serial Mode Register
397
BRR{Name}       equ     Base+1          ; Bit Rate Register
398
SCR{Name}       equ     Base+2          ; Serial Control Register
399
TDR{Name}       equ     Base+3          ; Transmit Data Register
400
SSR{Name}       equ     Base+4          ; Serial Status Register
401
RDR{Name}       equ     Base+5          ; Receive Data Register
402
                endm
403
 
404
                __defSCI $ffb0,"0"
405
                __defSCI $ffb8,"1"
406
 
407
; SMR Register
408
 
409
CA              equ     7               ; Communication Mode
410
CHR             equ     6               ; Character Length
411
PE              equ     5               ; Parity Enable
412
OE              equ     4               ; Parity Mode
413
STOP            equ     3               ; Stop Bit Length
414
MP              equ     2               ; Multiprocessor Mode
415
CKS1            equ     1               ; Clock Select 1
416
CKS0            equ     0
417
 
418
 
419
; SCR Register
420
 
421
TIE             equ     7               ; Transmit Interrupt Enable
422
RIE             equ     6               ; Receive      "        "
423
TE              equ     5               ; Transmit Enable
424
RE              equ     4               ; Receive Enable
425
MPIE            equ     3               ; Multiprozessor Interrupt Enable
426
TEIE            equ     2               ; Transmit-end Interrupt Enable
427
CKE1            equ     1               ; Clock Enable 1
428
CKE0            equ     0               ; Clock Enable 0
429
 
430
; SSR Register
431
 
432
TDRE            equ     7               ; Transmit Data Register Empty
433
RDRF            equ     6               ; Receive Data Register Full
434
ORER            equ     5               ; Overrun Error
435
FER             equ     4               ; Framing Error
436
PER             equ     3               ; Parity Error
437
TEND            equ     2               ; Transmit End
438
MPB             equ     1               ; Multiprocessor Bit
439
MPBT            equ     0               ; Multiprocessor Bit Transfer
440
 
441
;-----------------------------------------------------------------------------
442
; Smart Card Interface
443
 
444
; not implemented yet
445
 
446
;-----------------------------------------------------------------------------
447
; A/D Converter (Sec.15 p.505-526)
448
 
449
ADDRA           equ     $ffe0
450
ADDRAH          equ     $ffe0
451
ADDRAL          equ     $ffe1
452
 
453
ADDRB           equ     $ffe2
454
ADDRBH          equ     $ffe2
455
ADDRBL          equ     $ffe3
456
 
457
ADDRC           equ     $ffe4
458
ADDRCH          equ     $ffe4
459
ADDRCL          equ     $ffe5
460
 
461
 
462
ADDRD           equ     $ffe6
463
ADDRDH          equ     $ffe6
464
ADDRDL          equ     $ffe7
465
 
466
 
467
 
468
ADCSR           equ     $ffe8           ; Control/Status Register:
469
 
470
ADF             equ     7               ; Conversion Completed
471
ADIE            equ     6               ; Interrupt on Conversion End?
472
ADST            equ     5               ; Start Conversion
473
SCAN            equ     4               ; Scan Mode
474
CKS             equ     3               ; Conversion Time
475
CH2             equ     2               ; Channel Selection
476
CH1             equ     1
477
CH0             equ     0
478
 
479
 
480
ADCR            equ     $ffe9           ; A/D Control Register
481
 
482
TRGE            equ     7               ; Trigger Enable
483
 
484
 
485
;-----------------------------------------------------------------------------
486
; D/A-Wandler (Sec.16 p.527-533)
487
 
488
DADR0           equ     $ffdc           ; D/A Data Register 0
489
DADR1           equ     $ffdd           ; D/A Data Register 1
490
DACR            equ     $ffde           ; D/A Control Register
491
DASTCR          equ     $ff5c           ; D/A Standby Control Register
492
 
493
 
494
; DACR Register
495
 
496
DAOE1           equ     7               ; D/A Output Enable
497
DAOE0           equ     6
498
DAE             equ     5               ; D/A Enable
499
 
500
 
501
; DASTCR Register
502
 
503
DASTE           equ     0               ; D/A Standby Enable
504
 
505
 
506
 
507
 
508
;-----------------------------------------------------------------------------
509
; Clock-Pulse Generator (Sec.19 p.607-614)
510
 
511
DIVCR           equ     $ff5d           ; Divison Control Register
512
 
513
 
514
DIV1            equ     1
515
DIV0            equ     0
516
 
517
 
518
 
519
;-----------------------------------------------------------------------------
520
 
521
                restore			; allow listing again
522
 
523
                endif			; reg3048inc