WebSVN – pentevo – Blame – //tools/asl/asl-current/include/reg53x.inc

Rev	Author	Line No.	Line
1186	savelij	1	ifndef reg53xinc ; avoid multiple inclusion
		2	reg53xinc equ 1
		3
		4	save
		5	listing off ; no listing over this file
		6
		7	;****************************************************************************
		8	;* *
		9	;* AS 1.42 - File REG53x.INC *
		10	;* *
		11	;* Contains Register and Address Definitions for H8/53x *
		12	;* *
		13	;****************************************************************************
		14
		15	if (MOMCPUNAME<>"HD6475328")&&(MOMCPUNAME<>"HD6475348")&&(MOMCPUNAME<>"HD6475368")&&(MOMCPUNAME<>"HD6475388")
		16	fatal "wrong target selected: only HD6475328, HD6475348, HD6475368, or HD6475388 supported"
		17	endif
		18
		19
		20	if MOMPASS=1
		21	message "H8/53x Definitions (C) 1995 Alfred Arnold"
		22	endif
		23
		24	__cpunum equ MOMCPU-$6475000 ; more comfortable this way...
		25
		26	if __cpunum=$328 ; For H8/532, register base moves
		27	__regbase equ $ff00 ; one page upward
		28	elseif
		29	__regbase equ $fe00
		30	endif
		31
		32	;----------------------------------------------------------------------------
		33	; Adressen:
		34
		35	if __cpunum=$328
		36	IRAM equ $fb80 ; Internal RAM Start (1 kByte)
		37	IRAMEND equ $ff7f ; Internal RAM End
		38	elseif
		39	IRAM equ $f680 ; Internal RAM Start (2 kByte)
		40	IRAMEND equ $fe7f ; Internal RAM End
		41	endif
		42
		43	IROM equ $0000 ; Internal ROM Start
		44	if __cpunum=$368
		45	IROMEND equ $f67f ; Internal ROM End (62 kByte)
		46	elseif
		47	IROMEND equ $7fff ; Internal ROM End (32 kByte)
		48	endif
		49
		50
		51	;----------------------------------------------------------------------------
		52	; CPU Configuration
		53
		54	if __cpunum=$328
		55	__sysbase equ $fff8
		56	elseif
		57	__sysbase equ $ff10
		58	endif
		59
		60	WCR equ __sysbase+0 ; Wait State Control Register
		61	WC0 equ 0 ; Number of Wait Cycles (rw)
		62	WC1 equ 1
		63	WMS0 equ 2 ; Wait Mode (rw)
		64	WMS1 equ 3
		65
		66	RAMCR equ __sysbase+1 ; RAM Control Register
		67	RAME equ 7 ; Internal RAM Enable
		68
		69	MDCR equ __sysbase+2 ; Mode Control Register
		70	MDS0 equ 0 ; Mode Select (r)
		71	MDS1 equ 1
		72	MDS2 equ 2
		73
		74	SBYCR equ __sysbase+3 ; Software Standby Control Register
		75	SSBY equ 7 ; Sleep/Standby Mode Select (rw)
		76
		77	;----------------------------------------------------------------------------
		78	; Interrupt Control
		79
		80	if __cpunum=$328
		81	IPRA equ $fff0 ; IRQ1 / IRQ0 Interrupt Priority (rw)
		82	IPRB equ $fff1 ; FRT2 / FRT1 Interrupt Priority (rw)
		83	IPRC equ $fff2 ; 8 Bit Timer Interrupt Priority / FRT3 (rw)
		84	IPRD equ $fff3 ; AD Converter / SCI Interrupt Priority (rw)
		85	elseif
		86	IPRA equ $ff00 ; IRQ1 / IRQ0\|I.-Timer Interrupt Priority (rw)
		87	IPRB equ $ff01 ; IRQ5\|IRQ4 / IRQ3\|IRQ2 Interrupt Priority (rw)
		88	IPRC equ $ff02 ; FRT2 / FRT1 Interrupt Priority (rw)
		89	IPRD equ $ff03 ; 8 Bit Timer / FTR3 Interrupt Priority (rw)
		90	IPRE equ $ff04 ; SCI2 / SCI1 Interrupt Priority (rw)
		91	IPRF equ $ff05 ; - / AD Converter Interrupt Priority
		92	endif
		93
		94	;----------------------------------------------------------------------------
		95	; Data Transfer Controller:
		96
		97	if __cpunum=$328
		98	DTEA equ $fff4 ; Normal/DTC Interrupt Selection
		99	DTEB equ $fff5 ; (Population of Nibbles analogous to IPRx)
		100	DTEC equ $fff6
		101	DTED equ $fff7
		102	elseif
		103	DTEA equ $ff08
		104	DTEB equ $ff09
		105	DTEC equ $ff0a
		106	DTED equ $ff0b
		107	DTEE equ $ff0c
		108	DTEF equ $ff0d
		109	endif
		110
		111	;----------------------------------------------------------------------------
		112	; Ports:
		113
		114	__portbase equ __regbase+$80
		115
		116	P1DR equ __portbase+2 ; Port 1 Data Register (rw/r)
		117	P1DDR equ __portbase+0 ; Port 1 Data Direction Register (w)
		118	if __cpunum=$328
		119	P1CR equ $fffc ; Port 1 Control Register (rw)
		120	elseif
		121	SYSCR1 equ $fefc ; System Control Register 1 (rw)
		122	endif
		123	BRLE equ 3 ; P1CR/SYSCR1: Bus Release Modus
		124	NMIEG equ 4 ; Edge to trigger NMI Input
		125	IRQ0E equ 5 ; Use P15 as IRQ0 ?
		126	IRQ1E equ 6 ; Use P16 as IRQ1 ?
		127
		128	P2DR equ __portbase+3 ; Port 2 Data Register (rw)
		129	P2DDR equ __portbase+1 ; Port 2 Data Direction Register (w)
		130
		131	P3DR equ __portbase+6 ; Port 3 Data Register (rw)
		132	P3DDR equ __portbase+4 ; Port 3 Data Direction Register (w)
		133
		134	P4DR equ __portbase+7 ; Port 4 Data Register (rw)
		135	P4DDR equ __portbase+5 ; Port 4 Data Direction Register (w)
		136
		137	P5DR equ __portbase+10 ; Port 5 Data Register (rw)
		138	P5DDR equ __portbase+8 ; Port 5 Data Direction Register (w)
		139
		140	P6DR equ __portbase+11 ; Port 6 Data Register (rw)
		141	P6DDR equ __portbase+9 ; Port 6 Data Direction Register (w)
		142	if __cpunum<>$328
		143	SYSCR2 equ $fefd ; System Control Register 2 (w)
		144	P9SCI2E equ 0 ; Use P92..P94 for SCI2
		145	P9PWME equ 1 ; Use P92..P94 for PWM
		146	P6PWME equ 2 ; Use P61..P63 as PWM Output
		147	IRQ2E equ 3 ; Use P60 as IRQ2 ?
		148	IRQ3E equ 4 ; Use P61 as IRQ3 ?
		149	IRQ4E equ 5 ; Use P62 as IRQ4 ?
		150	IRQ5E equ 6 ; Use P63 as IRQ5 ?
		151	endif
		152
		153	P7DR equ __portbase+14 ; Port 7 Data Register (rw)
		154	P7DDR equ __portbase+12 ; Port 7 Data Direction Register (w)
		155
		156	P8DR equ __portbase+15 ; Port 8 Data Register (r)
		157
		158	if __cpunum=$388
		159	P9DR equ __portbase+18 ; Port 9 Data Register (r)
		160
		161	PADR equ __portbase+19 ; Port A Data Register (rw)
		162	PADDR equ __portbase+17 ; Port A Data Direction Register (w)
		163
		164	PBDR equ __portbase+22 ; Port B Data Register (rw)
		165	PBDDR equ __portbase+20 ; Port B Data Direction Register (w)
		166	PBPCR equ __portbase+24 ; Port B Pullup Register (w)
		167
		168	PCDR equ __portbase+23 ; Port C Data Register (rw)
		169	PCDDR equ __portbase+21 ; Port C Data Direction Register (w)
		170	PCPCR equ __portbase+25 ; Port C Pullup Register (w)
		171	elseif __cpunum=$328
		172	P9DR equ __portbase+$7f ; Port 9 Data Register (rw)
		173	P9DDR equ __portbase+$7e ; Port 9 Data Direction Register (w)
		174	elseif
		175	P9DR equ __portbase+$ff ; Port 9 Data Register (rw)
		176	P9DDR equ __portbase+$fe ; Port 9 Data Direction Register (w)
		177	endif
		178
		179	;----------------------------------------------------------------------------
		180	; Timer:
		181
		182	__deftimer macro Base,NAME
		183	TCR{NAME} equ Base+0 ; Control Register (rw)
		184	TCSR{NAME} equ Base+1 ; Control/Status Register (rw/r)
		185	FRC{NAME} equ Base+2 ; Count Register (rw, 16 Bit)
		186	OCRA{NAME} equ Base+4 ; Comparator A (rw, 16 Bit)
		187	OCRB{NAME} equ Base+6 ; Comparator B (rw, 16 Bit)
		188	ICR{NAME} equ Base+8 ; Input Capture Register (r, 16 Bit)
		189	endm
		190
		191	__deftimer __regbase+$90,"1"
		192	__deftimer __regbase+$a0,"2"
		193	__deftimer __regbase+$b0,"3"
		194
		195	CKS0 equ 0 ; TCRx: Clock Source Select (rw)
		196	CKS1 equ 1
		197	OEA equ 2 ; Output Comparison Result OCRA (rw)
		198	OEB equ 3 ; Output Comparison Result OCRB (rw)
		199	OVIE equ 4 ; FRC Overflow Interrupt Enable (rw)
		200	OCIEA equ 5 ; OCRA Compare Match Interrupt Enable (rw)
		201	OCIEB equ 6 ; OCRB Compare Match Interrupt Enable (rw)
		202	ICIE equ 7 ; ICR Capture Interrupt Enable (rw)
		203
		204	CCLRA equ 0 ; TCSRx: Reset FRC upon OCRA Compare Match (rw)
		205	IEDG equ 1 ; Input Capture Edge Select (rw)
		206	OLVLA equ 2 ; OCRA Output Signal Polarity Select (rw)
		207	OLVLB equ 3 ; OCRB Output Signal Polarity Select (rw)
		208	OVF equ 4 ; FRC Overflow Flag (r)
		209	OCFA equ 5 ; FRC=OCRA ? (r)
		210	OCFB equ 6 ; FRC=OCRB ? (r)
		211	ICF equ 7 ; Input Capture Flag (r)
		212
		213	; 8-Bit-Timer:
		214
		215	__tcntbase equ __regbase+$d0
		216
		217	TCR4 equ __tcntbase+0 ; Control Register (rw)
		218	CKS2 equ 2 ; Clock Select (Remainder identical to FRCx)
		219	CCLR0 equ 3 ; Reset Mode
		220	CCLR1 equ 4
		221	OVIE_4 equ 5 ; Overflow Interrupt Enable
		222	CMIEA equ 6 ; TCNT=TCORA Interrupt Enable
		223	CMIEB equ 7 ; TCNT=TCORB Interrupt Enable
		224
		225	TCSR4 equ __tcntbase+1 ; Control/Status Register (rw/r)
		226	OS0 equ 0 ; TCORA=TCNT -> TMO
		227	OS1 equ 1
		228	OS2 equ 2 ; TCORB=TCNT -> TMO
		229	OS3 equ 3
		230	OVF_4 equ 5 ; Overflow Flag
		231	CMFA equ 6 ; TCNT=TCORA Flag
		232	CMFB equ 7 ; TCNT=TCORB Flag
		233
		234	TCORA equ __tcntbase+2 ; Time Constant 1 (rw)
		235	TCORB equ __tcntbase+3 ; Time Constant 2 (rw)
		236	TCNT equ __tcntbase+4 ; Count Value (rw)
		237
		238	;----------------------------------------------------------------------------
		239	; Puls Width Modulators:
		240
		241	__defpwm macro Base,NAME
		242	PW{NAME}_TCR equ Base ; Control Register (rw)
		243	PW{NAME}_DTR equ Base+1 ; Pulse Width Register (rw)
		244	PW{NAME}_TCNT equ Base+2 ; Count Value (rw)
		245	endm
		246
		247	__defpwm __regbase+$c0,"1"
		248	__defpwm __regbase+$c4,"2"
		249	__defpwm __regbase+$c8,"3"
		250
		251	OS equ 6 ; PWx_TCR: Output Logic
		252	OE equ 7 ; Output Enable
		253
		254	;----------------------------------------------------------------------------
		255	; Watchdog:
		256
		257	__wdtbase equ __regbase+$ec
		258
		259	WDT_TCSR_R equ __wdtbase+0 ; Control/Status Register (different
		260	WDT_TCSR_W equ __wdtbase+1 ; Write/Read Addresses)
		261	TME equ 5 ; Timer Enable
		262	WTIT equ 6 ; Watchdog/Timer Mode
		263	WDT_OVF equ 7 ; Watchdog Overflow
		264
		265	WDT_TCNT equ __wdtbase+1 ; Count Register (rw)
		266
		267	if __cpunum<>$328
		268	RSTCSR_W equ $ff14 ; Reset Register (different
		269	RSTCSR_R equ $ff15 ; Write/Read Addresses)
		270	RSTOE equ 6 ; Output Watchdog Reset
		271	WRST equ 7 ; Reset by Watchdog ?
		272	endif
		273
		274	;----------------------------------------------------------------------------
		275	; serielle Schnittstelle:
		276
		277	__defsci macro Base,NAME
		278	SMR{NAME} equ Base+0 ; Mode Register (rw)
		279	BRR{NAME} equ Base+1 ; Bit Raten Register (rw)
		280	SCR{NAME} equ Base+2 ; Control Register (rw)
		281	TDR{NAME} equ Base+3 ; Transmit Data (rw)
		282	SSR{NAME} equ Base+4 ; Status Register (rw)
		283	RDR{NAME} equ Base+5 ; Receive Data (r)
		284	endm
		285
		286	if __cpunum=$328
		287	__defsci __regbase+$d8,""
		288	elseif
		289	__defsci __regbase+$d8,"1"
		290	__defsci __regbase+$f0,"2"
		291	endif
		292
		293	STOP equ 3 ; SMRx: Number of Stop Bits
		294	O_E equ 4 ; odd/even Parity
		295	PE equ 5 ; With/Without Parity
		296	CHR equ 6 ; 7/8 Data Bits
		297	C_A equ 7 ; synchronous/asynchronous
		298
		299	CKE0 equ 0 ; SCRx: Output Clock if communicating synchronously
		300	CKE1 equ 1 ; Clock internal/external (-->SCK Input or Output)
		301	RE equ 4 ; Receiver Enable
		302	TE equ 5 ; Transmitter Enable
		303	RIE equ 6 ; Receive Interrupt Enable
		304	TIE equ 7 ; Transmit Interrupt Enable
		305
		306	PER equ 3 ; SSRx: Parity Error
		307	FER equ 4 ; Framing Error
		308	ORER equ 5 ; Receiver Overflow
		309	RDRF equ 6 ; Receiver Full
		310	TDRE equ 7 ; Transmitter Empty
		311
		312	;----------------------------------------------------------------------------
		313	; A/D Converter
		314
		315	__adbase equ __regbase+$e0
		316
		317	ADDRA equ __adbase+0 ; Channel A Conversion Result (r, 16Bit)
		318	ADDRB equ __adbase+2 ; Channel B Conversion Result (r, 16Bit)
		319	ADDRC equ __adbase+4 ; Channel C Conversion Result (r, 16Bit)
		320	ADDRD equ __adbase+6 ; Channel D Conversion Result (r, 16Bit)
		321
		322	ADCSR equ __adbase+8 ; Control/Status Register (rw)
		323	CH0 equ 0 ; Channel Selection
		324	CH1 equ 1
		325	CH2 equ 2
		326	CKS equ 3 ; 274/138 Clocks Conversion Time
		327	SCAN equ 4 ; Single Channel/Scan-Mode
		328	ADST equ 5 ; Start/Stop Converter
		329	ADIE equ 6 ; End of Conversion Interrupt Enable
		330	ADF equ 7 ; End of Conversion Flag
		331
		332	if __cpunum<>$328
		333	ADCR equ __adbase+9 ; Control Register (rw)
		334	TRGE equ 7 ; External Trigger
		335	endif
		336
		337	;----------------------------------------------------------------------------
		338
		339	restore ; re-allow listing
		340
		341	endif ; reg53xinc

Subversion Repositories pentevo

(root)//tools/asl/asl-current/include/reg53x.inc – Rev 1186