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1186 savelij 1
                ifndef  reg68332inc     ; avoid multiple inclusion
2
reg6833xinc     equ     1
3
 
4
                save
5
                listing off             ; no listing over this file
6
                macexp  off             ; saves a bit of time
7
 
8
;****************************************************************************
9
;*                                                                          *
10
;*   AS 1.42 - Datei REG683XX.INC                                           *
11
;*   								            *
12
;*   Contains Register Address Definitions for 68332, 68340, and 68360      *
13
;*                                                                          *
14
;****************************************************************************
15
 
16
                if      (MOMCPUNAME<>"68332")&&(MOMCPUNAME<>"68340")&&(MOMCPUNAME<>"68360")
17
                 fatal   "wrong target sleected: only 68332, 68340, or 68360 supported"
18
		endif
19
 
20
 
21
                if      MOMPASS=1
22
                 message "CPU32 Register Definitions (C) 1994 Alfred Arnold"
23
                 message "including \{MOMCPU} registers"
24
		endif
25
 
26
;-----------------------------------------------------------------------------
27
; The base is either $fffa00 or $7fa000, this has to be set in advance
28
; (or you live with the default :-) ).
29
; On the 68340, the base may be anywhere.
30
; Since the 68332 does not expose A31..A24, one could place the registers at
31
; $fffffa00 and use short addresses.  Anyone ever tried that?
32
; An alternative is to set the base to 0 befor eincluding this file, so the
33
; symbols may be used as offsets relative to the base.
34
 
35
                ifndef  SIMBase
36
                 if      MOMCPU=$68332
37
SIMBase           equ     $fffa00
38
                 elseif
39
SIMBase           equ     $000000
40
                 endif
41
                endif
42
 
43
;=============================================================================
44
; Since 68360, 68340, and 68332 differ significantly in their register set, 
45
; I did not bother to sort out common registers.
46
 
47
                switch  MOMCPUNAME
48
 
49
;-----------------------------------------------------------------------------
50
 
51
                case    "68360"
52
 
53
;-----------------------------------------------------------------------------
54
 
55
MBAR            equ     $0003ff00       ; [L] Peripherals Start Address (CPU Space!)
56
MBARE           equ     $0003ff04       ; [L] Disable/Enable MBAR
57
 
58
RegBase         equ     SIMBase+$1000   ; Register Start Address
59
 
60
MCR             equ     RegBase+$0000   ; [L] SIM Module Configuration
61
 
62
AVR             equ     RegBase+$0008   ; [B] Enable Auto Vector Interrupts
63
RSR             equ     RegBase+$0009   ; [B] Reset Status
64
CLK0CR          equ     RegBase+$000c   ; [B] Clock Output 2 & 1 Control
65
PLLCR           equ     RegBase+$0010   ; [W] PLL Control
66
CDVCR           equ     RegBase+$0014   ; [W] "Slow" Clock Control
67
PEPAR           equ     RegBase+$0016   ; [W] Port E I/O Pins Assignment
68
SYPCR           equ     RegBase+$0022   ; [B] System Monitors, Bus Timimg
69
SWIV            equ     RegBase+$0023   ; [B] Watchdog Interrupt Vector
70
PICR            equ     RegBase+$0026   ; [W] Periodic Interrupt Interrupt Level and Vector
71
PITR            equ     RegBase+$002a   ; [W] Periodic Interrupt  Counter Value and  Prescaler
72
SWSR            equ     RegBase+$002f   ; [B] Reset Watchdog
73
BKAR            equ     RegBase+$0030   ; [L] Breakpoint Address
74
BKCR            equ     RegBase+$0034   ; [L] Breakpoint Control
75
 
76
GMR             equ     RegBase+$0040   ; [L] Memory Controller Global Control
77
MSTAT           equ     RegBase+$0044   ; [W] Memory-Controller Status
78
BR0             equ     RegBase+$0050   ; [L] CS0 SRAM/DRAM Base
79
OR0             equ     RegBase+$0054   ; [L] CS0 DRAM/SRAM Options
80
BR1             equ     RegBase+$0060   ; [L] CS1 SRAM/DRAM Base
81
OR1             equ     RegBase+$0064   ; [L] CS1 DRAM/SRAM Options
82
BR2             equ     RegBase+$0070   ; [L] CS2 SRAM/DRAM Base
83
OR2             equ     RegBase+$0074   ; [L] CS2 DRAM/SRAM Options
84
BR3             equ     RegBase+$0080   ; [L] CS3 SRAM/DRAM Base
85
OR3             equ     RegBase+$0084   ; [L] CS3 DRAM/SRAM Options
86
BR4             equ     RegBase+$0090   ; [L] CS4 SRAM/DRAM Base
87
OR4             equ     RegBase+$0094   ; [L] CS4 DRAM/SRAM Options
88
BR5             equ     RegBase+$00a0   ; [L] CS5 SRAM/DRAM Base
89
OR5             equ     RegBase+$00a4   ; [L] CS5 DRAM/SRAM Options
90
BR6             equ     RegBase+$00b0   ; [L] CS6 SRAM/DRAM Base
91
OR6             equ     RegBase+$00b4   ; [L] CS6 DRAM/SRAM Options
92
BR7             equ     RegBase+$00c0   ; [L] CS7 SRAM/DRAM Base
93
OR7             equ     RegBase+$00c4   ; [L] CS7 DRAM/SRAM Options
94
 
95
;-----------------------------------------------------------------------------
96
; Communications Controller:
97
 
98
RAMBase         equ     SIMBase         ; [ ] RAM Base Address
99
 
100
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
101
; IDMA:
102
 
103
IDMA1Base       equ     RAMBase+$0e70
104
IDMA2Base       equ     RAMBase+$0f70
105
 
106
ICCR            equ     RegBase+$0500   ; [W] IDMA Channels Configuration
107
CMR1            equ     RegBase+$0504   ; [W] IDMA1 Mode
108
CMR2            equ     RegBase+$0526   ; [W] IDMA2 Mode
109
__defidma       macro   NAME,Adr,IDMABase
110
SAPR{NAME}      equ     Adr             ; [L] Source Address for Memory Copy Transactions
111
DAPR{NAME}      equ     Adr+4           ; [L] Target Address  "    "      "       "
112
BCR{NAME}       equ     Adr+8           ; [L] IDMA Count Register
113
FCR{NAME}       equ     Adr+12          ; [B] Functions Codes
114
CMAR{NAME}      equ     Adr+14          ; [B] Channel Mask
115
CSR{NAME}       equ     Adr+16          ; [B] IDMA Channel Status
116
IDMA{NAME}_IBASE         equ      IDMABase+0     ; [W] Descriptor Base Address
117
IDMA{NAME}_IBPTR         equ      IDMABase+0     ; [W] Descriptor Pointer
118
IDMA{NAME}_ISTATE        equ      IDMABase+0     ; [L] Internal Status
119
IDMA{NAME}_ITEMP         equ      IDMABase+0     ; [L] Temporary Storage
120
                endm
121
                __defidma "1",RegBase+$508
122
                __defidma "2",RegBase+$528
123
 
124
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
125
; SDMA:
126
 
127
SDSR            equ     RegBase+$051c   ; [B] SDMA Status
128
SDCR            equ     RegBase+$051e   ; [W] SDMA Channel Configuration
129
SDAR            equ     RegBase+$0520   ; [L] SDMA Address Register
130
 
131
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
132
; CPIC:
133
 
134
CICR            equ     RegBase+$0540   ; [L] Interrupt Configuration
135
CIPR            equ     RegBase+$0544   ; [L] Interrupt Flags
136
CIMR            equ     RegBase+$0548   ; [L] Interrupt Masks
137
CISR            equ     RegBase+$054c   ; [L] Interrupts Pending
138
 
139
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
140
; PIO:
141
 
142
PADIR           equ     RegBase+$0550   ; [W] Port A Data Direction Register
143
PAPAR           equ     RegBase+$0552   ; [W] Port A Assignment 
144
PAODR           equ     RegBase+$0554   ; [W] Port A Open Drain Control
145
PADAT           equ     RegBase+$0556   ; [W] Port A Data Register
146
 
147
PCDIR           equ     RegBase+$0560   ; [W] Port C Data Direction Register
148
PCPAR           equ     RegBase+$0562   ; [W] Port C Assignment
149
PCSO            equ     RegBase+$0564   ; [W] Port C Special Options
150
PCDAT           equ     RegBase+$0566   ; [W] Port C Data Register
151
PCINT           equ     RegBase+$0568   ; [W] Port C Interrupt Control
152
 
153
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
154
; TIMER:
155
 
156
TimerBase       equ     RAMBase+$0db0
157
 
158
TGCR            equ     RegBase+$0560   ; [W] Timer Global Configuration
159
TMR1            equ     RegBase+$0590   ; [W] Timer 1 Mode
160
TRR1            equ     RegBase+$0594   ; [W] Timer 1 Reference Value
161
TCR1            equ     RegBase+$0598   ; [W] Timer 1 Capture Value
162
TCN1            equ     RegBase+$059c   ; [W] Timer 1 Counter Value
163
TER1            equ     RegBase+$05b0   ; [W] Timer 1 Event Report
164
TMR2            equ     RegBase+$0592
165
TRR2            equ     RegBase+$0596
166
TCR2            equ     RegBase+$059a
167
TCN2            equ     RegBase+$059e
168
TER2            equ     RegBase+$05b2
169
TMR3            equ     RegBase+$05a0
170
TRR3            equ     RegBase+$05a4
171
TCR3            equ     RegBase+$05a8
172
TCN3            equ     RegBase+$05ac
173
TER3            equ     RegBase+$05b4
174
TMR4            equ     RegBase+$05a2
175
TRR4            equ     RegBase+$05a6
176
TCR4            equ     RegBase+$05aa
177
TCN4            equ     RegBase+$05ae
178
TER4            equ     RegBase+$05b6
179
TIMER_TM_BASE   equ     TimerBase+$00   ; [W] Table Base Address
180
TIMER_TM_ptr    equ     TimerBase+$02   ; [W] Table Pointer
181
TIMER_R_TMR     equ     TimerBase+$04   ; [W] Mode
182
TIMER_R_TMV     equ     TimerBase+$06   ; [W] Valid Register
183
TIMER_TM_cmd    equ     TimerBase+$08   ; [L] Command Register
184
TIMER_TM_cnt    equ     TimerBase+$0c   ; [L] Internal Counter
185
 
186
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
187
; CP:
188
 
189
MiscBase        equ     RAMBase+$0cb0
190
 
191
CR              equ     RegBase+$05c0   ; [W] Command Register
192
RCCR            equ     RegBase+$05c4   ; [W] RISC-Controller Configuration
193
RTER            equ     RegBase+$05d6   ; [W] Timer Events
194
RTMR            equ     RegBase+$05da   ; [W] Timer Mask
195
CP_REV_num      equ     MiscBase        ; [W] Microcode Revision Number
196
 
197
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
198
; BRG:
199
 
200
BRGC1           equ     RegBase+$05f0   ; [L] Baud Rate Generator 1 Configration
201
BRGC2           equ     RegBase+$05f4
202
BRGC3           equ     RegBase+$05f8
203
BRGC4           equ     RegBase+$05fc
204
 
205
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
206
; SCC:
207
 
208
SCC1Base        equ     RAMBase+$0c00
209
SCC2Base        equ     RAMBase+$0d00
210
SCC3Base        equ     RAMBase+$0e00
211
SCC4Base        equ     RAMBase+$0f00
212
 
213
__defscc        macro   NAME,Adr,SCCBase
214
GSMR_L{NAME}    equ     Adr+0           ; [Q] Mode
215
GSMR_H{NAME}    equ     Adr+4
216
PSMR{NAME}      equ     Adr+8           ; [W] Protocol Specific Mode
217
TODR{NAME}      equ     Adr+12          ; [W] Force Transmission Start
218
DSR{NAME}       equ     Adr+14          ; [W] SCCx Synchronisation Pattern
219
SCCE{NAME}      equ     Adr+16          ; [W] UART Event Register
220
SCCM{NAME}      equ     Adr+20          ; [W] UART Event Mask
221
SCCS{NAME}      equ     Adr+23          ; [B] UART Status
222
SCC{NAME}_RBASE           equ     SCCBase+$00     ; [W] Receive Buffer Start Address
223
SCC{NAME}_TBASE           equ     SCCBase+$02     ; [W] Transmit Buffer Start Address
224
SCC{NAME}_RFCR            equ     SCCBase+$04     ; [B] Receive Address Space
225
SCC{NAME}_TFCR            equ     SCCBase+$05     ; [B] Transmit Address Space
226
SCC{NAME}_MRBLR           equ     SCCBase+$06     ; [W] Receive Buffer Length
227
SCC{NAME}_RSTATE          equ     SCCBase+$08     ; [L] Receiver Status
228
SCC{NAME}_RBPTR           equ     SCCBase+$10     ; [W] Receive Address Pointer
229
SCC{NAME}_TSTATE          equ     SCCBase+$18     ; [L] Transmitter Status
230
SCC{NAME}_TBPTR           equ     SCCBase+$20     ; [W] Transmit Address Pointer
231
SCC{NAME}_RCRC            equ     SCCBase+$28     ; [L] Receive CRC
232
SCC{NAME}_TCRC            equ     SCCBase+$2c     ; [L] Transmit CRC
233
SCC{NAME}_MAX_IDL         equ     SCCBase+$38     ; [W] --UART-- Maximum Number of Idle Characters
234
SCC{NAME}_IDLC            equ     SCCBase+$3a     ; [W] Temporary Idle Counter
235
SCC{NAME}_BRKCR           equ     SCCBase+$3c     ; [W] Number of Transmit Breaks
236
SCC{NAME}_PAREC           equ     SCCBase+$3e     ; [W] Parity Error Counter
237
SCC{NAME}_FRMEC           equ     SCCBase+$40     ; [W] Framing Error Counter
238
SCC{NAME}_NOSEC           equ     SCCBase+$42     ; [W] Noise Counter
239
SCC{NAME}_BRKEC           equ     SCCBase+$44     ; [W] Break Condition
240
SCC{NAME}_BRKLN           equ     SCCBase+$46     ; [W] Length of most recent Break
241
SCC{NAME}_UADDR1          equ     SCCBase+$48     ; [W] Slave Addresse
242
SCC{NAME}_UADDR2          equ     SCCBase+$4a     ; [W]
243
SCC{NAME}_RTEMP           equ     SCCBase+$4c     ; [W] Temporary Storage
244
SCC{NAME}_TOSEQ           equ     SCCBase+$4e     ; [W] Out-of-Sequence Characters
245
SCC{NAME}_CHARACTER1      equ     SCCBase+$50     ; [W] Characters that generate Interrupts
246
SCC{NAME}_CHARACTER2      equ     SCCBase+$52     ; [W]
247
SCC{NAME}_CHARACTER3      equ     SCCBase+$54     ; [W]
248
SCC{NAME}_CHARACTER4      equ     SCCBase+$56     ; [W]
249
SCC{NAME}_CHARACTER5      equ     SCCBase+$58     ; [W]
250
SCC{NAME}_CHARACTER6      equ     SCCBase+$5a     ; [W]
251
SCC{NAME}_CHARACTER7      equ     SCCBase+$5c     ; [W]
252
SCC{NAME}_CHARACTER8      equ     SCCBase+$5e     ; [W]
253
SCC{NAME}_RCCM            equ     SCCBase+$60     ; [W] Received Characters Mask
254
SCC{NAME}_RCCR            equ     SCCBase+$62     ; [W] Received Character
255
SCC{NAME}_RLBC            equ     SCCBase+$64     ; [W] Most Recent Break Character
256
SCC{NAME}_C_MASK          equ     SCCBase+$34     ; [L] --HDLC-- CRC Polynom
257
SCC{NAME}_C_PRES          equ     SCCBase+$38     ; [L] CRC Start Value
258
SCC{NAME}_DISFC           equ     SCCBase+$3c     ; [W] Discarded Frames Counter
259
SCC{NAME}_CRCEC           equ     SCCBase+$3e     ; [W] CRC Errors Counter
260
SCC{NAME}_ABTSC           equ     SCCBase+$40     ; [W] Aborts Counter
261
SCC{NAME}_NMARC           equ     SCCBase+$42     ; [W] Non-Matching Addresses Counter
262
SCC{NAME}_RETRC           equ     SCCBase+$44     ; [W] Retransmissions Counter
263
SCC{NAME}_MFLR            equ     SCCBase+$46     ; [W] Maximal Frame Length
264
SCC{NAME}_MAX_cnt         equ     SCCBase+$48     ; [W] Length Counter
265
SCC{NAME}_RFTHR           equ     SCCBase+$4a     ; [W] Received Frames Threshold
266
SCC{NAME}_RFCNT           equ     SCCBase+$4c     ; [W] Received Frames Count
267
SCC{NAME}_HMASK           equ     SCCBase+$4e     ; [W] Address Mask
268
SCC{NAME}_HADDR1          equ     SCCBase+$50     ; [W] Addresses
269
SCC{NAME}_HADDR2          equ     SCCBase+$52     ; [W]
270
SCC{NAME}_HADRR3          equ     SCCBase+$54     ; [W]
271
SCC{NAME}_HADDR4          equ     SCCBase+$56     ; [W]
272
SCC{NAME}_TMP             equ     SCCBase+$58     ; [W] Temporary Storage
273
SCC{NAME}_TMP_MB          equ     SCCBase+$5a     ; [W]     "        "
274
SCC{NAME}_CRCC            equ     SCCBase+$34     ; [L] --BISYNC-- Temporary CRC Value
275
SCC{NAME}_PRCRC           equ     SCCBase+$38     ; [W] Receiver Preset for CRC
276
SCC{NAME}_PTCRC           equ     SCCBase+$3a     ; [W] Transmitter Preset for CRC
277
SCC{NAME}_B_PAREC         equ     SCCBase+$3c     ; [W] Receiver Parity Errors Counter
278
SCC{NAME}_BSYNC           equ     SCCBase+$3e     ; [W] SYNC Characters
279
SCC{NAME}_BDLE            equ     SCCBase+$40     ; [W] DLE Characters
280
SCC{NAME}_B_CHARACTER1    equ     SCCBase+$42     ; [W] Control Characters
281
SCC{NAME}_B_CHARACTER2    equ     SCCBase+$44     ; [W]
282
SCC{NAME}_B_CHARACTER3    equ     SCCBase+$46     ; [W]
283
SCC{NAME}_B_CHARACTER4    equ     SCCBase+$48     ; [W]
284
SCC{NAME}_B_CHARACTER5    equ     SCCBase+$4a     ; [W]
285
SCC{NAME}_B_CHARACTER6    equ     SCCBase+$4c     ; [W]
286
SCC{NAME}_B_CHARACTER7    equ     SCCBase+$4e     ; [W]
287
SCC{NAME}_B_CHARACTER8    equ     SCCBase+$50     ; [W]
288
SCC{NAME}_B_RCCM          equ     SCCBase+$52     ; [W] Receive Control Character Mask
289
SCC{NAME}_CRC_P           equ     SCCBase+$30     ; [L] --Transparent-- CRC Preset
290
SCC{NAME}_CRC_C           equ     SCCBase+$34     ; [L] CRC Constant
291
SCC{NAME}_E_C_PRES        equ     SCCBase+$30     ; [L] --Ethernet-- CRC Preset
292
SCC{NAME}_E_C_MASK        equ     SCCBase+$34     ; [L] CRC Mask
293
SCC{NAME}_E_CRCEC         equ     SCCBase+$38     ; [L] CRC Error Counter
294
SCC{NAME}_ALEC            equ     SCCBase+$3c     ; [L] Alignment Error Counter
295
SCC{NAME}_E_DISFC         equ     SCCBase+$40     ; [L] Discarded Frames Counter
296
SCC{NAME}_PADS            equ     SCCBase+$44     ; [W] Padding Characters for Short Frames
297
SCC{NAME}_RET_Lim         equ     SCCBase+$46     ; [W] Maximum Number of Retries
298
SCC{NAME}_RET_cnt         equ     SCCBase+$48     ; [W] Current Number of Retries
299
SCC{NAME}_E_MFLR          equ     SCCBase+$4a     ; [W] Maximum Frame Length
300
SCC{NAME}_MINFLR          equ     SCCBase+$4c     ; [W] Minimum Frame Length
301
SCC{NAME}_MAXD1           equ     SCCBase+$4e     ; [W] Maximal Length DMA1
302
SCC{NAME}_MAXD2           equ     SCCBase+$50     ; [W] Maximal Length DMA2
303
SCC{NAME}_MAXD            equ     SCCBase+$52     ; [W] Rx Max DMA
304
SCC{NAME}_DMA_cnt         equ     SCCBase+$54     ; [W] DMA Counter Reception
305
SCC{NAME}_MAX_b           equ     SCCBase+$56     ; [W] Maximum BD Byte Count
306
SCC{NAME}_GADDR1          equ     SCCBase+$58     ; [W] Group Address Filter
307
SCC{NAME}_GADDR2          equ     SCCBase+$5a     ; [W]
308
SCC{NAME}_GADDR3          equ     SCCBase+$5c     ; [W]
309
SCC{NAME}_GADDR4          equ     SCCBase+$5e     ; [W]
310
SCC{NAME}_TBUF0.data0     equ     SCCBase+$60     ; [L] Save Areas - Current Frame
311
SCC{NAME}_TBUF0.data1     equ     SCCBase+$64     ; [L]
312
SCC{NAME}_TBUF0.rba0      equ     SCCBase+$68     ; [L]
313
SCC{NAME}_TBUF0.crc       equ     SCCBase+$6c     ; [L]
314
SCC{NAME}_TBUF0.bcnt      equ     SCCBase+$70     ; [W]
315
SCC{NAME}_PADDR1_H        equ     SCCBase+$72     ; [W] Physical Address
316
SCC{NAME}_PADDR1_M        equ     SCCBase+$74     ; [W]
317
SCC{NAME}_PADDR1_L        equ     SCCBase+$76     ; [W]
318
SCC{NAME}_P_Per           equ     SCCBase+$78     ; [W] Persistence
319
SCC{NAME}_RFBD_ptr        equ     SCCBase+$7a     ; [W] Rx First BD Counter
320
SCC{NAME}_TFBD_ptr        equ     SCCBase+$7c     ; [W] Tx First BD Pointer
321
SCC{NAME}_TLBD_ptr        equ     SCCBase+$7e     ; [W] Tx Last BD Pointer
322
SCC{NAME}_TBUF1.data0     equ     SCCBase+$80     ; [L] Save Areas - Next Frame
323
SCC{NAME}_TBUF1.data1     equ     SCCBase+$84     ; [L]
324
SCC{NAME}_TBUF1.rba0      equ     SCCBase+$88     ; [L]
325
SCC{NAME}_TBUF1.crc       equ     SCCBase+$8c     ; [L]
326
SCC{NAME}_TBUF1.bcnt      equ     SCCBase+$90     ; [W]
327
SCC{NAME}_TX_len          equ     SCCBase+$92     ; [W] Tx Frame Length Counter
328
SCC{NAME}_IADDR1          equ     SCCBase+$94     ; [W] Individual Address Filters
329
SCC{NAME}_IADDR2          equ     SCCBase+$96     ; [W]
330
SCC{NAME}_IADDR3          equ     SCCBase+$98     ; [W]
331
SCC{NAME}_IADDR4          equ     SCCBase+$9a     ; [W]
332
SCC{NAME}_BOFF_CNT        equ     SCCBase+$9c     ; [W] Backoff Counter
333
SCC{NAME}_TADDR_H         equ     SCCBase+$9e     ; [W] Temporary Address
334
SCC{NAME}_TADDR_M         equ     SCCBase+$9a     ; [W]
335
SCC{NAME}_TADDR_L         equ     SCCBase+$a0     ; [W]
336
                endm
337
                __defscc "1",RegBase+$0600,SCC1Base
338
                __defscc "2",RegBase+$0620,SCC2Base
339
                __defscc "3",RegBase+$0640,SCC3Base
340
                __defscc "4",RegBase+$0660,SCC4Base
341
 
342
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
343
; SMC:
344
 
345
SMC1Base        equ     RAMBase+$0e80
346
SMC2Base        equ     RAMBase+$0f80
347
 
348
__defsmc        macro   NAME,Adr,SMCBase
349
SMCMR{NAME}     equ     Adr+0           ; [W] Transparent Mode
350
SMCE{NAME}      equ     Adr+4           ; [B] Event Register
351
SMCM{NAME}      equ     Adr+8           ; [W] Mode
352
SMC{NAME}_RBASE           equ     SMCBase+$00     ; [W] Receive Buffer Descriptor Address
353
SMC{NAME}_TBASE           equ     SMCBase+$02     ; [W] Transmit Buffer Descriptor Address
354
SMC{NAME}_RFCR            equ     SMCBase+$04     ; [B] Receive Function Code
355
SMC{NAME}_TFCR            equ     SMCBase+$05     ; [B] Transmit Function Code
356
SMC{NAME}_MRBLR           equ     SMCBase+$06     ; [W] Maximum Length Receive Buffer
357
SMC{NAME}_RSTATE          equ     SMCBase+$08     ; [L] Internal Receiver Status
358
SMC{NAME}_RBPTR           equ     SMCBase+$10     ; [W] Rx Buffer Descriptor pointer
359
SMC{NAME}_TSTATE          equ     SMCBase+$18     ; [L] Internal Transmitter Status
360
SMC{NAME}_TBPTR           equ     SMCBase+$20     ; [W] Tx Buffer Descriptor Pointer
361
SMC{NAME}_MAX_IDL         equ     SMCBase+$28     ; [W] --UART-- Maximum Number Idle Characters
362
SMC{NAME}_IDLC            equ     SMCBase+$28     ; [W] Idle Counter
363
SMC{NAME}_BRKLN           equ     SMCBase+$28     ; [W] Length of last Break Character
364
SMC{NAME}_BRKEC           equ     SMCBase+$28     ; [W] Receive Break Condition Counter
365
SMC{NAME}_BRKCR           equ     SMCBase+$28     ; [W] Transmit Break Counter
366
SMC{NAME}_R_mask          equ     SMCBase+$28     ; [W] Temporary Bit Mask
367
SMC{NAME}_M_RxBD          equ     SMCBase+$00     ; [W] --GCI-- Monitor Channel Rx
368
SMC{NAME}_M_TxBD          equ     SMCBase+$02     ; [W] Monitor Channel Tx
369
SMC{NAME}_CI_RxBD         equ     SMCBase+$04     ; [W] C/I Channel Rx
370
SMC{NAME}_CI_TxBD         equ     SMCBase+$06     ; [W] C/I Channel Tx
371
SMC{NAME}_M_RxD           equ     SMCBase+$0c     ; [W] Monitor Rx Data
372
SMC{NAME}_M_TxD           equ     SMCBase+$0e     ; [W] Monitor Tx Data
373
SMC{NAME}_CI_RxD          equ     SMCBase+$10     ; [W] C/I Rx Data
374
SMC{NAME}_CI_TxD          equ     SMCBase+$12     ; [W] C/I Tx Data
375
                endm
376
                __defsmc "1",RegBase+$0682,SMC1Base
377
                __defsmc "2",RegBase+$0692,SMC2Base
378
 
379
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
380
; SPI:
381
 
382
SPIBase         equ     RAMBase+$0d80
383
 
384
SPMODE          equ     RegBase+$06a0   ; [W] Mode Rregister
385
SPIE            equ     RegBase+$06a6   ; [B] Event Register
386
SPIM            equ     RegBase+$06aa   ; [B] Mask Register
387
SPICOM          equ     RegBase+$06ad   ; [B] Command Register
388
SPI_RBASE       equ     SPIBase+$00     ; [W] Receive Descriptor Address
389
SPI_TBASE       equ     SPIBase+$02     ; [W] Transmit Descriptor Address
390
SPI_RFCR        equ     SPIBase+$04     ; [B] Receive Function Code
391
SPI_TFCR        equ     SPIBase+$05     ; [B] Transmit Function Code
392
SPI_MRBLR       equ     SPIBase+$06     ; [W] Maximum Length Receive Buffer
393
SPI_RSTATE      equ     SPIBase+$08     ; [L] Receiver Status
394
SPI_RBPTR       equ     SPIBase+$10     ; [W] Currently Active Receive Descriptor
395
SPI_TSTATE      equ     SPIBase+$18     ; [L] Trannsmitter Status
396
SPI_TBPTR       equ     SPIBase+$20     ; [W] Currently Active Transmit Descriptor
397
 
398
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
399
; PIP:
400
 
401
PIPBase         equ     SMC2Base
402
 
403
PIPC            equ     RegBase+$06b2   ; [W] Configuration Register
404
PTPR            equ     RegBase+$06b6   ; [W] Timing Parameters
405
PIPE            equ     SMCE2           ; [B] Event Register, overlayed!!
406
PBDIR           equ     RegBase+$06b8   ; [L] Port B Data Direction Register
407
PBPAR           equ     RegBase+$06bc   ; [L] Port B Assignment
408
PBODR           equ     RegBase+$06c2   ; [W] Port B Open Drain Control Bits
409
PBDAT           equ     RegBase+$06c4   ; [L] Port B Data Register
410
PIP_RBASE       equ     PIPBase+$00     ; [W] Receive Descriptor Address
411
PIP_TBASE       equ     PIPBase+$02     ; [W] Transmit Descriptor Address
412
PIP_CFCR        equ     PIPBase+$04     ; [B] Funktion Code
413
PIP_SMASK       equ     PIPBase+$05     ; [B] Status Mask
414
PIP_MRBLR       equ     PIPBase+$06     ; [W] Maximum Length of Receive Buffer
415
PIP_RSTATE      equ     PIPBase+$08     ; [L] Receiver Status
416
PIP_R_PTR       equ     PIPBase+$0c     ; [L] Internal Receive Data Pointer
417
PIP_RBPTR       equ     PIPBase+$10     ; [W] Current Receive Descriptor
418
PIP_R_CNT       equ     PIPBase+$12     ; [W] Receive Byte Counter
419
PIP_RTEMP       equ     PIPBase+$14     ; [L] Temporary Storage
420
PIP_TSTATE      equ     PIPBase+$18     ; [L] Transmitter Status
421
PIP_T_PTR       equ     PIPBase+$1c     ; [L] Current Transmit Data Pointer
422
PIP_TBPTR       equ     PIPBase+$20     ; [W] Current Transmit Data Descriptor
423
PIP_T_CNT       equ     PIPBase+$22     ; [W] Transmit Byte Counter
424
PIP_TTEMP       equ     PIPBase+$24     ; [L] Temporary Storage
425
PIP_MAX_SL      equ     PIPBase+$28     ; [W] Maximuma Sleep Time
426
PIP_SL_CNT      equ     PIPBase+$2a     ; [W] Sleep Counter
427
PIP_CHARACTER1  equ     PIPBase+$2c     ; [W] Control Characters
428
PIP_CHARACTER2  equ     PIPBase+$2e
429
PIP_CHARACTER3  equ     PIPBase+$30
430
PIP_CHARACTER4  equ     PIPBase+$32
431
PIP_CHARACTER5  equ     PIPBase+$34
432
PIP_CHARACTER6  equ     PIPBase+$36
433
PIP_CHARACTER7  equ     PIPBase+$38
434
PIP_CHARACTER8  equ     PIPBase+$3a
435
PIP_RCCM        equ     PIPBase+$3c     ; [W] Control Character Mask
436
PIP_RCCR        equ     PIPBase+$3e     ; [W] Control Character Register
437
 
438
;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
439
; SI:
440
 
441
SIMODE          equ     RegBase+$06e0   ; [L] Serial Interface Mode
442
SIGMR           equ     RegBase+$06e4   ; [B] Global Mode Setting
443
SISTR           equ     RegBase+$06e6   ; [B] Address of Router RAM
444
SICMR           equ     RegBase+$06e7   ; [B] Serial Interface Command Register
445
SICR            equ     RegBase+$06ec   ; [L] Serial Interface Clock Distribution
446
SIRP            equ     RegBase+$06f2   ; [L] RAM Pointer
447
SIRAM           equ     RegBase+$0700   ; [ ] Routing RAM
448
 
449
;=============================================================================
450
 
451
                case    "68340"
452
 
453
;-----------------------------------------------------------------------------
454
; Comments may eventually be a bit less elaborate, since Motorola's Technical
455
; Summary for the 68340 is not so detailed:
456
 
457
SIMBAR          equ     $0003ff00       ; [L] Peripheral Address Setting
458
 
459
MCR             equ     SIMBase+$000    ; [W] SIM Module Configuration
460
 
461
SYNCR           equ     SIMBase+$004    ; [W] Clock Synthesizer Control
462
AVR             equ     SIMBase+$006    ; [B] Auto Vectors
463
RSR             equ     SIMBase+$007    ; [B] Reset Status
464
 
465
PORTA           equ     SIMBase+$011    ; [B] Port A Data Register
466
DDRA            equ     SIMBase+$013    ; [B] Port A Data Direction Register
467
PPRA1           equ     SIMBase+$015    ; [B] Port A Pin Assignment
468
PPRA2           equ     SIMBase+$017    ; [B] 
469
PORTB           equ     SIMBase+$019    ; [B] Port B Data Register
470
PORTB1          equ     SIMBase+$01b    ; [B] ditto
471
DDRB            equ     SIMBase+$01d    ; [B] Port B Data Direction Register
472
PPRARB          equ     SIMBase+$01f    ; [B] Port B Pin Assignment
473
SWIV            equ     SIMBase+$020    ; [B] Software Vectors
474
SYPCR           equ     SIMBase+$021    ; [B] System Protection
475
PICR            equ     SIMBase+$022    ; [W] PIT Control
476
PITR            equ     SIMBase+$024    ; [W] PIT Data Register
477
SWSR            equ     SIMBase+$027    ; [B] Software Service
478
 
479
;-----------------------------------------------------------------------------
480
; Chip Selects:
481
 
482
__cnt           set     0
483
                rept    4
484
__name           set     "\{__CNT}"
485
CS{__name}AM1    set     SIMBase+$040+__cnt*8 ; [W] CSn Address Mask 1
486
CS{__name}AM2    set     SIMBase+$042+__cnt*8 ; [W] CSn Address Mask 2
487
CS{__name}BA1    set     SIMBase+$044+__cnt*8 ; [W] CSn Base Address 1
488
CS{__name}BA2    set     SIMBase+$046+__cnt*8 ; [W] CSn Base Address 2
489
__cnt            set     __cnt+1
490
                endm
491
 
492
;-----------------------------------------------------------------------------
493
; DMA:
494
 
495
DMABase         equ     SIMBase+$780
496
DMAMCR1         equ     DMABase+$000    ; [W] DMA Channel 1 Module Configuration
497
DMAINTR1        equ     DMABase+$004    ; [W] DMA Channel 1 Interrupts
498
DMACCR1         equ     DMABase+$008    ; [W] DMA Channel 1 Control Register
499
DMACSR1         equ     DMABase+$00a    ; [B] DMA Channel 1 Status Register
500
DMAFCR1         equ     DMABase+$00b    ; [B] DMA Channel 1 Function Code Register
501
DMASAR1         equ     DMABase+$00c    ; [L] DMA Channel 1 Source Address
502
DMADAR1         equ     DMABase+$010    ; [L] DMA Channel 1 Destination Address
503
DMABTC1         equ     DMABase+$014    ; [L] DMA Channel 1 Byte Counter
504
DMAMCR2         equ     DMABase+$020    ; ditto for Channel 2
505
DMAINTR2        equ     DMABase+$024
506
DMACCR2         equ     DMABase+$028
507
DMACSR2         equ     DMABase+$02a
508
DMAFCR2         equ     DMABase+$02b
509
DMASAR2         equ     DMABase+$02c
510
DMADAR2         equ     DMABase+$030
511
DMABTC2         equ     DMABase+$034
512
 
513
;-----------------------------------------------------------------------------
514
; Serial Stuff
515
 
516
SMBase          equ     SIMBase+$700
517
SMMCR           equ     SMBase+$000     ; [W] SIM Module Configuration
518
SMILR           equ     SMBase+$004     ; [B] Interrupt Level
519
SMIVR           equ     SMBase+$005     ; [B] Interrupt Vector
520
SMIPCR          equ     SMBase+$014     ; [BR] Pin Change Register
521
SMACR           equ     SMBase+$014     ; [BW] Auxiliary Control register
522
SMISR           equ     SMBase+$015     ; [BR] Interrupt Flags
523
SMIER           equ     SMBase+$015     ; [BW] Interupt Enables
524
SMOPCR          equ     SMBase+$01d     ; [BW] Output Ports Control
525
SMIP            equ     SMBase+$01d     ; [BR] Input Ports Status
526
SMOPS           equ     SMBase+$01e     ; [BW] Individually Set Port Bits
527
SMOPR           equ     SMBase+$01f     ; [BW] Individually Clear Port Bits
528
SMMR1A          equ     SMBase+$010     ; [B] Channel A Mode Register
529
SMMR2A          equ     SMBase+$020     ; [B] Channel A Mode Register
530
SMCSRA          equ     SMBase+$011     ; [BR] Channel A Clock Selection
531
SMSRA           equ     SMBase+$011     ; [BW] Channel A Status Register
532
SMCRA           equ     SMBase+$012     ; [BW] Channel A Command Register
533
SMRBA           equ     SMBase+$013     ; [BR] Channel A Receive Data Register
534
SMTBA           equ     SMBase+$013     ; [BW] Channel A Transmit Data Register
535
SMMR1B          equ     SMBase+$018     ; [B] Channel B Mode Register 1
536
SMMR2B          equ     SMBase+$021     ; [B] Channel B Mode Register 2
537
SMCSRB          equ     SMBase+$019     ; [BR] Channel B Clock Selection
538
SMSRB           equ     SMBase+$019     ; [BW] Channel B Status Register
539
SMCRB           equ     SMBase+$01a     ; [BW] Channel B Command Register
540
SMRBB           equ     SMBase+$01b     ; [BR] Channel B Receive Data Register
541
SMTBB           equ     SMBase+$01b     ; [BW] Channel B Transmit Data Register
542
 
543
;-----------------------------------------------------------------------------
544
; Timer:
545
 
546
TMBase          equ     SIMBase+$600
547
TM1MCR          equ     TMBase+$000     ; [W] Timer 1 Module Configuration
548
TM1IR           equ     TMBase+$004     ; [W] Timer 1 Interrupt Configuration
549
TM1CR           equ     TMBase+$006     ; [W] Timer 1 Control
550
TM1SR           equ     TMBase+$008     ; [W] Timer 1 Status/Prescaler
551
TM1CNTR         equ     TMBase+$00a     ; [W] Timer 1 Count Register
552
TM1PREL1        equ     TMBase+$00c     ; [W] Timer 1 Preset 1
553
TM1PREL2        equ     TMBase+$00e     ; [W] Timer 1 Preset 2
554
TM1COM          equ     TMBase+$010     ; [W] Timer 1 Compare Register
555
TM2MCR          equ     TMBase+$040     ; ditto for Timer 2
556
TM2IR           equ     TMBase+$044
557
TM2CR           equ     TMBase+$046
558
TM2SR           equ     TMBase+$048
559
TM2CNTR         equ     TMBase+$04a
560
TM2PREL1        equ     TMBase+$04c
561
TM2PREL2        equ     TMBase+$04e
562
TM2COM          equ     TMBase+$050
563
 
564
;=============================================================================
565
; 68332 Registers start here
566
 
567
                case    "68332"
568
 
569
;-----------------------------------------------------------------------------
570
; Fundamental SIM Control Registers
571
 
572
SIMCR           equ     SIMBase+$00     ; [W] MCU Configuration
573
SIYPCR          equ     SIMBase+$21     ; [W] Watchdog, Bus Monitor Control
574
SWSR            equ     SIMBase+$27     ; [B] Watchdog Reset (write $55/$aa)
575
PICR            equ     SIMBase+$22     ; [W] Timer Interrupt Control
576
PITR            equ     SIMBase+$24     ; [W] Timer Counter Value
577
 
578
;-----------------------------------------------------------------------------
579
; Processor Clock Synthesizer
580
 
581
SYNCR           equ     SIMBase+$04     ; [W] Clock Synthesizer Control
582
 
583
;-----------------------------------------------------------------------------
584
; Chip Select Outputs
585
 
586
CSPAR0          equ     SIMBase+$44     ; [W] CSBOOT,CS0..CS5 Control
587
CSPAR1          equ     SIMBase+$46     ; [W] CS6..CS10 Control
588
CSBARBT         equ     SIMBase+$48     ; [W] Boot ROM Start Address
589
CSORBT          equ     SIMBase+$4a     ; [W] Boot-ROM Options
590
__cnt           set     0
591
                rept    10              ; only generate 0..9 to avoid hex names
592
__name           set     "\{__CNT}"
593
CSBAR{__name}    equ     SIMBase+$4c+__cnt*4 ; [W] CSn Start Address
594
CSOR{__name}     equ     SIMBase+$4e+__cnt*4 ; [W] CSn Options
595
__cnt            set     __cnt+1
596
                endm
597
CSBAR10         equ     SIMBase+$74     ; [W] CS10 Start Address
598
CSOR10          equ     SIMBase+$76     ; [W] CS10 Options
599
 
600
;-----------------------------------------------------------------------------
601
; Nutzung der SIM-Bits als einfache I/O-Ports
602
 
603
PORTC           equ     SIMBase+$41     ; [B] Port C Data Bits
604
PORTE0          equ     SIMBase+$11     ; [B] Port E Data Bits
605
PORTE1          equ     SIMBase+$13     ; [B] ditto
606
DDRE            equ     SIMBase+$15     ; [B] Port E Data Direction Bits
607
PEPAR           equ     SIMBase+$17     ; [B] Port E Pins as Ports or Bus Signals Control
608
PORTF0          equ     SIMBase+$19     ; [B] Port F Data Bits
609
PORTF1          equ     SIMBase+$1b     ; [B] ditto
610
DDRF            equ     SIMBase+$1d     ; [B] Port F Data Direction Bits
611
PFPAR           equ     SIMBase+$1f     ; [B] Port F Pins as Ports or Bus Signals Control
612
 
613
;-----------------------------------------------------------------------------
614
; Boundary Scan Test of SIM Registers (for Motorola use only...)
615
 
616
SIMTR           equ     SIMBase+$02     ; [W] SIM Test Register
617
SIMTRE          equ     SIMBase+$08     ; [W] E Clock Test Register
618
TSTMSRA         equ     SIMBase+$30     ; [W] Shift Register A (Boundary Scan)
619
TSTMSRB         equ     SIMBase+$32     ; [W] Shift Register B (Boundary Scan)
620
TSTSC           equ     SIMBase+$34     ; [W] Shift Count Register
621
TSTRC           equ     SIMBase+$36     ; [W] Repeat Count Register
622
CREG            equ     SIMBase+$38     ; [W] Boundary Scan Control Register
623
DREG            equ     SIMBase+$3a     ; [W] Distributed Register (?!)
624
 
625
;-----------------------------------------------------------------------------
626
; Programmable Timers:
627
 
628
TPUBase         equ     SIMBase+$400    ; TPU Register Set Base Address
629
TPUMCR          equ     TPUBase+$00     ; [W] TPU Base Configuration
630
TICR            equ     TPUBase+$08     ; [W] TPU Interrupt Control
631
CIER            equ     TPUBase+$0a     ; [W] TPU Interrupt Enable
632
CISR            equ     TPUBase+$20     ; [W] TPU Interrupt Status
633
CFSR0           equ     TPUBase+$0c     ; [W] TPU Operating Modes Channels 12..15
634
CFSR1           equ     TPUBase+$0e     ; [W] TPU Operating Modes Channels  8..11
635
CFSR2           equ     TPUBase+$10     ; [W] TPU Operating Modes Channels  4.. 7
636
CFSR3           equ     TPUBase+$12     ; [W] TPU Operating Modes Channels  0.. 3
637
HSQR0           equ     TPUBase+$14     ; [W] TPU Sub Operating Modes Channels 8..15
638
HSQR1           equ     TPUBase+$16     ; [W] TPU Sub -Operating Modes Channels 0.. 7
639
HSRR0           equ     TPUBase+$18     ; [W] TPU Service Request Bits Channels 8..15
640
HSRR1           equ     TPUBase+$1a     ; [W] TPU Service Request Bits Channels 0.. 7
641
CPR0            equ     TPUBase+$1c     ; [W] TPU Priority Channels 8..15
642
CPR1            equ     TPUBase+$1e     ; [W] TPU Priority Channels 0.. 7
643
DSCR            equ     TPUBase+$04     ; [W] Debug and Test Registers
644
DSSR            equ     TPUBase+$06
645
LR              equ     TPUBase+$22
646
SGLR            equ     TPUBase+$24
647
DCNR            equ     TPUBase+$26
648
TCR             equ     TPUBase+$02
649
 
650
;-----------------------------------------------------------------------------
651
; TPU Command RAM:
652
 
653
TPURAMBase      equ     SIMBase+$100    ; TPURAM Base Address Control Register
654
TRAMMCR         equ     TPURAMBase+$00  ; [B] TPURAM Base Configuration
655
TRAMTST         equ     TPURAMBase+$02  ; [W] TPURAM Test Register
656
TRAMBAR         equ     TPURAMBase+$04  ; [W] TPURAM Base Address
657
 
658
;-----------------------------------------------------------------------------
659
; serielles:
660
 
661
QSMBase         equ     SIMBase+$200    ; Serial Interface Base Address
662
QSMCR           equ     QSMBase+$00     ; [W] QSM Base Configuration
663
QTEST           equ     QSMBase+$02     ; [W] QSM Test Register
664
QILR            equ     QSMBase+$04     ; [B] QSM Interrupt Priorities
665
QIVR            equ     QSMBase+$05     ; [B] QSM Interrupt Vector
666
PORTQS          equ     QSMBase+$15     ; [B] QSM Parallel Port Data Bits
667
PQSPAR          equ     QSMBase+$16     ; [B] Selection Port Bits QSM/Parallel Port
668
DDRQS           equ     QSMBase+$17     ; [B] QSM Parallel Port Data Direction Register
669
SPCR0           equ     QSMBase+$18     ; [W] QSPI Control Register 0
670
SPCR1           equ     QSMBase+$1a     ; [W] QSPI Control Register 1
671
SPCR2           equ     QSMBase+$1c     ; [W] QSPI Control Register 2
672
SPCR3           equ     QSMBase+$1e     ; [B] QSPI Control Register 3
673
SPSR            equ     QSMBase+$1f     ; [B] QSPI Status Register
674
__cnt           set     0               ; QSPI RAM Definition
675
                rept    16
676
__name           set     "\{__CNT}"
677
RR{__name}       equ     QSMBase+$100+__cnt*2 ; [W] Data RAM Reception Side
678
TR{__name}       equ     QSMBase+$120+__cnt*2 ; [W] Data RAM Transmission Side
679
CR{__name}       equ     QSMBase+$140+__cnt   ; [B] Command RAM
680
__cnt            set     __cnt+1
681
                endm
682
SCCR0           equ     QSMBase+$08     ; [W] SCI Control Register 0
683
SCCR1           equ     QSMBase+$0a     ; [W] SCI Control Register 1
684
SCSR            equ     QSMBase+$0c     ; [W] SCI Status Register
685
SCDR            equ     QSMBase+$0e     ; [W] SCI Data Register
686
 
687
;-----------------------------------------------------------------------------
688
 
689
                endcase                 ; of processor distinction
690
 
691
		restore                 ; re-allow listing
692
 
693
                endif                   ; reg6833xinc