Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef __reg72361inc ; avoid multiple inclusion |
| 2 | __reg72361inc equ 1 |
||
| 3 | |||
| 4 | save |
||
| 5 | listing off ; no listing over this file |
||
| 6 | |||
| 7 | ;**************************************************************************** |
||
| 8 | ;* * |
||
| 9 | ;* AS 1.42 - File REG72361.INC * |
||
| 10 | ;* * |
||
| 11 | ;* contains SFR and Bit Definitions for ST72[AR/J/K]361 * |
||
| 12 | ;* * |
||
| 13 | ;* Source: ST72361 Data Sheet, Rev. 3, August 2010, Doc ID 12468 * |
||
| 14 | ;* * |
||
| 15 | ;**************************************************************************** |
||
| 16 | |||
| 17 | ;---------------------------------------------------------------------------- |
||
| 18 | ; Memory Addresses |
||
| 19 | |||
| 20 | RAMSTART label $0080 ; start address internal RAM |
||
| 21 | switch substr(MOMCPUNAME,9,1) |
||
| 22 | case "4","6" |
||
| 23 | RAMEND label $067f ; end " " " |
||
| 24 | case "7","9" |
||
| 25 | RAMEND label $087f ; end " " " |
||
| 26 | endcase |
||
| 27 | |||
| 28 | ;---------------------------------------------------------------------------- |
||
| 29 | ; Interrupt Vectors |
||
| 30 | |||
| 31 | PWM_ART_vect label $ffe0 ; PWM ART Interrupt |
||
| 32 | LINSCI1_vect label $ffe2 ; LINSCI1 Interrupt Vector |
||
| 33 | LINSCI2_vect label $ffe4 ; LINSCI2 Interrupt Vector |
||
| 34 | TIMER16_vect label $ffe6 ; 16-bit Timer Interrupt Vector |
||
| 35 | TIMER8_vect label $ffe8 ; 8-bit Timer Interrupt Vector |
||
| 36 | SPI_vect label $ffea ; SPI Interrupt Vector |
||
| 37 | EI3_vect label $fff0 ; External Interrupt Vector B7..4 |
||
| 38 | EI2_vect label $fff2 ; External Interrupt Vector B3..0 |
||
| 39 | EI1_vect label $fff4 ; External Interrupt Vector F2..0 |
||
| 40 | EI0_vect label $fff6 ; External Interrupt Vector A3..0, shared with |
||
| 41 | AWU_vect label $fff6 ; Auto wake up from halt |
||
| 42 | MCC_RTC_vect label $fff8 ; Main clock controller time base interrupt |
||
| 43 | TLI_vect label $fffa ; Top Level Interrupt |
||
| 44 | TRAP_vect label $fffc ; TRAP (software) Interrupt Vector |
||
| 45 | RESET_vect label $fffe ; RESET Vector |
||
| 46 | |||
| 47 | ;---------------------------------------------------------------------------- |
||
| 48 | ; GPIO |
||
| 49 | |||
| 50 | include "gpio.inc" |
||
| 51 | __defgpio "PA",$0000 |
||
| 52 | __defgpio "PB",$0003 |
||
| 53 | __defgpio "PC",$0006 |
||
| 54 | __defgpio "PD",$0009 |
||
| 55 | __defgpio "PE",$000c |
||
| 56 | __defgpio "PF",$000f |
||
| 57 | |||
| 58 | ;---------------------------------------------------------------------------- |
||
| 59 | ; SPI |
||
| 60 | |||
| 61 | include "spi2.inc" |
||
| 62 | __defspi $0021 |
||
| 63 | |||
| 64 | ;---------------------------------------------------------------------------- |
||
| 65 | ; Flash |
||
| 66 | |||
| 67 | FCSR label $0024 ; Flash Control/Status Register |
||
| 68 | |||
| 69 | ;---------------------------------------------------------------------------- |
||
| 70 | ; ITC |
||
| 71 | |||
| 72 | ISPR0 label $0025 ; Interrupt Software Priority Register 0 |
||
| 73 | I0_0 bit ISPR0,0 |
||
| 74 | I1_0 bit ISPR0,1 |
||
| 75 | I0_1 bit ISPR0,2 |
||
| 76 | I1_1 bit ISPR0,3 |
||
| 77 | I0_2 bit ISPR0,4 |
||
| 78 | I1_2 bit ISPR0,5 |
||
| 79 | I0_3 bit ISPR0,6 |
||
| 80 | I1_3 bit ISPR0,7 |
||
| 81 | ISPR1 label $0026 ; Interrupt Software Priority Register 1 |
||
| 82 | I0_4 bit ISPR1,0 |
||
| 83 | I1_4 bit ISPR1,1 |
||
| 84 | I0_5 bit ISPR1,2 |
||
| 85 | I1_5 bit ISPR1,3 |
||
| 86 | I0_6 bit ISPR1,4 |
||
| 87 | I1_6 bit ISPR1,5 |
||
| 88 | I0_7 bit ISPR1,6 |
||
| 89 | I1_7 bit ISPR1,7 |
||
| 90 | ISPR2 label $0027 ; Interrupt Software Priority Register 2 |
||
| 91 | I0_8 bit ISPR2,0 |
||
| 92 | I1_8 bit ISPR2,1 |
||
| 93 | I0_9 bit ISPR2,2 |
||
| 94 | I1_9 bit ISPR2,3 |
||
| 95 | I0_10 bit ISPR2,4 |
||
| 96 | I1_10 bit ISPR2,5 |
||
| 97 | I0_11 bit ISPR2,6 |
||
| 98 | I1_11 bit ISPR2,7 |
||
| 99 | ISPR3 label $0028 ; Interrupt Software Priority Register 3 |
||
| 100 | I0_12 bit ISPR3,0 |
||
| 101 | I1_12 bit ISPR3,1 |
||
| 102 | I0_13 bit ISPR3,2 |
||
| 103 | I1_13 bit ISPR3,3 |
||
| 104 | EICR0 label $0029 ; External Interrupt Control Register 0 |
||
| 105 | IS3 bfield EICR0,6,2 ; ei3 sensitivity |
||
| 106 | IS2 bfield EICR0,4,2 ; ei2 sensitivity |
||
| 107 | IS1 bfield EICR0,2,2 ; ei1 sensitivity |
||
| 108 | IS0 bfield EICR0,0,2 ; ei0 sensitivity |
||
| 109 | EICR1 label $002a ; External Interrupt Control Register 1 |
||
| 110 | TLIS bit EICR1,1 ; Top Level Interrupt sensitivity |
||
| 111 | TLIE bit EICR1,0 ; Top Level Interrupt enable |
||
| 112 | |||
| 113 | ;---------------------------------------------------------------------------- |
||
| 114 | ; PWM ART |
||
| 115 | |||
| 116 | include "pwm_art.inc" |
||
| 117 | __defpwmart $0031 |
||
| 118 | |||
| 119 | ;---------------------------------------------------------------------------- |
||
| 120 | ; 8-bit Timer |
||
| 121 | |||
| 122 | T8CR2 label $003c ; Timer Control Register 2 |
||
| 123 | T8ICIE bit T8CR2,7 ; Input Capture Interrupt Enable |
||
| 124 | T8OCIE bit T8CR2,6 ; Output Compare Interrupt Enable |
||
| 125 | T8TOIE bit T8CR2,5 ; Timer Overflow Interrupt Enable |
||
| 126 | T8FOLV2 bit T8CR2,4 ; Forced Output Compare 2 |
||
| 127 | T8FOLV1 bit T8CR2,3 ; Forced Output Compare 1 |
||
| 128 | T8OLVL2 bit T8CR2,2 ; Output Level 2 |
||
| 129 | T8IEDG1 bit T8CR2,1 ; Input Edge 1 |
||
| 130 | T8OLVL1 bit T8CR2,0 ; Output Level 1 |
||
| 131 | T8CR1 label $003d ; Timer Control Register 1 |
||
| 132 | T8OC1E bit T8CR1,7 ; Output Compare 1 Pin Enable |
||
| 133 | T8OC2E bit T8CR1,6 ; Output Compare 2 Pin Enable |
||
| 134 | T8OPM bit T8CR1,5 ; One Pulse Mode |
||
| 135 | T8PWM bit T8CR1,4 ; Pulse Width Modulation |
||
| 136 | T8CC bfield T8CR1,2,2 ; Clock Control |
||
| 137 | T8IEDG2 bit T8CR1,1 ; Input Edge 2 |
||
| 138 | T8CSR label $003e ; Timer Control/Status Register |
||
| 139 | T8ICF1 bit T8CSR,7 ; Input Capture Flag 1 |
||
| 140 | T8OCF1 bit T8CSR,6 ; Output Compare Flag 1 |
||
| 141 | T8TOF bit T8CSR,5 ; Timer Overflow Flag |
||
| 142 | T8ICF2 bit T8CSR,4 ; Input Capture Flag 2 |
||
| 143 | T8OCF2 bit T8CSR,3 ; Output Compare Flag 2 |
||
| 144 | T8TIMD bit T8CSR,2 ; Timer disable |
||
| 145 | T8IC1R label $003f ; Timer Input Capture 1 Register |
||
| 146 | T8OC1R label $0040 ; Timer Output Compare 1 Register |
||
| 147 | T8CTR label $0041 ; Timer Counter Register |
||
| 148 | T8ACTR label $0042 ; Timer Alternate Counter Register |
||
| 149 | T8IC2R label $0043 ; Timer Input Capture 2 Register |
||
| 150 | T8OC2R label $0044 ; Timer Output Compare 2 Register |
||
| 151 | |||
| 152 | ;---------------------------------------------------------------------------- |
||
| 153 | ; 16-bit Timer |
||
| 154 | |||
| 155 | include "timer.inc" |
||
| 156 | __deftimer "T16",$0050 |
||
| 157 | T16CSR label T16SR ; Control/Status Register |
||
| 158 | T16TIMD bit T16CSR,2 ; Timer Disable |
||
| 159 | |||
| 160 | ;---------------------------------------------------------------------------- |
||
| 161 | ; LINSCI |
||
| 162 | |||
| 163 | __deflinsci macro Name,Base |
||
| 164 | __NS set "\{NAME}" |
||
| 165 | SCI{__NS}SR label $0050 ; SCI Status Register |
||
| 166 | SCI{__NS}TDRE bit SCI{__NS}SR,7 ; Transmit data register empty |
||
| 167 | SCI{__NS}TC bit SCI{__NS}SR,6 ; Transmission complete |
||
| 168 | SCI{__NS}RDRF bit SCI{__NS}SR,5 ; Received data ready flag |
||
| 169 | SCI{__NS}IDLE bit SCI{__NS}SR,4 ; Idle line detect |
||
| 170 | SCI{__NS}OR bit SCI{__NS}SR,3 ; Overrun error |
||
| 171 | SCI{__NS}NF bit SCI{__NS}SR,2 ; Noise flag |
||
| 172 | SCI{__NS}FE bit SCI{__NS}SR,1 ; Framing error |
||
| 173 | SCI{__NS}PE bit SCI{__NS}SR,0 ; Parity Error |
||
| 174 | SCI{__NS}DR label Base+$01 ; SCI Data Register |
||
| 175 | SCI{__NS}BRR label Base+$02 ; SCI Baud Rate Register |
||
| 176 | SCI{__NS}SCP bfield SCI{__NS}BRR,6,2 ; First SCI Prescaler [1:0] |
||
| 177 | SCI{__NS}SCT bfield SCI{__NS}BRR,3,3 ; SCI Transmitter rate divisor [2:0] |
||
| 178 | SCI{__NS}SCR bfield SCI{__NS}BRR,0,3 ; SCI Receiver rate divisor [2:0] |
||
| 179 | SCI{__NS}CR1 label Base+$03 ; SCI Control Register 1 |
||
| 180 | SCI{__NS}R8 bit SCI{__NS}CR1,7 ; Receive data bit 8 |
||
| 181 | SCI{__NS}T8 bit SCI{__NS}CR1,6 ; Transmit data bit 8 |
||
| 182 | SCI{__NS}SCID bit SCI{__NS}CR1,5 ; SCI Disable |
||
| 183 | SCI{__NS}M bit SCI{__NS}CR1,4 ; Word length |
||
| 184 | SCI{__NS}WAKE bit SCI{__NS}CR1,3 ; Wake-Up method |
||
| 185 | SCI{__NS}PCE bit SCI{__NS}CR1,2 ; Parity control enable |
||
| 186 | SCI{__NS}PS bit SCI{__NS}CR1,1 ; Parity selection |
||
| 187 | SCI{__NS}PIE bit SCI{__NS}CR1,0 ; Parity interrupt enable |
||
| 188 | SCI{__NS}CR2 label Base+$04 ; SCI Control Register 2 |
||
| 189 | SCI{__NS}TIE bit SCI{__NS}CR2,7 ; Transmitter interrupt enable |
||
| 190 | SCI{__NS}TCIE bit SCI{__NS}CR2,6 ; Transmission complete interrupt enable |
||
| 191 | SCI{__NS}RIE bit SCI{__NS}CR2,5 ; Receiver interrupt enable |
||
| 192 | SCI{__NS}ILIE bit SCI{__NS}CR2,4 ; Idle line interrupt enable |
||
| 193 | SCI{__NS}TE bit SCI{__NS}CR2,3 ; Transmitter enable |
||
| 194 | SCI{__NS}RE bit SCI{__NS}CR2,2 ; Receiver enable |
||
| 195 | SCI{__NS}RWU bit SCI{__NS}CR2,1 ; Receiver wake-up |
||
| 196 | SCI{__NS}SBK bit SCI{__NS}CR2,0 ; Send break |
||
| 197 | SCI{__NS}CR3 label Base+$05 ; SCI Control Register 3 |
||
| 198 | SCI{__NS}LINE bit SCI{__NS}CR3,6 ; LIN Mode Enable |
||
| 199 | SCI{__NS}CLKEN bit SCI{__NS}CR3,3 ; Clock Enable |
||
| 200 | SCI{__NS}CPOL bit SCI{__NS}CR3,2 ; Clock Polarity |
||
| 201 | SCI{__NS}CPHA bit SCI{__NS}CR3,1 ; Clock Phase |
||
| 202 | SCI{__NS}LBCL bit SCI{__NS}CR3,0 ; Last bit clock pulse |
||
| 203 | SCI{__NS}ERPR label Base+$06 ; SCI Extended Receive Prescaler Register |
||
| 204 | SCI{__NS}ETPR label Base+$07 ; SCI Extended Transmit Prescaler Register |
||
| 205 | endm |
||
| 206 | __deflinsci "1",$0048 |
||
| 207 | __deflinsci "2",$0060 |
||
| 208 | |||
| 209 | ;---------------------------------------------------------------------------- |
||
| 210 | ; Analog/Digital Converter |
||
| 211 | |||
| 212 | include "adc10.inc" |
||
| 213 | __defadc10 $0045 |
||
| 214 | SLOW bit ADCCSR,4 ; A/D Clock Selection |
||
| 215 | |||
| 216 | restore |
||
| 217 | |||
| 218 | endif ; __reg72361inc |