WebSVN – pentevo – Blame – //tools/asl/asl-current/include/stddef51.inc

Rev	Author	Line No.	Line
1186	savelij	1	ifndef stddef51inc ; avoid multiple inclusion
		2	stddef51inc equ 1
		3
		4	save
		5	listing off ; no listing over this file
		6
		7	;****************************************************************************
		8	;* *
		9	;* AS 1.42 - File STDDEF51.INC *
		10	;* *
		11	;* Holds SFR and Bit Definitions for MCS-51 Processors *
		12	;* *
		13	;****************************************************************************
		14
		15	if (MOMCPUNAME<>"87C750")&&(MOMCPUNAME<>"8051")&&(MOMCPUNAME<>"8052")&&(MOMCPUNAME<>"80C320")&&(MOMCPUNAME<>"80515")&&(MOMCPUNAME<>"80517")
		16	fatal "wrong target selected: only 87C750, 8051, 8052, 80C320, 80515, or 80517 supported"
		17	endif
		18
		19
		20	if MOMPASS=1
		21	message "MCS-51 SFR Definitions (C) 1993 Alfred Arnold/Gabriel Jager"
		22	message "including \{MOMCPU} SFRs"
		23	endif
		24
		25	;----------------------------------------------------------------------------
		26	; first of all, the things that exist (almost) everywhere:
		27
		28	P0 SFRB 80h ; I/O Ports
		29	P1 SFRB 90h
		30	P2 SFRB 0a0h
		31	P3 SFRB 0b0h
		32	RD BIT P3.7 ; Port 3: Write Line
		33	WR BIT P3.6 ; Read Line
		34	T1 BIT P3.5 ; Test Line 1
		35	T0 BIT P3.4 ; Test Line 0
		36	INT1 BIT P3.3 ; External Interrupt 1
		37	INT0 BIT P3.2 ; External Interrupt 0
		38	TXD BIT P3.1 ; Serial Output
		39	RXD BIT P3.0 ; Serial Input
		40	if MOMCPU=80C320H
		41	TXD1 BIT P1.3 ; zweiter Serial Output
		42	RXD1 BIT P1.2 ; zweiter Serial Input
		43	endif
		44
		45	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		46
		47	SP SFR 81h ; Stack Pointer
		48	DPL SFR 82h ; Data Pointer Bits 0..7
		49	DPH SFR 83h ; " Bits 8..15
		50	if MOMCPU=80C320H
		51	DPL0 SFR DPL
		52	DPH0 SFR DPH
		53	DPL1 SFR 84h ; Second Data Pointer 80C320
		54	DPH1 SFR DPL1+1
		55	DPS SFR 86h ; Bit 0 = Select DPTR0<-->DPTR1
		56	endif
		57	PSW SFRB 0d0h ; Processor Status Word
		58	CY BIT PSW.7
		59	AC BIT PSW.6
		60	F0 BIT PSW.5
		61	RS1 BIT PSW.4
		62	RS0 BIT PSW.3
		63	OV BIT PSW.2
		64	P BIT PSW.0
		65	ACC SFRB 0e0h ; Accumulator
		66	B SFRB 0f0h ; Auxiliary Accumulator for MUL/DIV
		67
		68	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		69
		70	SCON SFRB 98h ; Serial Interface: Control Register
		71	SM0 BIT SCON.7 ; Operating Modes
		72	SM1 BIT SCON.6
		73	SM2 BIT SCON.5
		74	REN BIT SCON.4 ; Receiver Enable
		75	TB8 BIT SCON.3 ; 9th Bit to be sent
		76	RB8 BIT SCON.2 ; 9th received bit
		77	TI BIT SCON.1 ; Transmit Interrupt Flag
		78	RI BIT SCON.0 ; Receive Interrupt Flag
		79	SBUF SFR 99h ; Data Register
		80
		81	if MOMCPU=80C320H ; Registers for Second Serial Port
		82	SCON0 SFR SCON
		83	SM0_0 BIT SCON0.7
		84	SM1_0 BIT SCON0.6
		85	SM2_0 BIT SCON0.5
		86	REN_0 BIT SCON0.4
		87	TB8_0 BIT SCON0.3
		88	RB8_0 BIT SCON0.2
		89	TI_0 BIT SCON0.1
		90	RI_0 BIT SCON0.0
		91	SBUF0 SFR SBUF
		92	SCON1 SFR 0c0h ; Control Register
		93	SM0_1 BIT SCON1.7
		94	SM1_1 BIT SCON1.6
		95	SM2_1 BIT SCON1.5
		96	REN_1 BIT SCON1.4
		97	TB8_1 BIT SCON1.3
		98	RB8_1 BIT SCON1.2
		99	TI_1 BIT SCON1.1
		100	RI_1 BIT SCON1.0
		101	SBUF1 SFR 0c1h ; Data Register
		102	endif
		103
		104	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		105
		106	PCON SFR 87h ; Power Management
		107
		108	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		109
		110	TCON SFRB 88h ; Timer 0/1 Control Register
		111	TF1 BIT TCON.7 ; Timer 1 Overflow
		112	TR1 BIT TCON.6 ; Timer 1 Start
		113	TF0 BIT TCON.5 ; Timer 0 Overflow
		114	TR0 BIT TCON.4 ; Timer 0 Start
		115	IE1 BIT TCON.3 ; External Interrupt 1 Flag
		116	IT1 BIT TCON.2 ; External Interrupt 1 Edge Select
		117	IE0 BIT TCON.1 ; External Interrupt 0 Flag
		118	IT0 BIT TCON.0 ; External Interrupt 0 Edge Select
		119	TMOD SFR 89h ; Timer 0/1 Operating Modes Register
		120	TL0 SFR 8ah ; Timer 0 Data
		121	TL1 SFR 8bh
		122	TH0 SFR 8ch ; Timer 1 Data
		123	TH1 SFR 8dh
		124
		125	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		126	; No Timer 2 on 8051
		127
		128	if MOMCPU<>8051h
		129	T2CON SFRB 0c8h ; Timer 2 Control Register
		130	TL2 SFR 0cch ; Timer 2 Data
		131	TH2 SFR 0cdh
		132	if (MOMCPU=8052h)\|\|(MOMCPU=80C320h)
		133	RCAP2L SFR 0cah ; Capture Register
		134	RCAP2H SFR 0cbh
		135	TF2 BIT T2CON.7 ; Timer 2 Overflow
		136	EXF2 BIT T2CON.6 ; Reload Occured
		137	RCLK BIT T2CON.5 ; Timer 2 Delivers RxD-Takt
		138	TCLK BIT T2CON.4 ; Timer 2 Delivers TxD-Takt
		139	EXEN2 BIT T2CON.3 ; Timer 2 External Enable
		140	TR2 BIT T2CON.2 ; Timer 2 Start
		141	CT2 BIT T2CON.1 ; Timer 2 as Counter
		142	CPRL2 BIT T2CON.0 ; Enable Capture
		143	elseif
		144	CRCL SFR 0cah ; other Names on 80515 !!
		145	CRCH SFR 0cbh
		146	T2PS BIT T2CON.7
		147	I3FR BIT T2CON.6
		148	I2FR BIT T2CON.5
		149	T2R1 BIT T2CON.4
		150	T2R0 BIT T2CON.3
		151	T2CM BIT T2CON.2
		152	T2I1 BIT T2CON.1
		153	T2I0 BIT T2CON.0
		154	endif
		155	endif
		156
		157	if MOMCPU=80C320H ; 80C320 Clock Selection
		158	CKCON SFR 8eh ; Bit 3,4,5 <--> Timer 0,1,2
		159	endif ; Bit 6,7 <--> Watchdog Timeout
		160
		161	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		162	; 80C320 Watchdog
		163
		164	if MOMCPU=80C320h
		165	WDCON SFRB 0d8h
		166	RWT BIT WDCON.0 ; Watchdog Reset
		167	EWT BIT WDCON.1 ; Watchdog Enable
		168	WTRF BIT WDCON.2 ; Watchdog Reset Flag
		169	WDIF BIT WDCON.3 ; Interrupt '512 Clocks to Reset' Flag
		170	PFI BIT WDCON.4 ; Power Fail Interrupt Flag
		171	EPFI BIT WDCON.5 ; Power Fail Interrupt Enable
		172	POR BIT WDCON.6
		173	WD_SMOD BIT WDCON.7
		174	TA SFR 0c7h ; write AA 55 to get access to special
		175	endif ; registers
		176
		177	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		178	;
		179
		180	if MOMCPU=80C320H
		181	SADDR0 SFR 0a9h ; Serial Port 0 Slave Address
		182	SADDR1 SFR 0aah ; Serial Port 1 Slave Address
		183	SADEN0 SFR 0b9h ; Enable Bits in SADDR0
		184	SADEN1 SFR 0bah ; Enable Bits in SADDR1
		185	endif
		186
		187	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		188	; Additional 80515/80517 Register
		189
		190	if (MOMCPU=80515h)\|\|(MOMCPU=80517h)
		191	P4 SFRB 0e8h
		192	P5 SFRB 0f8h
		193	P6 SFR 0DBh
		194
		195	CCEN SFR 0c1h
		196	CCH3 SFR 0c7h
		197	CCL3 SFR 0c6h
		198	CCH2 SFR 0c5h
		199	CCL2 SFR 0c4h
		200	CCH1 SFR 0c3h
		201	CCL1 SFR 0c2h
		202
		203	ADCON SFRB 0d8h ; Other Names on 80515/80517
		204	BD BIT ADCON.7
		205	CLK BIT ADCON.6
		206	BSY BIT ADCON.4
		207	ADM BIT ADCON.3
		208	MX2 BIT ADCON.2
		209	MX1 BIT ADCON.1
		210	MX0 BIT ADCON.0
		211	ADDAT SFR 0d9h
		212	DAPR SFR 0dah
		213	endif
		214
		215	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		216	; Additional 80517-Register
		217
		218	if MOMCPU=80517h
		219
		220	DPSEL SFR 92h ; Data Pointer Select
		221	ADCON1 SFR 0dch ; A/D Converter Control 1
		222	CTCON SFR 0e1h ; Compare Timer Control
		223	IEN2 SFR 9ah
		224	ARCON SFR 0efh
		225	MD0 SFR 0e9h ;] Multiplication
		226	MD1 SFR 0eah ;] and
		227	MD2 SFR 0ebh ;] Division Registers
		228	MD3 SFR 0ech ;]
		229	MD4 SFR 0edh ;] 1 - 5
		230	MD5 SFR 0eeh ;]
		231	CC4EN SFR 0c9h
		232	CCH4 SFR 0cfh
		233	CCL4 SFR 0ceh
		234	CMEN SFR 0f6h
		235	CMH0 SFR 0d3h
		236	CMH1 SFR 0d5h
		237	CMH2 SFR 0d7h
		238	CMH3 SFR 0e3h
		239	CMH4 SFR 0e5h
		240	CMH5 SFR 0e7h
		241	CMH6 SFR 0f3h
		242	CMH7 SFR 0f5h
		243	CML0 SFR 0d2h
		244	CML1 SFR 0d4h
		245	CML2 SFR 0d6h
		246	CML3 SFR 0e2h
		247	CML4 SFR 0e4h
		248	CML5 SFR 0e6h
		249	CML6 SFR 0f8h
		250	CML7 SFR 0f4h
		251	CMSEL SFR 0f7h
		252	CTRELH SFR 0dfh
		253	CTRELL SFR 0deh
		254	P6 SFR 0fah ; ??? Bit Addressable
		255	P7 SFR 0dbh ; ??? Bit Addressable
		256	P8 SFR 0ddH ; ??? Bit Addressable
		257	ADCON0 SFR 0d8h ; A/D Converter Control 0
		258	S0BUF SFR 99h ;] Control
		259	S0CON SFR 98h ;] of
		260	S1BUF SFR 9ch ;] Serial
		261	S1CON SFR 9bh ;] Interfaces
		262	S1REL SFR 9dh ;] 0 and 0
		263	WDTREL SFR 86h ;]
		264
		265	endif
		266
		267	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		268	; Interrupt Control Register: not compatible between 8051/52 and 80515/80517 !!!
		269
		270	if (MOMCPU=80515h)\|\|(MOMCPU=80517h)
		271	IEN0 SFRB 0a8h
		272	EAL BIT IEN0.7
		273	WDT BIT IEN0.6
		274	ET2 BIT IEN0.5
		275	ES BIT IEN0.4
		276	ET1 BIT IEN0.3
		277	EX1 BIT IEN0.2
		278	ET0 BIT IEN0.1
		279	EX0 BIT IEN0.0
		280	IEN1 SFRB 0b8h
		281	EXEN2 BIT IEN1.7
		282	SWDT BIT IEN1.6
		283	EX6 BIT IEN1.5
		284	EX5 BIT IEN1.4
		285	EX4 BIT IEN1.3
		286	EX3 BIT IEN1.2
		287	EX2 BIT IEN1.1
		288	EADC BIT IEN1.0
		289	IP0 SFR 0a9h
		290	IP1 SFR 0b9h
		291	IRCON SFRB 0c0h
		292	EXF2 BIT IRCON.7
		293	TF2 BIT IRCON.6
		294	IEX6 BIT IRCON.5
		295	IEX5 BIT IRCON.4
		296	IEX4 BIT IRCON.3
		297	IEX3 BIT IRCON.2
		298	IEX2 BIT IRCON.1
		299	IADC BIT IRCON.0
		300	elseif
		301	IE SFRB 0a8h ; Interrupt Enable
		302	IEC SFRB IE
		303	EA BIT IE.7 ; Global Interrupt Enable
		304	ES BIT IE.4 ; Serial Interface Interrupts Enable
		305	ET1 BIT IE.3 ; Timer 1 Interrupt Enable
		306	EX1 BIT IE.2 ; External Interrupt 1 Enable
		307	ET0 BIT IE.1 ; Timer 0 Interrupt Enable
		308	EX0 BIT IE.0 ; External Interrupt 0 Enable
		309	IP SFRB 0b8h ; Interrupt Priorities
		310	IPC SFRB IP
		311	PS BIT IP.4 ; Serial Interrupt Priority
		312	PT1 BIT IP.3 ; Timer 1 Interrupt Priority
		313	PX1 BIT IP.2 ; External Interrupt 1 Priority
		314	PT0 BIT IP.1 ; Timer 0 Interrupt Priority
		315	PX0 BIT IP.0 ; External Interrupt 0 Priority
		316	if MOMCPU=8052h
		317	ET2 BIT IE.5 ; Timer 2 Interrupt Enable
		318	PT2 BIT IP.5 ; Timer 2 Interrupt Priority
		319	endif
		320	endif
		321
		322	if MOMCPU=80C320H ; 80C320 Extended Interrupts
		323	EIE SFRB 0e8h
		324	EWDI BIT EIE.4 ; Watchdog Interrupt Enable
		325	EX5 BIT EIE.3 ; External Interrupts 2..5 Enable
		326	EX4 BIT EIE.2
		327	EX3 BIT EIE.1
		328	EX2 BIT EIE.0
		329	EIP SFRB 0f8h
		330	PWDI BIT EIP.4 ; Watchdog-Interrupt Priority
		331	PX5 BIT EIP.3 ; External Interrupts 2..5 Priority
		332	PX4 BIT EIP.2
		333	PX3 BIT EIP.1
		334	PX2 BIT EIP.0
		335	EXIF SFR 91h ; Extended Interrupt Flag Register
		336	endif
		337
		338	;---------------------------------------------------------------------------
		339	; Since the 8051 has no instructions to pus the registers, this has to be done
		340	; via direct addressing, which requires knowledge of the currently active bank.
		341	; The macro USING is provided for doing this. It holds the addresses of the
		342	; currently active registers in symbols AR0..AR7. USING expects the bank
		343	; number as argument.
		344
		345	Bank0 equ 0 ; For Completeness...
		346	Bank1 equ 1
		347	Bank2 equ 2
		348	Bank3 equ 3
		349
		350	using macro bank
		351	if (bank<0)\|\|(bank>3) ; only bank 0..3 allowed
		352	error "Falsche Banknummer: \{BANK}"
		353	endif
		354
		355	ifdef RegUsage ; Book-Keeping about Used Banks
		356	RegUsage set RegUsage\|(2^bank)
		357	elseif
		358	RegUsage set 2^bank
		359	endif
		360
		361	ar0 set bank*8 ; Set Symbols
		362	ar1 set ar0+1
		363	ar2 set ar0+2
		364	ar3 set ar0+3
		365	ar4 set ar0+4
		366	ar5 set ar0+5
		367	ar6 set ar0+6
		368	ar7 set ar0+7
		369	endm
		370
		371	restore ; re-allow listing
		372
		373	endif ; stddef51inc

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(root)//tools/asl/asl-current/include/stddef51.inc – Rev 1186