WebSVN – pentevo – Blame – //tools/asl/asl-current/include/stddef75.inc

Rev	Author	Line No.	Line
1186	savelij	1	ifndef stddef75inc ; avoid multiple inclusion
		2	stddef75inc equ 1
		3
		4	save
		5	listing off ; no listing over this file
		6
		7	;****************************************************************************
		8	;* *
		9	;* AS 1.42 - File STDDEF75.INC *
		10	;* *
		11	;* Contains SFR Definitions for the 75K0 Family *
		12	;* *
		13	;****************************************************************************
		14
		15	;----------------------------------------------------------------------------
		16	; For Comfort
		17
		18	__message macro msg,{NoExpand}
		19	if MOMPASS=1
		20	message msg
		21	endif
		22	endm
		23
		24	__message "uPD75K0 Register Definitions, (C) 1994 Alfred Arnold"
		25
		26	;----------------------------------------------------------------------------
		27	; Die Prozessoren zu Gruppen zusammenfassen
		28
		29	switch MOMCPU
		30	case 480258
		31	__message "Including uPD75402 Registers"
		32	__family equ 400
		33
		34	case 479236,479238,479240
		35	__message "Including uPD750xx Registers"
		36	__family equ 000
		37
		38	case 479848
		39	__message "Including uPD75268 Registers"
		40	__family equ 260
		41
		42	case 480004,480006,480008,480018,480022
		43	__message "Including uPD753xx Registers"
		44	__family equ 300
		45
		46	case 480040
		47	__message "Including uPD75328 Registers"
		48	__family equ 320
		49
		50	case 479492,479494,479496,479506,479510
		51	__message "Including uPD751xx Registers"
		52	__family equ 100
		53
		54	case 479750,479752,479762,479766
		55	__message "Including uPD752xx Registers"
		56	__family equ 200
		57
		58	case 480530,480534
		59	__message "Including uPD755xx Registers"
		60	__family equ 500
		61
		62	elsecase
		63	fatal "error: no target from uPD75xxx family selected"
		64	endcase
		65
		66	;----------------------------------------------------------------------------
		67	; all Interrupt Register have same structure, so use a macro:
		68
		69	__defint macro NAME,base,{NoExpand}
		70	__tmpnam set "NAME"
		71	I{__tmpnam} sfr base
		72	IE{__tmpnam} bit base.1
		73	IRQ{__tmpnam} bit base.0
		74	endm
		75
		76	;----------------------------------------------------------------------------
		77	; gemeinsame Register:
		78
		79	SP sfr 0f80h ; [8W] Stack Pointer
		80	BTM sfr 0f85h ; [4W] Base Timer Mode
		81	BT sfr 0f86h ; [8R] Bas Timer Count Value
		82	IM0 sfr 0fb4h ; [4W] INT0 Mode Register
		83	__defint BT,0fb8h ; [4] Interrupt BT Enable/Status
		84	PORT0 sfr 0ff0h ; [4R] Data Register Port 0
		85	PORT1 sfr 0ff1h ; [4R] Data Register Port 1
		86	PORT2 sfr 0ff2h ; [4] Data Register Port 2
		87	PORT3 sfr 0ff3h ; [4] Data Register Port 3
		88	PORT5 sfr 0ff5h ; [4] Data Register Port 5
		89	PORT6 sfr 0ff6h ; [4] Data Register Port 6
		90
		91	RESET label 0000h ; Reset Vector
		92	VIBT label 0002h ; Interrupt Vector Address INTBT
		93	; partially also INT4
		94	VI0 label 0004h ; Interrupt Vector Address INT0
		95	; partially also INT1
		96
		97	;----------------------------------------------------------------------------
		98
		99	if __family=400
		100	IME bit 0fb2h.3 ; [8] Interrupt Disable (access via EI/DI)
		101	PCC sfr 0fb3h ; [4W] Steuerung Prozessortakt
		102	__defint CSI,0fbdh ; [4] Interrupt CSI Enable/Status
		103	__defint 0,0fbeh ; [4] Interrupt 0 Enable/Status
		104	__defint 2,0fbeh ; [4] Interrupt 2 Enable/Status
		105	CLOM sfr 0fd0h ; [4W] Clock Output Mode Register
		106	POGA sfr 0fdch ; [8W] Pull-Up Cotrol Port A
		107	CSIM sfr 0fe0h ; [8W] Serial Interface Operation Mode
		108	CSIE bit CSIM+1.3
		109	COI bit CSIM+1.2
		110	WUP bit CSIM+1.1
		111	SBIC sfr 0fe2h ; [1] SBI Control
		112	CMDD bit SBIC.3
		113	RELD bit SBIC.2
		114	CMDT bit SBIC.1
		115	RELT bit SBIC.0
		116	BSYE bit SBIC+1.3
		117	ACKD bit SBIC+1.2
		118	ACKE bit SBIC+1.1
		119	ACKT bit SBIC+1.0
		120	SIO sfr 0fe4h ; [8] SIO Data Register
		121	SVA sfr 0fe6h ; [8W] Node Address on Serial Bus
		122	PMGA sfr 0fe8h ; [8W] Port Operation Mode
		123	PMGB sfr 0fech ; [8W] " "
		124
		125	VICSI label 0008h ; INTCSI Interrupt Vector Address
		126
		127	RAMEnd sfr 64 ; RAM Size
		128	endif
		129
		130	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		131
		132	if __family=000
		133	WM sfr 0f98h ; [8] Watchdog Mode
		134	TM0 sfr 0fa0h ; [8] Timer 0 Mode
		135	TOE0 bit 0fa2h.3 ; [1W] Timer 0 Output Enable
		136	T0 sfr 0fa4h ; [8R] Timer 0 Count Value
		137	TMOD0 sfr 0fa6h ; [8W] Timer 0 Modulo Register
		138	PSW sfr 0fb0h ; [4] Processor Status Word
		139	IST0 bit PSW.2
		140	MBE bit PSW.1
		141	IME bit 0fb2h.3 ; [8] Interrupt Disable (access via EI/DI)
		142	PCC sfr 0fb3h ; [4W] Processor Clock Control
		143	IM1 sfr 0fb5h ; [4W] INT1 Mode Register
		144	IM2 sfr 0fb6h ; [4W] INT2 Mode Register
		145	SCC sfr 0fb7h ; [1W] System Clock Control
		146	IE4 bit IBT.3 ; Enable/Status Interrupt 4
		147	IRQ4 bit IBT.2
		148	__defint W,0fbah ; [4] W Interrupt Enable/Status
		149	__defint T0,0fbch ; [4] T0 Interrupt Enable/Status
		150	__defint CSI,0fbdh ; [4] CSI Interrupt Enable/Status
		151	__defint 0,0fbeh ; [4] Interrupt 0 Enable/Status Interrupt 0
		152	IE1 bit I0.3 ; Interrupt 1 Enable/Status Interrupt 1
		153	IRQ1 bit I0.2
		154	__defint 2,0fbfh ; [4] Interrupt 2 Enable/Status
		155	BSB0 sfr 0fc0h ; [4] Bit Sequential Buffers
		156	BSB1 sfr 0fc1h
		157	BSB2 sfr 0fc2h
		158	BSB3 sfr 0fc3h
		159	CLOM sfr 0fd0h ; [4W] Clock Output Mode Register
		160	POGA sfr 0fdch ; [8W] Port A Pull-Up Control
		161	POGB sfr 0fdeh ; [8W] Port B Pull-Up Control
		162	CSIM sfr 0fe0h ; [8W] Serial Interface Operation Mode
		163	CSIE bit CSIM+1.3
		164	COI bit CSIM+1.2
		165	WUP bit CSIM+1.1
		166	SBIC sfr 0fe2h ; [1] SBI Control
		167	CMDD bit SBIC.3
		168	RELD bit SBIC.2
		169	CMDT bit SBIC.1
		170	RELT bit SBIC.0
		171	BSYE bit SBIC+1.3
		172	ACKD bit SBIC+1.2
		173	ACKE bit SBIC+1.1
		174	ACKT bit SBIC+1.0
		175	SIO sfr 0fe4h ; [8] Data Register SIO
		176	SVA sfr 0fe6h ; [8W] Node Address on Serial Bus
		177	PMGA sfr 0fe8h ; [8W] Port Operation Mode
		178	PM33 bit PMGA.3
		179	PM32 bit PMGA.2
		180	PM31 bit PMGA.1
		181	PM30 bit PMGA.0
		182	PM63 bit PMGA+1.3
		183	PM62 bit PMGA+1.2
		184	PM61 bit PMGA+1.1
		185	PM60 bit PMGA+1.0
		186	PMGB sfr 0fech ; [8W] " "
		187	PM2 bit PMGB.2
		188	PM4 bit PMGB+1.0
		189	PM5 bit PMGB+1.1
		190	PM7 bit PMGB+1.3
		191	PMGC sfr 0feeh ; [8W] " "
		192	PM8 bit PMGC.0
		193	PORT4 sfr 0ff4h ; [4] Data Register Port 4
		194	KR0 sfr PORT6.0
		195	KR1 sfr PORT6.1
		196	KR2 sfr PORT6.2
		197	KR3 sfr PORT6.3
		198	PORT7 sfr 0ff7h ; [4] Data Register Port 7
		199	KR4 sfr PORT7.0
		200	KR5 sfr PORT7.1
		201	KR6 sfr PORT7.2
		202	KR7 sfr PORT7.3
		203	PORT8 sfr 0ff8h ; [4] Data Register Port 8
		204
		205	VI1 label 0006h ; INT1 Vector Address
		206	VICSI label 0008h ; INTCSI Vector Address
		207	VIT0 label 000ah ; INTT0 Vector Address
		208
		209	RAMEnd sfr 512 ; RAM Size
		210	endif
		211
		212	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		213
		214	if __family=260
		215	DSPM sfr 0f88h ; [4W] Display Mode
		216	DIMS sfr 0f89h ; [4W] Display Dimmer Setting
		217	DIGS sfr 0f8ah ; [4] Display Number of Digits Selection
		218	KSF bit DIGS.3
		219	WM sfr 0f98h ; [8] Watchdog Mode
		220	TM0 sfr 0fa0h ; [8] Timer 0 Mode
		221	T0 sfr 0fa4h ; [8R] Timer 0 Count Value
		222	TMOD0 sfr 0fa6h ; [8W] Timer 0 Modulo Register
		223	PSW sfr 0fb0h ; [4] Processor Status Word
		224	IST0 bit PSW.2
		225	MBE bit PSW.1
		226	IME bit 0fb2h.3 ; [8] Interrupt Disable (access via EI/DI)
		227	PCC sfr 0fb3h ; [4W] Processor Clock Control
		228	IM1 sfr 0fb5h ; [4W] INT1 Mode Register
		229	SCC sfr 0fb7h ; [1W] System Clock Control
		230	IE4 bit IBT.3 ; Interrupt 4 Enable/Status
		231	IRQ4 bit IBT.2
		232	__defint W,0fbah ; [4] W Interrupt Enable/Status
		233	IEKS bit 0fbbh.3 ; [1] Keyboard Interrupt Enable/Status
		234	IRQKS bit 0fbbh.2
		235	__defint T0,0fbch ; [4] T0 Interrupt Enable/Status
		236	__defint SIO,0fbdh ; [4] SIO Interrupt Enable/Status
		237	__defint 0,0fbeh ; [4] Interrupt 0 Enable/Status
		238	IE1 bit I0.3 ; Interrupt 1 Enable/Status
		239	IRQ1 bit I0.2
		240	__defint 2,0fbfh ; [4] Interrupt 2 Enable/Status
		241	SIOM sfr 0fe0h ; [8W] Serial Interface Operation Mode
		242	SIO sfr 0fe4h ; [8] SIO Data Register
		243	PMGA sfr 0fe8h ; [8W] Port Operation Mode
		244	PM33 bit PMGA.3
		245	PM32 bit PMGA.2
		246	PM31 bit PMGA.1
		247	PM30 bit PMGA.0
		248	PM63 bit PMGA+1.3
		249	PM62 bit PMGA+1.2
		250	PM61 bit PMGA+1.1
		251	PM60 bit PMGA+1.0
		252	PMGB sfr 0fech ; [8W] " "
		253	PM2 bit PMGB.2
		254	PM4 bit PMGB+1.0
		255	PM5 bit PMGB+1.1
		256	PORT4 sfr 0ff4h ; [4] Port 4 Data Register
		257	SSTART sfr 01c0h ; Start of Display Memory
		258	KS0 sfr 01fch ; [8] Keyboard Register
		259	KS1 sfr 01feh ; [4]
		260	PORTH sfr 01ffh ; [4] Port H Data Register
		261
		262	VI1 label 0006h ; INT1 Interrupt Vector Address
		263	VISIO label 0008h ; INTSIO Interrupt Vector Address
		264	VIT0 label 000ah ; INTT0 Interrupt Vector Address
		265	VIKS label 000eh ; INTKS Interrupt Vector Address
		266
		267	RAMEnd sfr 512 ; RAM Size
		268	endif
		269
		270	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		271
		272	if __family=300
		273	LCDM sfr 0f8ch ; [8W] LC-Display Mode
		274	LCDC sfr 0f8eh ; [4W] LC-Display Control
		275	WM sfr 0f98h ; [8] Watchdog Mode
		276	TM0 sfr 0fa0h ; [8] Timer 0 Mode
		277	TOE0 bit 0fa2h.3 ; [1W] Timer 0 Output Enable
		278	T0 sfr 0fa4h ; [8R] Timer 0 Count Value
		279	TMOD0 sfr 0fa6h ; [8W] Timer 0 Modulo Register
		280	PSW sfr 0fb0h ; [4] Processor Status Word
		281	IST0 bit PSW.2
		282	MBE bit PSW.1
		283	IME bit 0fb2h.3 ; [8] Interrupt Disable (access via EI/DI)
		284	PCC sfr 0fb3h ; [4W] Processor Clock Control
		285	IM1 sfr 0fb5h ; [4W] INT1 Mode Register
		286	IM2 sfr 0fb6h ; [4W] INT2 Mode Register
		287	SCC sfr 0fb7h ; [1W] System Clock Control
		288	IE4 bit IBT.3 ; Interrupt 4 Enable/Status
		289	IRQ4 bit IBT.2
		290	__defint W,0fbah ; [4] W Interrupt Enable/Status
		291	__defint T0,0fbch ; [4] T0 Interrupt Enable/Status
		292	__defint CSI,0fbdh ; [4] CSI Interrupt Enable/Status
		293	__defint 0,0fbeh ; [4] Interrupt 0 Enable/Status
		294	IE1 bit I0.3 ; Interrupt 1 Enable/Status
		295	IRQ1 bit I0.2
		296	__defint 2,0fbfh ; [4] Interrupt 2 Enable/Status
		297	BSB0 sfr 0fc0h ; [4] Bit Sequential Buffers
		298	BSB1 sfr 0fc1h
		299	BSB2 sfr 0fc2h
		300	BSB3 sfr 0fc3h
		301	CLOM sfr 0fd0h ; [4W] Clock Output Mode Register
		302	POGA sfr 0fdch ; [8W] Port A Pull-Up Control
		303	CSIM sfr 0fe0h ; [8W] Serial Interface Operation Mode
		304	CSIE bit CSIM+1.3
		305	COI bit CSIM+1.2
		306	WUP bit CSIM+1.1
		307	SBIC sfr 0fe2h ; [1] SBI Control
		308	CMDD bit SBIC.3
		309	RELD bit SBIC.2
		310	CMDT bit SBIC.1
		311	RELT bit SBIC.0
		312	BSYE bit SBIC+1.3
		313	ACKD bit SBIC+1.2
		314	ACKE bit SBIC+1.1
		315	ACKT bit SBIC+1.0
		316	SIO sfr 0fe4h ; [8] SIO Data Register
		317	SVA sfr 0fe6h ; [8W] Node Address on Serial Bus
		318	PMGA sfr 0fe8h ; [8W] Port Operation Mode
		319	PM33 bit PMGA.3
		320	PM32 bit PMGA.2
		321	PM31 bit PMGA.1
		322	PM30 bit PMGA.0
		323	PM63 bit PMGA+1.3
		324	PM62 bit PMGA+1.2
		325	PM61 bit PMGA+1.1
		326	PM60 bit PMGA+1.0
		327	PMGB sfr 0fech ; [8W] " "
		328	PM2 bit PMGB.2
		329	PM4 bit PMGB+1.0
		330	PM5 bit PMGB+1.1
		331	PM7 bit PMGB+1.3
		332	PORT4 sfr 0ff4h ; [4] Port 4 Data Register
		333	KR0 sfr PORT6.0
		334	KR1 sfr PORT6.1
		335	KR2 sfr PORT6.2
		336	KR3 sfr PORT6.3
		337	PORT7 sfr 0ff7h ; [4] Port 7 Data Register
		338	KR4 sfr PORT7.0
		339	KR5 sfr PORT7.1
		340	KR6 sfr PORT7.2
		341	KR7 sfr PORT7.3
		342
		343	VI1 label 0006h ; INT1 Interrupt Vector Address
		344	VICSI label 0008h ; INTCSI Interrupt Vector Address
		345	VIT0 label 000ah ; INTT0 Interrupt Vector Address
		346
		347	RAMEnd sfr 512 ; RAM Size
		348	endif
		349
		350	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		351
		352	if __family=320
		353	LCDM sfr 0f8ch ; [8W] LC-Display Mode
		354	LCDC sfr 0f8eh ; [4W] LC-Display Control
		355	WM sfr 0f98h ; [8] Watchdog Mode
		356	TM0 sfr 0fa0h ; [8] Timer 0 Mode
		357	TOE0 bit 0fa2h.3 ; [1W] Timer 0 Output Enable
		358	T0 sfr 0fa4h ; [8R] Timer 0 Count Value
		359	TMOD0 sfr 0fa6h ; [8W] Timer 0 Modulo Register
		360	PSW sfr 0fb0h ; [4] Processor Status Word
		361	IST0 bit PSW.2
		362	MBE bit PSW.1
		363	IME bit 0fb2h.3 ; [8] Interrupt Disable (access via EI/DI)
		364	PCC sfr 0fb3h ; [4W] Processor Clock Control
		365	IM1 sfr 0fb5h ; [4W] INT1 Mode Register
		366	IM2 sfr 0fb6h ; [4W] INT2 Mode Register
		367	SCC sfr 0fb7h ; [1W] System Clock Control
		368	IE4 bit IBT.3 ; Interrupt 4 Enable/Status
		369	IRQ4 bit IBT.2
		370	__defint W,0fbah ; [4] W Interrupt Enable/Status
		371	__defint T0,0fbch ; [4] T0 Interrupt Enable/Status
		372	__defint CSI,0fbdh ; [4] CSI Interrupt Enable/Status
		373	__defint 0,0fbeh ; [4] Interrupt 0 Enable/Status
		374	IE1 bit I0.3 ; Interrupt 1 Enable/Status
		375	IRQ1 bit I0.2
		376	__defint 2,0fbfh ; [4] Interrupt 2 Enable/Status
		377	BSB0 sfr 0fc0h ; [4] Bit Sequential Buffers
		378	BSB1 sfr 0fc1h
		379	BSB2 sfr 0fc2h
		380	BSB3 sfr 0fc3h
		381	CLOM sfr 0fd0h ; [4W] Clock Output Mode Register
		382	ADM sfr 0fd8h ; [1] A/D Converter Control
		383	SOC sfr ADM.3
		384	EOC sfr ADM.2
		385	SA sfr 0fdah
		386	POGA sfr 0fdch ; [8W] Port A Pull-Up Control
		387	POBG sfr 0fdeh ; [8W] Port B Pull-Up Control
		388	CSIM sfr 0fe0h ; [8W] Serial Interface Operation Mode
		389	CSIE bit CSIM+1.3
		390	COI bit CSIM+1.2
		391	WUP bit CSIM+1.1
		392	SBIC sfr 0fe2h ; [1] SBI Control
		393	CMDD bit SBIC.3
		394	RELD bit SBIC.2
		395	CMDT bit SBIC.1
		396	RELT bit SBIC.0
		397	BSYE bit SBIC+1.3
		398	ACKD bit SBIC+1.2
		399	ACKE bit SBIC+1.1
		400	ACKT bit SBIC+1.0
		401	SIO sfr 0fe4h ; [8] SIO Data Register
		402	SVA sfr 0fe6h ; [8W] Node Address on Serial Bus
		403	PMGA sfr 0fe8h ; [8W] Port Operation Mode
		404	PM33 bit PMGA.3
		405	PM32 bit PMGA.2
		406	PM31 bit PMGA.1
		407	PM30 bit PMGA.0
		408	PM63 bit PMGA+1.3
		409	PM62 bit PMGA+1.2
		410	PM61 bit PMGA+1.1
		411	PM60 bit PMGA+1.0
		412	PMGB sfr 0fech ; [8W] " "
		413	PM2 bit PMGB.2
		414	PM4 bit PMGB+1.0
		415	PM5 bit PMGB+1.1
		416	PM7 bit PMGB+1.3
		417	PMGC sfr 0feeh ; [8W] " "
		418	PORT4 sfr 0ff4h ; [4] Port 4 Data Register
		419	KR0 sfr PORT6.0
		420	KR1 sfr PORT6.1
		421	KR2 sfr PORT6.2
		422	KR3 sfr PORT6.3
		423	PORT7 sfr 0ff7h ; [4] Port 7 Data Register
		424	KR4 sfr PORT7.0
		425	KR5 sfr PORT7.1
		426	KR6 sfr PORT7.2
		427	KR7 sfr PORT7.3
		428	PORT8 sfr 0ff8h ; [4] Port 8 Data Register
		429
		430	VI1 label 0006h ; INT1 Interrupt Vector Address
		431	VICSI label 0008h ; INTCSI Interrupt Vector Address
		432	VIT0 label 000ah ; INTT0 Interrupt Vector Address
		433
		434	RAMEnd sfr 512 ; RAM Size
		435	endif
		436
		437	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		438
		439	if __family=100
		440	TM0 sfr 0fa0h ; [8] Timer 0 Mode
		441	TOE0 bit 0fa2h.3 ; [1W] Timer 0 Output Enable
		442	TO0 bit 0fa2h.2 ; [1W] Timer 0 Output
		443	TOF0 bit 0fa2h.1 ; [1W] Timer 0 Output Flip Flop
		444	TI0 bit 0fa2h.0 ; [1W] Timer 0 Input
		445	T0 sfr 0fa4h ; [8R] Timer 0 Count Value
		446	TMOD0 sfr 0fa6h ; [8W] Timer 0 Modulo Register
		447	TM1 sfr 0fa8h ; [8] Timer 1 Mode
		448	TOE1 bit 0faah.3 ; [1W] Enable Timer 1 Output
		449	TO1 bit 0faah.2 ; [1W] Timer 1 Output
		450	TOF1 bit 0faah.1 ; [1W] Timer 1 Output Flip Flop
		451	TI1 bit 0faah.0 ; [1W] Timer 1 Input
		452	T1 sfr 0fach ; [8R] Timer 1 Counter Value
		453	TMOD1 sfr 0faeh ; [8W] Timer 1 Modulo Register
		454	PSW sfr 0fb0h ; [4] Processor Status Word
		455	IST1 bit PSW.3
		456	IST0 bit PSW.2
		457	MBE bit PSW.1
		458	RBE bit PSW.0
		459	IPS sfr 0fb2h ; [4W] Interrupt Priorities
		460	PCC sfr 0fb3h ; [4W] Processor Clock Control
		461	IM1 sfr 0fb5h ; [4W] INT1 Mode Register
		462	IE4 bit IBT.3 ; Interrupt 4 Enable/Status
		463	IRQ4 bit IBT.2
		464	__defint T0,0fbch ; [4] T0 Interrupt Enable/Status
		465	IET1 bit IT0.3
		466	IRQT1 bit IT0.2
		467	__defint SIO,0fbdh ; [4] SIO Interrupt Enable/Status
		468	__defint 0,0fbeh ; [4] Interrupt 0 Enable/Status
		469	IE1 bit I0.3 ; Interrupt 1 Enable/Status
		470	IRQ1 bit I0.2
		471	__defint 2,0fbfh ; [4] Interrupt 2 Enable/Status
		472	IE3 bit I2.3 ; Interrupt 3 Enable/Status
		473	IRQ3 bit I2.2
		474	BSB0 sfr 0fc0h ; [4] Bit Sequential Buffers
		475	BSB1 sfr 0fc1h
		476	BSB2 sfr 0fc2h
		477	BSB3 sfr 0fc3h
		478	CLOM sfr 0fd0h ; [4W] Clock Output Mode Register
		479	PONF bit 0fd1h.0 ; [1] Power-on-Flag
		480	PTHM sfr 0fd6h ; [8] Threshold Setting
		481	SIOM sfr 0fe0h ; [8W] Serial Interface Operation Mode
		482	SIO sfr 0fe4h ; [8] SIO Data Register
		483	PMGA sfr 0fe8h ; [8W] Port Operation Mode
		484	PM33 bit PMGA.3
		485	PM32 bit PMGA.2
		486	PM31 bit PMGA.1
		487	PM30 bit PMGA.0
		488	PM63 bit PMGA+1.3
		489	PM62 bit PMGA+1.2
		490	PM61 bit PMGA+1.1
		491	PM60 bit PMGA+1.0
		492	PMGB sfr 0fech ; [8W] " "
		493	PM2 bit PMGB.2
		494	PM4 bit PMGB+1.0
		495	PM5 bit PMGB+1.1
		496	PM7 bit PMGB+1.3
		497	PMGC sfr 0feeh ; [8W] " "
		498	PM8 bit PMGC.0
		499	PM9 bit PMGC.1
		500	PM12 bit PMGC+1.0
		501	PM13 bit PMGC+1.1
		502	PM14 bit PMGC+1.2
		503	PORT4 sfr 0ff4h ; [4] Port 4 Data Register
		504	PORT7 sfr 0ff7h ; [4] Port 7 Data Register
		505	PORT8 sfr 0ff8h ; [4] Port 8 Data Register
		506	PORT9 sfr 0ff9h ; [4] Port 9 Data Register
		507	PORT12 sfr 0ffch ; [4] Port 12 Data Register
		508	PORT13 sfr 0ffdh ; [4] Port 13 Data Register
		509	PORT14 sfr 0ffeh ; [4] Port 14 Data Register
		510
		511	VISIO label 0006h ; INTSIO Interrupt Vector Address
		512	VIT0 label 0008h ; INTT0 Interrupt Vector Address
		513	VIT1 label 000ah ; INTT1 Interrupt Vector Address
		514
		515	if MOMCPU<75108h ; RAM Size
		516	RAMEnd sfr 320
		517	elseif
		518	RAMEnd sfr 512
		519	endif
		520	endif
		521
		522	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		523
		524	if __family=200
		525	DSPM sfr 0f88h ; [4W] Display Mode
		526	DIMS sfr 0f89h ; [4W] Display Dimmer Setting
		527	DIGS sfr 0f8ah ; [4] Display Number of Digits Selection
		528	KSF bit DIGS.3
		529	TPGM sfr 0f90h ; [8W] Pulse Generator Mode
		530	MODL sfr 0f94h ; [8] Pulsgenerator Modulo Value
		531	MODH sfr 0f96h ; [8]
		532	WM sfr 0f98h ; [8] Watchdog Mode
		533	TM0 sfr 0fa0h ; [8] Timer 0 Mode
		534	T0 sfr 0fa4h ; [8R] Timer 0 Count Value
		535	TMOD0 sfr 0fa6h ; [8W] Timer 0 Modulo Register
		536	PSW sfr 0fb0h ; [4] Processor Status Word
		537	IST1 bit PSW.3
		538	IST0 bit PSW.2
		539	MBE bit PSW.1
		540	RBE bit PSW.0
		541	IPS sfr 0fb2h ; [4W] Interrupt Priorities
		542	PCC sfr 0fb3h ; [4W] Processor Clock Control
		543	IM1 sfr 0fb5h ; [4W] INT1 Mode Register
		544	SCC sfr 0fb7h ; [1W] System Clock Control
		545	IE4 bit IBT.3 ; Interrupt 4 Enable/Status
		546	IRQ4 bit IBT.2
		547	__defint W,0fbah ; [4] W Interrupt Enable/Status
		548	__defint TPG,0fbbh ; [4] TPG Interrupt Enable/Status
		549	IEKS bit ITPG.3 ; KS Interrupt Enable/Status
		550	IRQKS bit ITPG.2
		551	__defint T0,0fbch ; [4] T0 Interrupt Enable/Status
		552	__defint SIO,0fbdh ; [4] SIO Interrupt Enable/Status
		553	__defint 0,0fbeh ; [4] Interrupt 0 Enable/Status
		554	IE1 bit I0.3 ; Interrupt 1 Enable/Status
		555	IRQ1 bit I0.2
		556	__defint 2,0fbfh ; [4] Interrupt 2 Enable/Status
		557	PONF bit 0fd1h.0 ; [1] Power-on Flag
		558	SIOM sfr 0fe0h ; [8W] Serial Interface Operation Mode
		559	SIO sfr 0fe4h ; [8] SIO Data Register
		560	PMGA sfr 0fe8h ; [8W] Port Operation Mode
		561	PM33 bit PMGA.3
		562	PM32 bit PMGA.2
		563	PM31 bit PMGA.1
		564	PM30 bit PMGA.0
		565	PM63 bit PMGA+1.3
		566	PM62 bit PMGA+1.2
		567	PM61 bit PMGA+1.1
		568	PM60 bit PMGA+1.0
		569	PMGB sfr 0fech ; [8W] " "
		570	PM2 bit PMGB.2
		571	PM4 bit PMGB+1.0
		572	PM5 bit PMGB+1.1
		573	PORT4 sfr 0ff4h ; [4] Port 4 Data Register
		574	SSTART sfr 01c0h ; Start of Display Memory
		575	KS0 sfr 01fch ; [8] Keyboard Register
		576	KS1 sfr 01feh ; [4]
		577	PORTH sfr 01ffh ; [4] Data Register Port H
		578
		579	VI1 label 0006h ; INT1 Interrupt Vector Address
		580	VISIO label 0008h ; Interrupt Vector Address INTSIO
		581	VIT0 label 000ah ; INTT0 Interrupt Vector Address
		582	VITPG label 000ch ; Interrupt Vector Address INTTPG
		583	VIKS label 000eh ; Interrupt Vector Address INTKS
		584
		585	if MOMCPU<75108h ; RAM Size
		586	RAMEnd sfr 396
		587	elseif MOMCPU<75212h
		588	RAMEnd sfr 497
		589	elseif
		590	RAMEnd sfr 512
		591	endif
		592	endif
		593
		594	;- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
		595
		596	if __family=500
		597	TPGM sfr 0f90h ; [8W] Pulse Generator Mode
		598	MODL sfr 0f94h ; [8] Pulse Generator Modulo Value
		599	MODH sfr 0f96h ; [8]
		600	WM sfr 0f98h ; [8] Watchdog Mode
		601	TM0 sfr 0fa0h ; [8] Timer 0 Mode
		602	TOE0 bit 0fa2h.3 ; [1W] Timer 0 Output Enable
		603	T0 sfr 0fa4h ; [8R] Timer 0 Count Value
		604	TMOD0 sfr 0fa6h ; [8W] Timer 0 Modulo Register
		605	PSW sfr 0fb0h ; [4] Processor Status Word
		606	IST1 bit PSW.3
		607	IST0 bit PSW.2
		608	MBE bit PSW.1
		609	RBE bit PSW.0
		610	IPS sfr 0fb2h ; [4W] Interrupt Priorities
		611	PCC sfr 0fb3h ; [4W] Processor Clock Control
		612	IM1 sfr 0fb5h ; [4W] INT1 Mode Register
		613	IM2 sfr 0fb6h ; [4W] INT2 Mode Register
		614	SCC sfr 0fb7h ; [1W] System Clock Control
		615	IE4 bit IBT.3 ; Interrupt 4 Enable/Status
		616	IRQ4 bit IBT.2
		617	EOT bit 0fb9h.0
		618	__defint W,0fbah ; [4] W Interrupt Enable/Status
		619	__defint TPG,0fbbh ; [4] TPG Interrupt Enable/Status
		620	__defint T0,0fbch ; [4] T0 Interrupt Enable/Status
		621	__defint CSIO,0fbdh ; [4] CSIO InterruptEnable/Status
		622	__defint 0,0fbeh ; [4] Interrupt 0 Enable/Status
		623	IE1 bit I0.3 ; Interrupt 1 Enable/Status
		624	IRQ1 bit I0.2
		625	__defint 2,0fbfh ; [4] Interrupt 2 Enable/Status
		626	BSB0 sfr 0fc0h ; [4] Bit Sequential Buffers
		627	BSB1 sfr 0fc1h
		628	BSB2 sfr 0fc2h
		629	BSB3 sfr 0fc3h
		630	CSIM1 sfr 0fc8h ; [8W] Serial Interface Operation Mode
		631	CSIE1 bit CSIM1+1.3
		632	SIO1 sfr 0fcch ; [8] SIO Data Register
		633	CLOM sfr 0fd0h ; [4W] Clock Output Mode Register
		634	ADM sfr 0fd8h ; [1] A/D Converter Control
		635	SOC sfr ADM.3
		636	EOC sfr ADM.2
		637	SA sfr 0fdah
		638	POGA sfr 0fdch ; [8W] Port A Pull-Up Control
		639	CSIM0 sfr 0fe0h ; [8W] Serial Interface Operation Mode
		640	CSIE bit CSIM+1.3
		641	COI bit CSIM+1.2
		642	WUP bit CSIM+1.1
		643	SBIC sfr 0fe2h ; [1] SBI Control
		644	CMDD bit SBIC.3
		645	RELD bit SBIC.2
		646	CMDT bit SBIC.1
		647	RELT bit SBIC.0
		648	BSYE bit SBIC+1.3
		649	ACKD bit SBIC+1.2
		650	ACKE bit SBIC+1.1
		651	ACKT bit SBIC+1.0
		652	SIO0 sfr 0fe4h ; [8] SIO Data Register
		653	SVA sfr 0fe6h ; [8W] Node Address on Serial Bus
		654	PMGA sfr 0fe8h ; [8W] Port Operation Mode
		655	PM33 bit PMGA.3
		656	PM32 bit PMGA.2
		657	PM31 bit PMGA.1
		658	PM30 bit PMGA.0
		659	PM63 bit PMGA+1.3
		660	PM62 bit PMGA+1.2
		661	PM61 bit PMGA+1.1
		662	PM60 bit PMGA+1.0
		663	PMGB sfr 0fech ; [8W] " "
		664	PM2 bit PMGB.2
		665	PM4 bit PMGB+1.0
		666	PM5 bit PMGB+1.1
		667	PM7 bit PMGB+1.3
		668	PMGC sfr 0feeh ; [8W] " "
		669	PM8 bit PMGC.0
		670	PM9 bit PMGC.1
		671	PM12 bit PMGC+1.0
		672	PM13 bit PMGC+1.1
		673	PM14 bit PMGC+1.2
		674	PORT4 sfr 0ff4h ; [4] Port 4 Data Register
		675	PORT7 sfr 0ff7h ; [4] Port 7 Data Register
		676	PORT8 sfr 0ff8h ; [4R] Port 8 Data Register
		677	PORT9 sfr 0ff9h ; [4] Port 9 Data Register
		678	PORT10 sfr 0ffah ; [4] Port 10 Data Register
		679	PORT11 sfr 0ffbh ; [4] Port 11 Data Register
		680	PORT12 sfr 0ffch ; [4] Port 12 Data Register
		681	PORT13 sfr 0ffdh ; [4] Port 13 Data Register
		682	PORT14 sfr 0ffeh ; [4] Port 14 Data Register
		683	PORT15 sfr 0fffh ; [4R] Port 15 Data Register
		684
		685	VI1 label 0006h ; INT1 Interrupt Vector Address
		686	VICSIO label 0008h ; INTCSI Interrupt Vector AddressO
		687	VIT0 label 000ah ; INTT0 Interrupt Vector Address
		688	VITPG label 000ch ; Interrupt Vector Address INTTPG
		689
		690	RAMEnd sfr 512 ; RAM Size
		691	endif
		692
		693	restore ; re-enable listing
		694
		695	endif ; stddef75inc

Subversion Repositories pentevo

(root)//tools/asl/asl-current/include/stddef75.inc – Rev 1186