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Rev | Author | Line No. | Line |
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1186 | savelij | 1 | ifndef __stm8lclk01inc ; avoid multiple inclusion |
2 | __stm8lclk01inc equ 1 |
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3 | |||
4 | save |
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5 | listing off ; no listing over this file |
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6 | |||
7 | ;**************************************************************************** |
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8 | ;* * |
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9 | ;* AS 1.42 - File CLK01.INC * |
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10 | ;* * |
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11 | ;* contains SFR and Bit Definitions for STM8Lx01 CLK Controller * |
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12 | ;* * |
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13 | ;**************************************************************************** |
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14 | |||
15 | __defclk01 macro Base |
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16 | CLK_CKDIVR label Base+$00 ; Clock master divider register |
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17 | HSIDIV bfield CLK_CKDIVR,0,2 ; High speed internal clock prescaler |
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18 | CLK_PCKENR label Base+$03 ; Peripheral clock gating register |
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19 | PCKEN bfield CLK_PCKENR1,0,8 ; Peripheral clock enable |
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20 | CLK_CCOR label Base+$05 ; Configurable clock control register |
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21 | CCOSEL bfield CLK_CCOR,1,2 ; Configurable clock output selection |
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22 | CCOEN bit CLK_CCOR,0 ; Configurable clock output enable |
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23 | endm |
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24 | |||
25 | restore |
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26 | endif ; __stm8lclk01inc |