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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef __stm8lusart01inc ; avoid multiple inclusion |
| 2 | __stm8lusart01inc equ 1 |
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| 3 | |||
| 4 | save |
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| 5 | listing off ; no listing over this file |
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| 6 | |||
| 7 | ;**************************************************************************** |
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| 8 | ;* * |
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| 9 | ;* AS 1.42 - File USART01.INC * |
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| 10 | ;* * |
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| 11 | ;* contains SFR and Bit Definitions for STM8Lx01 U(S)ART * |
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| 12 | ;* * |
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| 13 | ;**************************************************************************** |
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| 14 | |||
| 15 | __defusart01 macro NAME,Base |
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| 16 | __NS set "\{NAME}_" |
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| 17 | {__NS}SR label Base+0 ; status register |
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| 18 | {__NS}TXE bit {__NS}SR,7 ; Transmit data register empty |
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| 19 | {__NS}TC bit {__NS}SR,6 ; Transmission complete |
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| 20 | {__NS}RXNE bit {__NS}SR,5 ; Read data register not empty |
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| 21 | {__NS}IDLE bit {__NS}SR,4 ; IDLE line detected |
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| 22 | {__NS}OR bit {__NS}SR,3 ; Overrun error/LIN Header Error |
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| 23 | {__NS}NF bit {__NS}SR,2 ; Noise flag |
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| 24 | {__NS}FE bit {__NS}SR,1 ; Framing error |
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| 25 | {__NS}PE bit {__NS}SR,0 ; Parity error |
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| 26 | {__NS}DR label Base+1 ; data register |
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| 27 | {__NS}BRR1 label Base+2 ; baud rate register 1 |
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| 28 | {__NS}BRR2 label Base+3 ; baud rate register 2 |
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| 29 | {__NS}CR1 label Base+4 ; control register 1 |
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| 30 | {__NS}R8 bit {__NS}CR1,7 ; Receive Data bit 8 |
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| 31 | {__NS}T8 bit {__NS}CR1,6 ; Transmit data bit 8 |
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| 32 | {__NS}USARTD bit {__NS}CR1,5 ; USART Disable |
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| 33 | {__NS}M bit {__NS}CR1,4 ; word length |
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| 34 | {__NS}WAKE bit {__NS}CR1,3 ; Wakeup method |
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| 35 | {__NS}PCEN bit {__NS}CR1,2 ; Parity control enable |
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| 36 | {__NS}PS bit {__NS}CR1,1 ; Parity selection |
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| 37 | {__NS}PIEN bit {__NS}CR1,0 ; Parity interrupt enable |
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| 38 | {__NS}CR2 label Base+5 ; control register 2 |
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| 39 | {__NS}TIEN bit {__NS}CR2,7 ; Transmitter interrupt enable |
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| 40 | {__NS}TCIEN bit {__NS}CR2,6 ; Transmission complete interrupt enable |
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| 41 | {__NS}RIEN bit {__NS}CR2,5 ; Receiver interrupt enable |
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| 42 | {__NS}ILIEN bit {__NS}CR2,4 ; IDLE Line interrupt enable |
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| 43 | {__NS}TEN bit {__NS}CR2,3 ; Transmitter enable |
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| 44 | {__NS}REN bit {__NS}CR2,2 ; Receiver enable |
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| 45 | {__NS}RWU bit {__NS}CR2,1 ; Receiver wakeup |
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| 46 | {__NS}SBK bit {__NS}CR2,0 ; Send break |
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| 47 | {__NS}CR3 label Base+6 ; control register 3 |
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| 48 | {__NS}STOP bfield {__NS}CR3,4,2 ; STOP bits |
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| 49 | {__NS}CLKEN bit {__NS}CR3,3 ; Clock enable |
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| 50 | {__NS}CPOL bit {__NS}CR3,2 ; Clock polarity |
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| 51 | {__NS}CPHA bit {__NS}CR3,1 ; Clock phase |
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| 52 | {__NS}LBCL bit {__NS}CR3,0 ; Last bit clock pulse |
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| 53 | {__NS}CR4 label Base+7 ; control register 4 |
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| 54 | {__NS}ADD bfield {__NS}CR4,0,4 ; Address of the UART node |
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| 55 | endm |
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| 56 | |||
| 57 | restore |
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| 58 | endif ; __stm8lusart01inc |