Rev 78 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 78 | lvd | 1 | clk=48mhz |
| 2 | cpu=3.5..14mhz (nowait) |
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| 3 | |||
| 4 | 'start access' signal -- max 4tc after combinatorial read/write from host |
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| 5 | |||
| 6 | ->D->D->D\ |
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| 7 | | | |
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| 8 | \--L->start access |
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| 9 | old------^ |
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| 10 | state |
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| 11 | |||
| 12 | access time for both sl811 and w5300 -- 5tc |
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| 13 | |||
| 84 | lvd | 14 | data setup for w5300: 42ns |
| 15 | data setup for sl811: 25..85ns |
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| 78 | lvd | 16 | |
| 84 | lvd | 17 | |
| 78 | lvd | 18 | READ: via latch, transparent during access time, then latches read data (if CPU cycle continues) |
| 19 | |||
| 20 | WRITE: via latch, data latched from CPU early, shown to the peripherals for the 5 tc |
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| 84 | lvd | 21 | -- ACHTUNG write /WR strobe is late!!!111 |
| 78 | lvd | 22 | |
| 84 | lvd | 23 | 5tc@48MHz = 1.5 tc @ 14MHz |
| 24 | 4tc@48MHz = 1.2 tc @ 14MHz |
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| 25 | so write will finish after 2.7 tc @ 14MHz after write pulse begin (memory write), |
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| 26 | such write WON'T coincide with the following memory read cycle, because it can't start earlier than |
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| 27 | 3tc @48MHz after read pulse |
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| 28 | |||
| 29 | |||
| 30 | |||
| 31 | TODO: |
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| 32 | + забуферировать rd/wr |
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| 33 | + забуферировать cs's |
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| 34 | + забуферировать sl811_a0 |
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| 35 | + забуферировать w5300_a |
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| 36 | + сделать новое управление шиной |
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| 37 |