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492 lvd 1 
// counter-based 'fapch', based on pentagon design, with filter and adopted to
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// 28mhz
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module fapch_counter
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(
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        input  wire fclk,
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        input  wire rdat_n,
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        output reg  vg_rclk,
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        output reg  vg_rawr
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);
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        reg [4:0] rdat_sync;
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        reg rdat_edge1, rdat_edge2;
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        wire rdat;
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        wire rwidth_ena;
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        reg [3:0] rwidth_cnt;
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        wire rclk_strobe;
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        reg [5:0] rclk_cnt;
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        // RCLK/RAWR restore
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        // currently simplest counter method, no PLL whatsoever now
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        //
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        // RCLK period must be 112 clocks (@28 MHz), or 56 clocks for each state
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        // RAWR on time is 4 clocks
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        // digital filter - removing glitches
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        always @(posedge fclk)
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                rdat_sync[4:0] <= { rdat_sync[3:0], (~rdat_n) };
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        always @(posedge fclk)
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        begin
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                if( rdat_sync[4:1]==4'b1111 ) // filter beginning of strobe
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                        rdat_edge1 <= 1'b1;
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                else if( rclk_strobe ) // filter any more strobes during same strobe half-perion
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                        rdat_edge1 <= 1'b0;
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                rdat_edge2 <= rdat_edge1;
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        end
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        assign rdat = rdat_edge1 & (~rdat_edge2);
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        always @(posedge fclk)
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                if( rwidth_ena )
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                begin
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                        if( rdat )
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                                rwidth_cnt <= 4'd0;
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                        else
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                                rwidth_cnt <= rwidth_cnt + 4'd1;
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                end
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        assign rwidth_ena = rdat | (~rwidth_cnt[2]); // [2] - 140ns, [3] - 280ns
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        always @(posedge fclk)
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                vg_rawr <= rwidth_cnt[2]; // RAWR has 2 clocks latency from rdat strobe
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        assign rclk_strobe = (rclk_cnt==6'd0);
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        always @(posedge fclk)
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        begin
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                if( rdat )
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                        rclk_cnt <= 6'd29; // (56/2)-1 plus halfwidth of RAWR
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                else if( rclk_strobe )
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                        rclk_cnt <= 6'd55; // period is 56 clocks
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                else
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                        rclk_cnt <= rclk_cnt - 6'd1;
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        end
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        always @(posedge fclk)
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                if( rclk_strobe )
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                        vg_rclk <= ~vg_rclk; // vg_rclk latency is 2 clocks plus a number loaded into rclk_cnt at rdat strobe
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endmodule
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