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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 158 | savelij | 1 | |
| 2 | ; LAST UPDATE: 28.05.2021 savelij |
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| 3 | |||
| 4 | IF 1 |
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| 5 | ; 筮 /६ |
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| 6 | DD_P0 EQU 15 ; 0 |
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| 7 | MM_P0 EQU 6 ; 0 |
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| 8 | YY_P0 EQU 13 ; 0 |
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| 9 | DD_P1 EQU 8 ; 1 |
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| 10 | MM_P1 EQU 8 ; 1 |
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| 11 | YY_P1 EQU 14 ; 1 |
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| 12 | DD_P7 EQU 19 ; 7 |
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| 13 | MM_P7 EQU 1 ; 7 |
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| 14 | YY_P7 EQU 11 ; 7 |
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| 15 | ELSE |
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| 16 | ; ⠢ ⥪饩 /६ |
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| 17 | ENDIF |
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| 18 | |||
| 19 | DATA_P0 EQU DD_P0+MM_P0<<5+YY_P0<<9+0X8000 ; 0 |
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| 20 | DATA_P1 EQU DD_P1+MM_P1<<5+YY_P1<<9+0X8000 ; 1 |
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| 21 | DATA_P7 EQU DD_P7+MM_P7<<5+YY_P7<<9+0X8000 ; 7 |
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| 22 | |||
| 23 | ; |
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| 24 | LDPAGE EQU 1 ; 稪 |
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| 25 | MAINPAGE EQU 1 ; ᭮ 訢 ROM |
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| 26 | FPGAPAGE EQU 1 ; ᭮ 訢 FPGA |
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| 27 | |||
| 28 | ; 64K |
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| 29 | LOADER_PAGE EQU 0 ; 稪 |
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| 30 | MAINROM_PAGE EQU 1 ; ᭮ 訢 ROM |
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| 31 | FPGA_PAGE EQU 7 ; ᭮ 訢 FPGA |