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Rev	Author	Line No.	Line
13	lvd	1	# Copyright (C) 1991-2007 Altera Corporation
		2	# Your use of Altera Corporation's design tools, logic functions
		3	# and other software and tools, and its AMPP partner logic
		4	# functions, and any output files from any of the foregoing
		5	# (including device programming or simulation files), and any
		6	# associated documentation or information are expressly subject
		7	# to the terms and conditions of the Altera Program License
		8	# Subscription Agreement, Altera MegaCore Function License
		9	# Agreement, or other applicable license agreement, including,
		10	# without limitation, that your use is for the sole purpose of
		11	# programming logic devices manufactured by Altera and sold by
		12	# Altera or its authorized distributors. Please refer to the
		13	# applicable agreement for further details.
		14
		15
		16	# The default values for assignments are stored in the file
		17	# top_assignment_defaults.qdf
		18	# If this file doesn't exist, and for assignments not listed, see file
		19	# assignment_defaults.qdf
		20
		21	# Altera recommends that you do not modify this file. This
		22	# file is updated automatically by the Quartus II software
		23	# and any changes you make may be lost or overwritten.
		24
		25
		26	set_global_assignment -name FAMILY MAX3000A
84	lvd	27	set_global_assignment -name DEVICE "EPM3128ATC100-10"
13	lvd	28	set_global_assignment -name TOP_LEVEL_ENTITY top
		29	set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
		30	set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:32:27 OCTOBER 13, 2012"
73	lvd	31	set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
13	lvd	32	set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
133	lvd	33	set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
13	lvd	34	set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
		35	set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
		36	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
		37	set_global_assignment -name VERILOG_FILE ../rtl/ports.v
		38	set_global_assignment -name VERILOG_FILE ../rtl/top.v
		39	set_global_assignment -name VERILOG_FILE ../rtl/wizmap.v
		40	set_global_assignment -name VERILOG_FILE ../rtl/zbus.v
		41	set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
62	lvd	42	set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
13	lvd	43	set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
		44	set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
		45	set_global_assignment -name SLOW_SLEW_RATE ON
22	lvd	46	set_global_assignment -name AUTO_TURBO_BIT OFF
40	lvd	47
		48	set_location_assignment PIN_52 -to za[15]
		49	set_location_assignment PIN_54 -to za[14]
		50	set_location_assignment PIN_56 -to za[13]
		51	set_location_assignment PIN_57 -to za[12]
		52	set_location_assignment PIN_58 -to zd[7]
		53	set_location_assignment PIN_60 -to zd[0]
		54	set_location_assignment PIN_61 -to zd[1]
		55	set_location_assignment PIN_63 -to zd[2]
		56	set_location_assignment PIN_64 -to zd[6]
		57	set_location_assignment PIN_67 -to za[0]
		58	set_location_assignment PIN_68 -to zd[5]
		59	set_location_assignment PIN_69 -to za[1]
		60	set_location_assignment PIN_71 -to zd[3]
		61	set_location_assignment PIN_75 -to za[2]
		62	set_location_assignment PIN_76 -to zd[4]
		63	set_location_assignment PIN_79 -to za[3]
		64	set_location_assignment PIN_81 -to ziorqge
		65	set_location_assignment PIN_83 -to zblkrom
		66	set_location_assignment PIN_84 -to zmreq_n
		67	set_location_assignment PIN_85 -to ziorq_n
84	lvd	68	set_location_assignment PIN_7 -to zrd_n
40	lvd	69	set_location_assignment PIN_88 -to zwr_n
26	lvd	70	set_location_assignment PIN_89 -to zrst_n
40	lvd	71	set_location_assignment PIN_90 -to za[7]
		72	set_location_assignment PIN_92 -to za[6]
		73	set_location_assignment PIN_93 -to za[5]
		74	set_location_assignment PIN_94 -to za[4]
		75	set_location_assignment PIN_96 -to zcsrom_n
		76	set_location_assignment PIN_97 -to za[8]
		77	set_location_assignment PIN_98 -to za[10]
		78	set_location_assignment PIN_99 -to za[9]
		79	set_location_assignment PIN_100 -to za[11]
		80
52	lvd	81	set_location_assignment PIN_20 -to bd[0]
		82	set_location_assignment PIN_6 -to w5300_addr[6]
		83	set_location_assignment PIN_16 -to bd[5]
		84	set_location_assignment PIN_23 -to w5300_addr[2]
		85	set_location_assignment PIN_29 -to bd[1]
		86	set_location_assignment PIN_41 -to sl811_cs_n
		87	set_location_assignment PIN_14 -to w5300_addr[7]
		88	set_location_assignment PIN_13 -to bd[6]
		89	set_location_assignment PIN_21 -to w5300_addr[3]
		90	set_location_assignment PIN_37 -to bd[2]
		91	set_location_assignment PIN_9 -to sl811_a0
		92	set_location_assignment PIN_25 -to w5300_addr[8]
		93	set_location_assignment PIN_8 -to sl811_rst_n
		94	set_location_assignment PIN_31 -to w5300_addr[4]
		95	set_location_assignment PIN_40 -to bd[3]
		96	set_location_assignment PIN_36 -to bwr_n
		97	set_location_assignment PIN_17 -to w5300_addr[9]
		98	set_location_assignment PIN_30 -to sl811_intrq
		99	set_location_assignment PIN_19 -to w5300_addr[5]
		100	set_location_assignment PIN_32 -to bd[4]
		101	set_location_assignment PIN_10 -to w5300_rst_n
		102	set_location_assignment PIN_35 -to w5300_addr[1]
70	dimkam	103	set_location_assignment PIN_12 -to sl811_ms_n
73	lvd	104	set_location_assignment PIN_87 -to fclk
84	lvd	105	set_location_assignment PIN_80 -to zint_n
		106	set_location_assignment PIN_28 -to usb_clk
73	lvd	107
		108
103	lvd	109	set_location_assignment PIN_42 -to usb_power
		110	set_location_assignment PIN_44 -to w5300_addr[0]
		111	set_location_assignment PIN_45 -to w5300_cs_n
		112	set_location_assignment PIN_46 -to w5300_int_n
		113	set_location_assignment PIN_47 -to bd[7]
		114	set_location_assignment PIN_48 -to brd_n
		115
		116
		117
84	lvd	118	set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
		119	set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR ../rtl/tb -section_id eda_simulation
		120	set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
		121	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
		122	set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS ON -section_id eda_simulation
		123	set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation
		124	set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED ON -section_id eda_simulation
73	lvd	125
84	lvd	126
		127	set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
		128
		129	set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id fclock
		130	set_instance_assignment -name CLOCK_SETTINGS fclock -to fclk
		131
121	lvd	132
		133	set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ON

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