WebSVN – zxusbnet – Blame – /branches/p2666fix_onlyIO/cpld/rtl/tb/ssz80.v

Rev	Author	Line No.	Line
15	lvd	1	// initially part of ZXiznet project (c) NedoPC 2012
		2	//
		3	// Simple Simulator of Z80
		4	// performs only some Z80 cycles as tasks, no /WAIT etc.
		5
185	lvd	6
		7	// reference Z80 cycles:
		8	//
		9	//
		10	// M1 opcode read:
		11	// \|-------------------------------\|
		12	// clk: _/```\___/```\___/```\___/```\___/`
		13	// mreq `````\___________/```````````````
		14	// rd `````\___________/```````````````
		15
		16	// mem read/write:
		17	// \|-----------------------\|
		18	// clk: _/```\___/```\___/```\___/`
		19	// mreq `````\_______________/```
		20	// rd `````\_______________/```
		21	// wr `````````````\_______/```
		22
		23	// IO read/write:
		24	// \|-------------------------------\|
		25	// clk: _/```\___/```\___/```\___/```\___/`
		26	// iorq `````````\___________________/```
		27	// rd/wr `````````\___________________/```
		28
		29
		30	`timescale 1ns/100ps
		31
15	lvd	32	module ssz80
		33	(
		34	input wire clk,
		35	input wire rst_n,
		36
		37	output reg mreq_n,
		38	output reg iorq_n,
		39	output reg wr_n,
		40	output reg rd_n,
		41
		42	output reg [15:0] a,
		43
		44	inout wire [ 7:0] d
		45	);
		46
		47
		48	reg [7:0] dout;
		49	reg oena;
		50
		51
		52	assign d = oena ? dout : 8'bZZZZ_ZZZZ;
		53
		54
		55
		56
		57	initial
		58	begin
33	lvd	59	a='d0;
		60
15	lvd	61	dout = 'd0;
		62	oena = 1'b0;
		63
		64	mreq_n = 1'bZ;
		65	iorq_n = 1'bZ;
		66	rd_n = 1'bZ;
		67	wr_n = 1'bZ;
		68	end
		69
		70
		71
		72
185	lvd	73	task fetch;
		74	input [15:0] addr;
		75	output [ 7:0] data;
		76
		77	begin
		78	@(posedge clk);
		79	mreq_n <= 1'b1;
		80	iorq_n <= 1'b1;
		81	rd_n <= 1'b1;
		82	wr_n <= 1'b1;
		83	oena <= 1'b0;
		84	a <= addr;
		85
		86	@(negedge clk);
		87
		88	mreq_n <= 1'b0;
		89	rd_n <= 1'b0;
		90
		91	@(posedge clk);
		92	@(posedge clk);
		93
		94	data = d;
		95	mreq_n <= 1'b1;
		96	rd_n <= 1'b1;
		97
		98	@(negedge clk);
		99	@(negedge clk);
		100	end
		101
		102	endtask
		103
		104
		105
		106
		107
15	lvd	108	task memrd;
		109
		110	input [15:0] addr;
		111	output [ 7:0] data;
		112
		113	begin
		114	@(posedge clk);
		115	mreq_n <= 1'b1;
		116	iorq_n <= 1'b1;
		117	rd_n <= 1'b1;
		118	wr_n <= 1'b1;
		119	oena <= 1'b0;
		120	a <= addr;
		121
		122	@(negedge clk);
		123
		124	mreq_n <= 1'b0;
		125	rd_n <= 1'b0;
		126
		127	@(negedge clk);
		128	@(negedge clk);
		129
		130	data = d;
		131	mreq_n <= 1'b1;
		132	rd_n <= 1'b1;
30	lvd	133
15	lvd	134	end
		135	endtask
		136
		137
		138	task memwr;
		139
		140	input [15:0] addr;
		141	input [ 7:0] data;
		142
		143	begin
		144	@(posedge clk);
		145
		146	mreq_n <= 1'b1;
		147	iorq_n <= 1'b1;
		148	rd_n <= 1'b1;
		149	wr_n <= 1'b1;
		150	a <= addr;
		151	dout <= data;
		152	oena <= 1'b1;
		153
		154	@(negedge clk);
		155
		156	mreq_n <= 1'b0;
84	lvd	157	@(negedge clk);
15	lvd	158	wr_n <= 1'b0;
		159	@(negedge clk);
		160
		161	mreq_n <= 1'b1;
		162	wr_n <= 1'b1;
185	lvd	163	wait(wr_n==1'b1); // delta-cycle delay!!!
30	lvd	164
185	lvd	165	//@(posedge clk);
35	lvd	166	oena <= 1'b0;
15	lvd	167	end
		168	endtask
		169
		170
185	lvd	171	task iord_;
15	lvd	172
		173	input [15:0] addr;
		174
		175	output [7:0] data;
		176
		177	begin
		178
		179	@(posedge clk);
		180
		181	mreq_n <= 1'b1;
		182	iorq_n <= 1'b1;
		183	rd_n <= 1'b1;
		184	wr_n <= 1'b1;
		185
		186	oena <= 1'b0;
		187	a <= addr;
		188
185	lvd	189	@(posedge clk);
15	lvd	190
		191	iorq_n <= 1'b0;
		192	rd_n <= 1'b0;
		193
		194	@(negedge clk);
		195	@(negedge clk);
185	lvd	196	@(negedge clk);
15	lvd	197
		198	data = d;
		199
		200	iorq_n <= 1'b1;
		201	rd_n <= 1'b1;
		202
		203	end
		204
		205	endtask
		206
		207
185	lvd	208	task iowr_;
15	lvd	209
		210	input [15:0] addr;
		211	input [ 7:0] data;
		212
		213	begin
		214
		215	@(posedge clk);
		216
		217	mreq_n <= 1'b1;
		218	iorq_n <= 1'b1;
		219	rd_n <= 1'b1;
		220	wr_n <= 1'b1;
		221
		222	a <= addr;
		223	dout <= data;
		224	oena <= 1'b1;
		225
185	lvd	226	@(posedge clk);
15	lvd	227
		228	iorq_n <= 1'b0;
		229	wr_n <= 1'b0;
		230
		231	@(negedge clk);
		232	@(negedge clk);
185	lvd	233	@(negedge clk);
15	lvd	234
		235	iorq_n <= 1'b1;
		236	wr_n <= 1'b1;
		237
185	lvd	238	wait(wr_n==1'b1); // delta-cycle delay!!!
		239	#(1.0);
		240	//@(posedge clk);
		241	//oena <= 1'b0;
		242	end
15	lvd	243
185	lvd	244	endtask
		245
		246
		247
		248
		249	task iowr;
		250
		251	input [15:0] addr;
		252	input [ 7:0] data;
		253
		254	begin
		255	random_mem();
		256	iowr_(addr,data);
		257	random_mem();
15	lvd	258	end
		259
		260	endtask
		261
185	lvd	262
		263	task iord;
15	lvd	264
185	lvd	265	input [15:0] addr;
		266	output [ 7:0] data;
15	lvd	267
185	lvd	268	begin
		269	random_mem();
		270	iord_(addr,data);
		271	random_mem();
		272	end
15	lvd	273
185	lvd	274	endtask
		275
		276
		277
		278
		279	task random_mem;
		280
		281	reg [15:0] addr;
		282	reg [ 7:0] data;
		283
		284	integer m;
		285
		286	begin
		287	addr = $random()>>16;
		288	data = $random()>>24;
		289
		290	case( $random()%3 )
		291	0: memrd(addr,data);
		292	1: memwr(addr,data);
		293	2: fetch(addr,data);
		294	endcase
		295	end
		296
		297	endtask
		298
		299
		300
15	lvd	301	endmodule
		302

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