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Rev | Author | Line No. | Line |
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9 | lvd | 1 | // ZXiznet project |
116 | lvd | 2 | // (c) NedoPC 2012-2018 |
9 | lvd | 3 | // |
13 | lvd | 4 | // zx-bus functions: ports mapping/access, ROM mapping |
9 | lvd | 5 | |
6 | module zbus |
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7 | ( |
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70 | dimkam | 8 | input wire fclk, |
84 | lvd | 9 | |
13 | lvd | 10 | input wire [15:0] za, |
11 | inout wire [ 7:0] zd, |
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12 | // |
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25 | lvd | 13 | inout wire [ 7:0] bd, |
14 | // |
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13 | lvd | 15 | input wire ziorq_n, |
16 | input wire zrd_n, |
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17 | input wire zwr_n, |
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18 | input wire zmreq_n, |
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19 | output wire ziorqge, |
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20 | output wire zblkrom, |
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21 | input wire zcsrom_n, |
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22 | input wire zrst_n, |
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23 | |||
24 | // |
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25 | output wire ports_wrena, |
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26 | output wire ports_wrstb_n, |
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27 | output wire [ 1:0] ports_addr, |
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28 | output wire [ 7:0] ports_wrdata, |
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29 | input wire [ 7:0] ports_rddata, |
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30 | |||
31 | // |
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32 | input wire [ 1:0] rommap_win, |
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33 | input wire rommap_ena, |
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34 | |||
35 | // |
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70 | dimkam | 36 | output reg sl811_cs_n, |
84 | lvd | 37 | output reg sl811_a0, |
13 | lvd | 38 | |
39 | // |
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70 | dimkam | 40 | output reg w5300_cs_n, |
84 | lvd | 41 | input wire w5300_ports, |
42 | input wire [ 9:0] async_w5300_addr, |
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43 | output reg [ 9:0] w5300_addr, |
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44 | |||
45 | |||
46 | |||
47 | // buffered rd/wr strobes to usb/ether chips |
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48 | output reg bwr_n, |
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49 | output reg brd_n |
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9 | lvd | 50 | ); |
13 | lvd | 51 | parameter BASE_ADDR = 8'hAB; |
9 | lvd | 52 | |
53 | |||
13 | lvd | 54 | |
84 | lvd | 55 | |
56 | reg [1:0] rst_n_resync; |
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57 | wire rst_n = rst_n_resync[1]; |
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58 | |||
59 | |||
13 | lvd | 60 | wire io_addr_ok; |
61 | |||
62 | wire mrd, mwr; |
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63 | |||
25 | lvd | 64 | wire ena_dbuf; |
65 | wire ena_din; |
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66 | wire ena_dout; |
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13 | lvd | 67 | |
68 | |||
72 | lvd | 69 | |
84 | lvd | 70 | // buffering chipselects |
71 | reg async_w5300_cs_n; |
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72 | reg async_sl811_cs_n; |
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73 | // |
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74 | reg [1:0] r_w5300_cs_n; |
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75 | reg [1:0] r_sl811_cs_n; |
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72 | lvd | 76 | |
84 | lvd | 77 | // buffering sl811 a0 |
78 | reg async_sl811_a0; |
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79 | // |
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80 | reg [1:0] r_sl811_a0; |
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72 | lvd | 81 | |
84 | lvd | 82 | // buffering w5300 address |
83 | reg [9:0] r_w5300_addr [0:1]; |
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72 | lvd | 84 | |
85 | |||
84 | lvd | 86 | // for filtering strobes |
87 | reg [2:0] wr_regs; |
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88 | reg [2:0] rd_regs; |
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89 | reg wr_state, |
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90 | rd_state; |
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91 | wire wr_start, |
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92 | rd_start; |
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72 | lvd | 93 | |
84 | lvd | 94 | // |
95 | reg [2:0] ctr_5; |
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96 | |||
97 | |||
98 | |||
99 | |||
100 | // common read and write latches latch |
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101 | reg [7:0] read_latch; |
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102 | reg [7:0] write_latch; |
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103 | |||
104 | |||
105 | |||
106 | |||
107 | // reset resync |
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108 | always @(posedge fclk, negedge zrst_n) |
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109 | if( !zrst_n ) |
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110 | rst_n_resync[1:0] <= 2'b00; |
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111 | else |
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112 | rst_n_resync[1:0] <= { rst_n_resync[0], 1'b1 }; |
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113 | |||
114 | |||
115 | |||
116 | |||
117 | // make filtered out vesions of read/write strobes |
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118 | always @(posedge fclk) |
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119 | begin |
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120 | wr_regs[2:0] <= { wr_regs[1:0], ~zwr_n }; |
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121 | rd_regs[2:0] <= { rd_regs[1:0], ~zrd_n }; |
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122 | end |
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123 | // |
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124 | |||
134 | lvd | 125 | assign wr_start = wr_regs[2:0]==3'b001 && !ctr_5; |
126 | assign rd_start = rd_regs[2:0]==3'b001 && !ctr_5; |
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84 | lvd | 127 | |
134 | lvd | 128 | |
84 | lvd | 129 | // buffered rd/wrs |
130 | always @(posedge fclk) |
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131 | begin |
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132 | if( wr_start ) |
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133 | bwr_n <= 1'b0; |
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134 | else if( !ctr_5 ) |
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135 | bwr_n <= 1'b1; |
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136 | // |
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137 | if( rd_start ) |
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138 | brd_n <= 1'b0; |
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139 | else if( !ctr_5 ) |
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140 | brd_n <= 1'b1; |
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141 | end |
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142 | // |
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143 | always @(posedge fclk, negedge rst_n) |
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144 | if( !rst_n ) |
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145 | begin |
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146 | ctr_5 <= 3'd0; |
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147 | end |
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148 | else if( wr_start || rd_start ) |
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149 | ctr_5 <= 3'd4; |
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134 | lvd | 150 | else if( ctr_5 ) |
84 | lvd | 151 | ctr_5 <= ctr_5 - 3'd1; |
152 | |||
153 | |||
154 | // buffered chipselects |
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155 | always @(posedge fclk) |
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156 | begin |
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157 | r_w5300_cs_n[1:0] <= { r_w5300_cs_n[0], async_w5300_cs_n }; |
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158 | r_sl811_cs_n[1:0] <= { r_sl811_cs_n[0], async_sl811_cs_n }; |
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159 | end |
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160 | // |
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161 | always @(posedge fclk) |
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162 | if( wr_start || rd_start ) |
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163 | begin |
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133 | lvd | 164 | w5300_cs_n <= async_w5300_cs_n; |
165 | sl811_cs_n <= async_sl811_cs_n; |
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84 | lvd | 166 | end |
167 | else if( !ctr_5 ) |
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168 | begin |
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169 | w5300_cs_n <= 1'b1; |
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170 | sl811_cs_n <= 1'b1; |
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171 | end |
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172 | |||
173 | |||
174 | // buffered sl811_a0 |
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175 | always @(posedge fclk) |
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176 | r_sl811_a0[1:0] <= { r_sl811_a0[0], async_sl811_a0 }; |
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177 | // |
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178 | always @(posedge fclk) |
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179 | if( wr_start || rd_start ) |
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133 | lvd | 180 | sl811_a0 <= async_sl811_a0; |
84 | lvd | 181 | |
182 | |||
183 | |||
184 | // buffered w5300_addr |
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185 | always @(posedge fclk) |
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186 | begin |
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187 | r_w5300_addr[0] <= async_w5300_addr; |
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188 | r_w5300_addr[1] <= r_w5300_addr[0]; |
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189 | end |
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190 | // |
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191 | always @(posedge fclk) |
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192 | if( wr_start || rd_start ) |
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133 | lvd | 193 | w5300_addr <= async_w5300_addr; |
84 | lvd | 194 | |
195 | |||
196 | |||
197 | |||
198 | |||
199 | |||
13 | lvd | 200 | // addr decode |
201 | assign io_addr_ok = (za[7:0]==BASE_ADDR); |
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202 | |||
203 | |||
204 | // IORQGE |
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205 | assign ziorqge = io_addr_ok ? 1'b1 : 1'bZ; |
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206 | |||
207 | |||
208 | |||
209 | // ports write |
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210 | assign ports_addr = za[9:8]; |
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211 | // |
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212 | assign ports_wrdata = zd; |
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213 | // |
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214 | assign ports_wrena = io_addr_ok && za[15]; |
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215 | assign ports_wrstb_n = ziorq_n | zwr_n; |
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216 | |||
217 | |||
59 | lvd | 218 | |
72 | lvd | 219 | always @* |
84 | lvd | 220 | async_sl811_cs_n = !( !w5300_ports && io_addr_ok && ( !za[15] || (za[15] && za[9:8]==2'b00) ) && !ziorq_n ); |
70 | dimkam | 221 | |
13 | lvd | 222 | // |
84 | lvd | 223 | always @* |
224 | async_sl811_a0 = ~za[15]; |
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13 | lvd | 225 | |
226 | |||
227 | // w5300 chip select |
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228 | assign mwr = !zmreq_n && !zwr_n && (za[15:14]==rommap_win) && rommap_ena; |
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229 | assign mrd = !zmreq_n && !zrd_n && !zcsrom_n && (za[15:14]==rommap_win) && rommap_ena; |
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230 | // |
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72 | lvd | 231 | always @* |
84 | lvd | 232 | async_w5300_cs_n = ~(mwr || mrd || ( w5300_ports && io_addr_ok && !za[15] && !ziorq_n ) ); |
13 | lvd | 233 | |
234 | // block ROM |
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235 | assign zblkrom = (rommap_ena && (za[15:14]==rommap_win)) ? 1'b1 : 1'bZ; |
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236 | |||
237 | |||
238 | |||
84 | lvd | 239 | assign ena_dbuf = (~async_sl811_cs_n) | (~async_w5300_cs_n); |
25 | lvd | 240 | assign ena_dout = ~zrd_n; |
241 | |||
84 | lvd | 242 | wire ports_rd = io_addr_ok && !ziorq_n && !zrd_n && za[15] && (za[9:8]!=2'b00); |
25 | lvd | 243 | |
84 | lvd | 244 | wire b_ena_dbuf = (~sl811_cs_n) | (~w5300_cs_n); |
245 | wire b_ena_din = ~bwr_n; |
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246 | |||
25 | lvd | 247 | // ports data read/buffering |
84 | lvd | 248 | /* assign zd = (io_addr_ok && !ziorq_n && !zrd_n && za[15] && (za[9:8]!=2'b00)) ? |
25 | lvd | 249 | ports_rddata : ( (ena_dbuf && ena_dout) ? bd : 8'bZZZZ_ZZZZ ); |
13 | lvd | 250 | |
251 | |||
25 | lvd | 252 | assign bd = (ena_dbuf && ena_din) ? zd : 8'bZZZZ_ZZZZ; |
84 | lvd | 253 | */ |
25 | lvd | 254 | |
84 | lvd | 255 | assign zd = ports_rd ? ports_rddata : ((ena_dbuf && ena_dout) ? read_latch : 8'hZZ); |
256 | |||
257 | assign bd = (b_ena_dbuf && b_ena_din) ? write_latch : 8'hZZ; |
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258 | |||
259 | |||
260 | |||
261 | |||
262 | // write latch |
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263 | always @* |
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264 | if( !zwr_n ) |
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265 | write_latch <= zd; |
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266 | |||
267 | // read latch |
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268 | always @* |
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269 | if( !brd_n ) |
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270 | read_latch <= bd; |
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271 | |||
272 | |||
273 | |||
274 | |||
9 | lvd | 275 | endmodule |
276 |