WebSVN – ngs – Blame – /cpld/cpld5_buf/GS_cpld.qsf

Rev	Author	Line No.	Line
17	lvd	1	# Copyright (C) 1991-2006 Altera Corporation
		2	# Your use of Altera Corporation's design tools, logic functions
		3	# and other software and tools, and its AMPP partner logic
		4	# functions, and any output files from any of the foregoing
		5	# (including device programming or simulation files), and any
		6	# associated documentation or information are expressly subject
		7	# to the terms and conditions of the Altera Program License
		8	# Subscription Agreement, Altera MegaCore Function License
		9	# Agreement, or other applicable license agreement, including,
		10	# without limitation, that your use is for the sole purpose of
		11	# programming logic devices manufactured by Altera and sold by
		12	# Altera or its authorized distributors. Please refer to the
		13	# applicable agreement for further details.
		14
		15
		16	# The default values for assignments are stored in the file
		17	# GS_cpld_assignment_defaults.qdf
		18	# If this file doesn't exist, and for assignments not listed, see file
		19	# assignment_defaults.qdf
		20
		21	# Altera recommends that you do not modify this file. This
		22	# file is updated automatically by the Quartus II software
		23	# and any changes you make may be lost or overwritten.
		24
		25
		26	set_global_assignment -name DEVICE "EPM3064ATC100-10"
		27	set_global_assignment -name FAMILY MAX3000A
		28	set_global_assignment -name TOP_LEVEL_ENTITY GS_cpld
		29	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
		30	set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:14:09 MARCH 18, 2010"
66	lvd	31	set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
17	lvd	32	set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
		33	set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
		34	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
22	lvd	35	set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE test1.cvwf
25	lvd	36	set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
		37	set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
60	lvd	38	set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
25	lvd	39	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
		40	set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
		41	set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
40	chrv	42	set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR sim/gate -section_id eda_simulation
		43	set_global_assignment -name MAX7000_DEVICE_IO_STANDARD "3.3-V LVTTL"
49	lvd	44
40	chrv	45	set_location_assignment PIN_6 -to config_n
49	lvd	46	set_location_assignment PIN_8 -to romcs_n
40	chrv	47	set_location_assignment PIN_9 -to cs
49	lvd	48
		49	set_location_assignment PIN_10 -to warmres_n
40	chrv	50	set_location_assignment PIN_13 -to in_ramcs0_n
		51	set_location_assignment PIN_14 -to in_ramcs1_n
		52	set_location_assignment PIN_16 -to in_ramcs2_n
		53	set_location_assignment PIN_17 -to in_ramcs3_n
49	lvd	54	set_location_assignment PIN_19 -to mreq_n
		55
		56	set_location_assignment PIN_20 -to rd_n
		57	set_location_assignment PIN_21 -to wr_n
		58	set_location_assignment PIN_23 -to iorq_n
		59	set_location_assignment PIN_25 -to a15
		60	set_location_assignment PIN_29 -to a14
		61
		62	set_location_assignment PIN_30 -to a13
		63	set_location_assignment PIN_31 -to a12
		64	set_location_assignment PIN_32 -to a11
		65	set_location_assignment PIN_35 -to a10
		66	set_location_assignment PIN_36 -to a7
		67	set_location_assignment PIN_37 -to a6
		68
		69	set_location_assignment PIN_40 -to d[6]
		70	set_location_assignment PIN_41 -to d[7]
		71	set_location_assignment PIN_42 -to d[4]
		72	set_location_assignment PIN_44 -to d[5]
		73	set_location_assignment PIN_45 -to d[1]
		74	set_location_assignment PIN_46 -to d[3]
		75	set_location_assignment PIN_47 -to d[2]
		76	set_location_assignment PIN_48 -to d[0]
		77
		78	set_location_assignment PIN_52 -to rd[2]
		79	set_location_assignment PIN_54 -to rd[3]
		80	set_location_assignment PIN_56 -to mema14
		81	set_location_assignment PIN_57 -to ra13
		82	set_location_assignment PIN_58 -to ra12
		83
		84	set_location_assignment PIN_60 -to ra11
		85	set_location_assignment PIN_61 -to ra10
		86	set_location_assignment PIN_63 -to rd[1]
		87	set_location_assignment PIN_64 -to rd[0]
		88	set_location_assignment PIN_67 -to mema15
		89	set_location_assignment PIN_68 -to mema19
		90	set_location_assignment PIN_69 -to memwe_n
		91
		92	set_location_assignment PIN_71 -to out_ramcs1_n
		93	set_location_assignment PIN_75 -to memoe_n
		94	set_location_assignment PIN_76 -to ra7
		95	set_location_assignment PIN_79 -to ra6
		96
		97	set_location_assignment PIN_80 -to rd[4]
		98	set_location_assignment PIN_81 -to rd[5]
40	chrv	99	set_location_assignment PIN_83 -to out_ramcs0_n
49	lvd	100	set_location_assignment PIN_84 -to rd[7]
		101	set_location_assignment PIN_85 -to rd[6]
		102	set_location_assignment PIN_87 -to clkin
		103	set_location_assignment PIN_88 -to clk24in
		104	set_location_assignment PIN_89 -to coldres_n
		105
		106	set_location_assignment PIN_90 -to clk20in
		107	set_location_assignment PIN_92 -to clksel0
		108	set_location_assignment PIN_93 -to clksel1
		109	set_location_assignment PIN_96 -to clkout
		110	set_location_assignment PIN_98 -to conf_done
		111	set_location_assignment PIN_99 -to init_done
		112
		113	set_location_assignment PIN_100 -to status_n
		114
58	lvd	115
60	lvd	116	set_global_assignment -name SLOW_SLEW_RATE ON
		117	set_global_assignment -name BDF_FILE clocker.bdf
		118	set_global_assignment -name VERILOG_FILE GS_cpld.v
		119	set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
66	lvd	120	set_global_assignment -name SAVE_DISK_SPACE OFF
		121	set_global_assignment -name AUTO_TURBO_BIT OFF

Subversion Repositories ngs

(root)/cpld/cpld5_buf/GS_cpld.qsf – Rev 66