WebSVN – pentevo – Blame – /fpga/base_trdemu/trunk/sim_top/gate/flex10ke_atoms.v

Rev	Author	Line No.	Line
278	lvd	1	// Copyright (C) 1991-2006 Altera Corporation
		2	// Your use of Altera Corporation's design tools, logic functions
		3	// and other software and tools, and its AMPP partner logic
		4	// functions, and any output files from any of the foregoing
		5	// (including device programming or simulation files), and any
		6	// associated documentation or information are expressly subject
		7	// to the terms and conditions of the Altera Program License
		8	// Subscription Agreement, Altera MegaCore Function License
		9	// Agreement, or other applicable license agreement, including,
		10	// without limitation, that your use is for the sole purpose of
		11	// programming logic devices manufactured by Altera and sold by
		12	// Altera or its authorized distributors. Please refer to the
		13	// applicable agreement for further details.
		14
		15
		16	// Quartus II 6.1 Build 201 11/27/2006
		17
		18
		19	///////////////////////////////////////////////////////////////////////////////
		20	//
		21	// FLEX10KE LCELL ATOM
		22	//
		23	// Supports lut_mask, does not support equations.
		24	// Support normal, arithmetic, updown counter and iclrable counter mode.
		25	// parameter output_mode is informational only and has no simulation function.
		26	// No checking is done for validation of parameters passed from top level.
		27	// Input default values are implemented using tri1 and tri0 net.
		28	//
		29	///////////////////////////////////////////////////////////////////////////////
		30
		31	`timescale 1 ps/1 ps
		32	module flex10ke_asynch_lcell (dataa, datab, datac, datad,
		33	cin, cascin, qfbkin,
		34	combout, regin, cout, cascout) ;
		35
		36	parameter operation_mode = "normal" ;
		37	parameter output_mode = "reg_and_comb";
		38	parameter lut_mask = "ffff" ;
		39	parameter cin_used = "false";
		40
		41	input dataa, datab, datac, datad ;
		42	input cin, qfbkin;
		43	input cascin;
		44	output cout, cascout, regin, combout ;
		45
		46	reg icout, data, tmp_cascin;
		47	reg [15:0] bin_mask;
		48	reg [2:0] iop_mode;
		49
		50	wire idataa;
		51	wire idatab;
		52	wire idatac;
		53	wire idatad;
		54	wire icascin;
		55	wire icin;
		56
		57	buf (idataa, dataa);
		58	buf (idatab, datab);
		59	buf (idatac, datac);
		60	buf (idatad, datad);
		61	buf (icascin, cascin);
		62	buf (icin, cin);
		63
		64	specify
		65
		66
		67	(dataa => combout) = (0, 0) ;
		68	(datab => combout) = (0, 0) ;
		69	(datac => combout) = (0, 0) ;
		70	(datad => combout) = (0, 0) ;
		71	(cascin => combout) = (0, 0) ;
		72	(cin => combout) = (0, 0) ;
		73	(qfbkin => combout) = (0, 0) ;
		74
		75	(dataa => cout) = (0, 0);
		76	(datab => cout) = (0, 0);
		77	(datac => cout) = (0, 0);
		78	(datad => cout) = (0, 0);
		79	(cin => cout) = (0, 0) ;
		80	(qfbkin => cout) = (0, 0) ;
		81
		82	(cascin => cascout) = (0, 0) ;
		83	(cin => cascout) = (0, 0) ;
		84	(dataa => cascout) = (0, 0) ;
		85	(datab => cascout) = (0, 0) ;
		86	(datac => cascout) = (0, 0) ;
		87	(datad => cascout) = (0, 0) ;
		88	(qfbkin => cascout) = (0, 0) ;
		89
		90	(dataa => regin) = (0, 0) ;
		91	(datab => regin) = (0, 0) ;
		92	(datac => regin) = (0, 0) ;
		93	(datad => regin) = (0, 0) ;
		94	(cascin => regin) = (0, 0) ;
		95	(cin => regin) = (0, 0) ;
		96	(qfbkin => regin) = (0, 0) ;
		97
		98	endspecify
		99
		100	function [16:1] str_to_bin ;
		101	input [8*4:1] s;
		102	reg [8*4:1] reg_s;
		103	reg [4:1] digit [8:1];
		104	reg [8:1] tmp;
		105	integer m , ivalue ;
		106	begin
		107
		108	ivalue = 0;
		109	reg_s = s;
		110	for (m=1; m<=4; m= m+1 )
		111	begin
		112	tmp = reg_s[32:25];
		113	digit[m] = tmp & 8'b00001111;
		114	reg_s = reg_s << 8;
		115	if (tmp[7] == 'b1)
		116	digit[m] = digit[m] + 9;
		117	end
		118	str_to_bin = {digit[1], digit[2], digit[3], digit[4]};
		119	end
		120	endfunction
		121
		122	function lut4 ;
		123	input [15:0] mask ;
		124	input dataa, datab, datac, datad ;
		125	reg prev_lut4;
		126	reg dataa_new, datab_new, datac_new, datad_new;
		127	integer h, i, j, k;
		128	integer hn, in, jn, kn;
		129	integer exitloop;
		130	integer check_prev;
		131
		132	begin
		133	lut4 = mask[{datad, datac, datab, dataa}]; // Try direct index first
		134	if (lut4 === 1'bx)
		135	begin
		136	if ((datad === 1'bx) \|\| (datad === 1'bz))
		137	begin
		138	datad_new = 1'b0;
		139	hn = 2;
		140	end
		141	else
		142	begin
		143	datad_new = datad;
		144	hn = 1;
		145	end
		146	check_prev = 0;
		147	exitloop = 0;
		148	h = 1;
		149	while ((h <= hn) && (exitloop == 0))
		150	begin
		151	if ((datac === 1'bx) \|\| (datac === 1'bz))
		152	begin
		153	datac_new = 1'b0;
		154	in = 2;
		155	end
		156	else
		157	begin
		158	datac_new = datac;
		159	in = 1;
		160	end
		161	i = 1;
		162	while ((i <= in) && (exitloop ==0))
		163	begin
		164	if ((datab === 1'bx) \|\| (datab === 1'bz))
		165	begin
		166	datab_new = 1'b0;
		167	jn = 2;
		168	end
		169	else
		170	begin
		171	datab_new = datab;
		172	jn = 1;
		173	end
		174	j = 1;
		175	while ((j <= jn) && (exitloop ==0))
		176	begin
		177	if ((dataa === 1'bx) \|\| (dataa === 1'bz))
		178	begin
		179	dataa_new = 1'b0;
		180	kn = 2;
		181	end
		182	else
		183	begin
		184	dataa_new = dataa;
		185	kn = 1;
		186	end
		187	k = 1;
		188	while ((k <= kn) && (exitloop ==0))
		189	begin
		190	lut4 = mask[{datad_new, datac_new, datab_new, dataa_new}];
		191
		192	if ((check_prev == 1) && (prev_lut4 !==lut4))
		193	begin
		194	lut4 = 1'bx;
		195	exitloop = 1;
		196	end
		197	else
		198	begin
		199	check_prev = 1;
		200	prev_lut4 = lut4;
		201	end
		202	k = k + 1;
		203	dataa_new = 1'b1;
		204	end // loop a
		205	j = j + 1;
		206	datab_new = 1'b1;
		207	end // loop b
		208	i = i + 1;
		209	datac_new = 1'b1;
		210	end // loop c
		211	h = h + 1;
		212	datad_new = 1'b1;
		213	end // loop d
		214	end
		215
		216	end
		217	endfunction
		218
		219	initial
		220	begin
		221	tmp_cascin = 1;
		222	bin_mask = str_to_bin (lut_mask) ;
		223
		224	if (operation_mode == "normal" && cin_used == "true") iop_mode = 4; // normal+cin is chain end only
		225	else if (operation_mode == "normal") iop_mode = 0; // most common
		226	else if (operation_mode == "arithmetic") iop_mode = 1; // second most common
		227	else if (operation_mode == "up_dn_cntr") iop_mode = 2;
		228	else if (operation_mode == "clrb_cntr") iop_mode = 3;
		229	else
		230	begin
		231	$display ("Error: Invalid operation_mode specified\n");
		232	iop_mode = 5;
		233	end
		234	end
		235
		236	always @(idatad or idatac or idatab or idataa or icin or
		237	icascin or qfbkin)
		238	begin
		239	if (iop_mode == 0) // operation_mode == "normal" without cin
		240	begin
		241	if ((icascin == 1'b1) \|\| (icascin == 1'b0))
		242	tmp_cascin = icascin;
		243
		244	data = lut4(bin_mask, idataa, idatab, idatac, idatad) && tmp_cascin;
		245	end
		246
		247	else if (iop_mode == 1) // operation_mode == "arithmetic"
		248	begin
		249	if ((icascin == 1'b1) \|\| (icascin == 1'b0))
		250	tmp_cascin = icascin;
		251
		252	data = lut4 (bin_mask, idataa, idatab, icin, 'b1) && tmp_cascin ;
		253	icout = lut4 ( bin_mask, idataa, idatab, icin, 'b0) ;
		254	end
		255
		256	else if (iop_mode == 2) // operation_mode == "up_dn_cntr"
		257	begin
		258	if ((icascin == 1'b1) \|\| (icascin == 1'b0))
		259	tmp_cascin = icascin;
		260	icout = lut4(bin_mask, qfbkin, idatab, icin, 'b0);
		261	if (idatad == 'b0)
		262	data = idatac && tmp_cascin;
		263	else
		264	data = (lut4(bin_mask, idataa, qfbkin, icin, 'b1)) && tmp_cascin;
		265	end
		266
		267	else if (iop_mode == 3) // operation_mode == "clrb_cntr"
		268	begin
		269	icout = lut4(bin_mask, qfbkin, idatab, icin, 'b0);
		270	if (idatad == 'b0)
		271	data = idatac && idatab;
		272	else
		273	data = (lut4(bin_mask, idataa, qfbkin, icin, 'b1)) && idatab;
		274	end
		275	else if (iop_mode == 4) // operation_mode == "normal" with cin
		276	begin
		277	if ((icascin == 1'b1) \|\| (icascin == 1'b0))
		278	tmp_cascin = icascin;
		279
		280	data = lut4 (bin_mask, idataa, idatab, icin, idatad) && tmp_cascin;
		281	end
		282	end
		283
		284	and (cascout, data, 'b1) ;
		285	and (combout, data, 'b1) ;
		286	and (cout, icout, 'b1) ;
		287	and (regin, data, 'b1) ;
		288
		289	endmodule
		290
		291	`timescale 1 ps/1 ps
		292
		293	module flex10ke_lcell_register (clk, aclr, aload,
		294	datain, dataa, datab, datac, datad, devclrn, devpor, regout, qfbko) ;
		295
		296	parameter operation_mode = "normal";
		297	parameter packed_mode = "false" ;
		298	parameter clock_enable_mode = "false";
		299	parameter x_on_violation = "on";
		300
		301	input clk, datain, dataa, datab, datac, datad;
		302	input aclr, aload, devclrn, devpor ;
		303	output regout, qfbko ;
		304
		305	reg iregout, init, oldclk;
		306	reg [1:0] isync_mode;
		307	reg iclock_enable_mode;
		308	wire clk_in, idataa, idatac, idatad;
		309	wire reset;
		310
		311	reg datain_viol, dataa_viol, datab_viol, datac_viol, datad_viol;
		312	reg aload_viol;
		313	reg clk_per_viol;
		314	reg violation;
		315
		316	wire iclr;
		317	wire iaload;
		318	wire idatab;
		319
		320	buf (clk_in, clk);
		321	buf (iclr, aclr);
		322	buf (iaload, aload);
		323	buf (idataa, dataa);
		324	buf (idatab, datab);
		325	buf (idatac, datac);
		326	buf (idatad, datad);
		327
		328	assign reset = devpor && devclrn && (!iclr) && idataa;
		329
		330	specify
		331
		332	$period (posedge clk &&& reset, 0, clk_per_viol);
		333
		334	$setuphold (posedge clk &&& reset, datain, 0, 0, datain_viol) ;
		335	$setuphold (posedge clk &&& reset, dataa, 0, 0, dataa_viol) ;
		336	$setuphold (posedge clk &&& reset, datab, 0, 0, datab_viol) ;
		337	$setuphold (posedge clk &&& reset, datac, 0, 0, datac_viol) ;
		338	$setuphold (posedge clk &&& reset, datad, 0, 0, datad_viol) ;
		339	$setuphold (posedge clk &&& reset, aload, 0, 0, aload_viol) ;
		340
		341
		342	(posedge clk => (regout +: iregout)) = 0 ;
		343	(posedge aclr => (regout +: 1'b0)) = (0, 0) ;
		344
		345	(posedge clk => (qfbko +: iregout)) = 0 ;
		346	(posedge aclr => (qfbko +: 1'b0)) = (0, 0) ;
		347
		348	endspecify
		349
		350	initial
		351	begin
		352	violation = 1;
		353	init = 0;
		354	oldclk = 'b0;
		355
		356	if (operation_mode == "clrb_cntr") isync_mode = 0;
		357	else if (operation_mode == "up_dn_cntr") isync_mode = 1;
		358	else if (packed_mode == "true") isync_mode = 2;
		359	else if (packed_mode == "false") isync_mode = 3;
		360	else
		361	$display("Error: Invalid combination of parameters used. Packed mode may be used only when operation_mode is 'normal'.\n");
		362
		363	iclock_enable_mode = (clock_enable_mode == "true");
		364	end
		365
		366	always @ (datain_viol or dataa_viol or datab_viol or datac_viol or datad_viol or aload_viol or clk_per_viol)
		367	begin
		368	if (x_on_violation == "on")
		369	violation = 1;
		370	end
		371
		372	always @ (clk_in or iclr or devclrn or devpor or posedge violation or idatac or iaload)
		373	begin
		374	if (violation == 1'b1)
		375	begin
		376	violation = 0;
		377	iregout = 'bx;
		378	end
		379	else
		380	begin
		381	if (devclrn == 'b0)
		382	iregout = 'b0;
		383	else if (iclr == 'b1)
		384	iregout = 'b0 ;
		385	else if (iaload == 'b1)
		386	iregout = idatac;
		387	else if ((clk_in == 'b1)&&(oldclk == 'b0)&&((iclock_enable_mode == 1'b0) \|\| (idataa == 1'b1)))
		388	begin
		389	case (isync_mode)
		390	0: // operation_mode == "clrb_cntr"
		391	begin
		392	if (idatab == 'b0)
		393	begin
		394	iregout = 'b0;
		395	end
		396	else if (idatad == 'b0)
		397	begin
		398	iregout = idatac;
		399	end
		400	else
		401	begin
		402	iregout = datain;
		403	end
		404	end
		405	1: // operation_mode == "up_dn_cntr"
		406	begin
		407	if (idatad == 'b0)
		408	begin
		409	iregout = idatac;
		410	end
		411	else
		412	begin
		413	iregout = datain;
		414	end
		415	end
		416	2: iregout = idatad; // packed_mode == "true"
		417	3: iregout = datain; // packed_mode == "false"
		418	endcase
		419	end
		420	end
		421	if (init==0)
		422	begin
		423	iregout = 'b0;
		424	init = 1;
		425	end
		426	oldclk = clk_in;
		427	end
		428
		429	and (regout, iregout, 'b1) ;
		430	and (qfbko, iregout, 'b1) ;
		431
		432	endmodule
		433
		434	`timescale 1 ps/1 ps
		435
		436	module flex10ke_lcell (clk, dataa, datab, datac, datad, aclr,
		437	aload, cin, cascin, devclrn, devpor,
		438	combout, regout, cout, cascout) ;
		439
		440	parameter operation_mode = "normal" ;
		441	parameter output_mode = "reg_and_comb";
		442	parameter packed_mode = "false" ;
		443	parameter clock_enable_mode = "false";
		444	parameter lut_mask = "ffff" ;
		445	parameter cin_used = "false";
		446	parameter x_on_violation = "on";
		447
		448	input clk, dataa, datab, datac, datad ;
		449	input aclr, aload, cin, cascin, devclrn, devpor ;
		450	output cout, cascout, regout, combout ;
		451	wire dffin, qfbk;
		452
		453	flex10ke_asynch_lcell lecomb (dataa, datab, datac, datad, cin, cascin,
		454	qfbk, combout, dffin, cout, cascout);
		455
		456	defparam lecomb.operation_mode = operation_mode,
		457	lecomb.output_mode = output_mode,
		458	lecomb.cin_used = cin_used,
		459	lecomb.lut_mask = lut_mask;
		460
		461	flex10ke_lcell_register lereg (clk, aclr, aload, dffin, dataa, datab, datac, datad,
		462	devclrn, devpor, regout, qfbk);
		463
		464	defparam lereg.operation_mode = operation_mode,
		465	lereg.packed_mode = packed_mode,
		466	lereg.clock_enable_mode = clock_enable_mode,
		467	lereg.x_on_violation = x_on_violation;
		468
		469	endmodule
		470
		471	///////////////////////////////////////////////////////////////////////////////
		472	//
		473	// FLEX10KE IO Atom
		474	//
		475	`timescale 1 ps/1 ps
		476	module flex10ke_io (clk, datain, aclr, ena, oe, devclrn, devoe, devpor,
		477	padio, dataout) ;
		478
		479	parameter operation_mode = "input" ;
		480	parameter reg_source_mode = "none" ;
		481	parameter feedback_mode = "from_pin" ;
		482	parameter power_up = "low";
		483	parameter open_drain_output = "false";
		484
		485	inout padio ;
		486	input datain, clk, aclr, ena, oe, devpor, devoe, devclrn ;
		487	output dataout;
		488	wire reg_pre, reg_clr;
		489	tri1 ena;
		490	tri0 aclr;
		491
		492	wire dffeD, dffeQ;
		493
		494	specify
		495
		496	endspecify
		497
		498	assign reg_clr = (power_up == "low") ? devpor : 1'b1;
		499	assign reg_pre = (power_up == "high") ? devpor : 1'b1;
		500
		501	flex10ke_asynch_io inst1 (datain, oe, padio, dffeD, dffeQ, dataout);
		502	defparam
		503	inst1.operation_mode = operation_mode,
		504	inst1.reg_source_mode = reg_source_mode,
		505	inst1.feedback_mode = feedback_mode,
		506	inst1.open_drain_output = open_drain_output;
		507
		508	dffe_io io_reg (dffeQ, clk, ena, dffeD, devclrn && !aclr && reg_clr, reg_pre);
		509
		510	endmodule
		511
		512	//
		513	// ASYNCH_IO
		514	//
		515	module flex10ke_asynch_io(datain, oe, padio, dffeD, dffeQ, dataout);
		516
		517	parameter operation_mode = "input" ;
		518	parameter reg_source_mode = "none" ;
		519	parameter feedback_mode = "from_pin" ;
		520	parameter open_drain_output = "false";
		521
		522	input datain, oe;
		523	input dffeQ;
		524	output dffeD;
		525	output dataout;
		526	inout padio;
		527
		528	reg tmp_comb, tri_in, tri_in_new, temp;
		529	reg reg_indata, tmp_dataout, switch;
		530	reg [3:0] isource_mode;
		531	reg op_mode_output;
		532	reg op_mode_bidir;
		533	reg ifeedback_from_pin;
		534	reg ifeedback_from_reg;
		535	wire regout;
		536
		537	specify
		538
		539	(padio => dataout) = (0, 0);
		540	(posedge oe => (padio +: tri_in_new)) = 0;
		541	(negedge oe => (padio +: 1'bz)) = 0;
		542	(datain => padio) = (0, 0);
		543	(dffeQ => padio) = (0, 0);
		544	(dffeQ => dataout) = (0, 0);
		545
		546	endspecify
		547
		548	wire ipadio;
		549	wire idatain;
		550	wire ioe;
		551
		552	buf (ipadio, padio);
		553	buf (idatain, datain);
		554	buf (ioe, oe);
		555
		556	initial
		557	begin
		558	tri_in = 1'b0;
		559	tmp_comb = 'b0;
		560	reg_indata = 'b0;
		561
		562	if ((reg_source_mode == "none") && (feedback_mode == "none"))
		563	begin
		564	if ((operation_mode == "output") \|\|
		565	(operation_mode == "bidir"))
		566	isource_mode = 0; // tri_in = idatain;
		567	end
		568	else if ((reg_source_mode == "none") && (feedback_mode == "from_pin"))
		569	begin
		570	if (operation_mode == "input")
		571	isource_mode = 1; // tmp_comb = ipadio;
		572	else if (operation_mode == "bidir")
		573	begin
		574	isource_mode = 2; // tmp_comb = ipadio; tri_in = idatain;
		575	end
		576	else $display ("Error: Invalid operation_mode specified\n");
		577	end
		578	else if ((reg_source_mode == "data_in") && (feedback_mode == "from_reg"))
		579	begin
		580	if ((operation_mode == "output") \|\| (operation_mode == "bidir"))
		581	begin
		582	isource_mode = 3; // tri_in = idatain; reg_indata = idatain;
		583	end
		584	else $display ("Error: Invalid operation_mode specified\n");
		585	end
		586	else if ((reg_source_mode == "pin_only") &&
		587	(feedback_mode == "from_reg"))
		588	begin
		589	if (operation_mode == "input")
		590	isource_mode = 4; // reg_indata = ipadio;
		591	else if (operation_mode == "bidir")
		592	begin
		593	isource_mode = 5; // tri_in = idatain; reg_indata = ipadio;
		594	end
		595	else $display ("Error: Invalid operation_mode specified\n");
		596	end
		597	else if ((reg_source_mode == "data_in_to_pin") &&
		598	(feedback_mode == "from_pin"))
		599	begin
		600	if (operation_mode == "bidir")
		601	begin
		602	isource_mode = 6; // tri_in = dffeQ; reg_indata = idatain; tmp_comb = ipadio;
		603	end
		604	else $display ("Error: Invalid operation_mode specified\n");
		605	end
		606	else if ((reg_source_mode == "data_in_to_pin") &&
		607	(feedback_mode == "from_reg"))
		608	begin
		609	if ((operation_mode == "output") \|\|
		610	(operation_mode == "bidir"))
		611	begin
		612	isource_mode = 7; // reg_indata = idatain; tri_in = dffeQ;
		613	end
		614	else $display ("Error: Invalid operation_mode specified\n");
		615	end
		616	else if ((reg_source_mode == "data_in_to_pin") &&
		617	(feedback_mode == "none"))
		618	begin
		619	if ((operation_mode == "output") \|\|
		620	(operation_mode == "bidir"))
		621	begin
		622	isource_mode = 8; // tri_in = dffeQ; reg_indata = idatain;
		623	end
		624	else $display ("Error: Invalid operation_mode specified\n");
		625	end
		626	else if ((reg_source_mode == "pin_loop") &&
		627	(feedback_mode == "from_pin"))
		628	begin
		629	if (operation_mode == "bidir")
		630	begin
		631	isource_mode = 9; // tri_in = dffeQ; reg_indata = ipadio; tmp_comb = ipadio;
		632	end
		633	else $display ("Error: Invalid operation_mtmp_dataouttmp_dataoutode specified\n");
		634	end
		635	else if ((reg_source_mode == "pin_loop") &&
		636	(feedback_mode == "from_reg"))
		637	begin
		638	if (operation_mode == "bidir")
		639	begin
		640	isource_mode = 10; // reg_indata = ipadio; tri_in = dffeQ;
		641	end
		642	else $display ("Error: Invalid operation_mode specified\n");
		643	end
		644	else
		645	begin
		646	isource_mode = 11;
		647	$display ("Error: Invalid combination of paratmp_dataoutmeters used\n");
		648	end
		649
		650	op_mode_output = (operation_mode == "output");
		651	op_mode_bidir = (operation_mode == "bidir");
		652	ifeedback_from_pin = (feedback_mode == "from_pin");
		653	ifeedback_from_reg = (feedback_mode == "from_reg");
		654	end
		655
		656	always @(ipadio or idatain or ioe or dffeQ)
		657	begin
		658	case (isource_mode)
		659	0: tri_in = idatain;
		660	1: tmp_comb = ipadio;
		661	2: begin
		662	tmp_comb = ipadio;
		663	tri_in = idatain;
		664	end
		665	3: begin
		666	tri_in = idatain;
		667	reg_indata = idatain;
		668	end
		669	4: reg_indata = ipadio;
		670	5: begin
		671	tri_in = idatain;
		672	reg_indata = ipadio;
		673	end
		674	6: begin
		675	tri_in = dffeQ;
		676	reg_indata = idatain;
		677	tmp_comb = ipadio;
		678	end
		679	7: begin
		680	reg_indata = idatain;
		681	tri_in = dffeQ;
		682	end
		683	8: begin
		684	tri_in = dffeQ;
		685	reg_indata = idatain;
		686	end
		687	9: begin
		688	tri_in = dffeQ;
		689	reg_indata = ipadio;
		690	tmp_comb = ipadio;
		691	end
		692	10: begin
		693	reg_indata = ipadio;
		694	tri_in = dffeQ;
		695	end
		696	endcase
		697
		698	if (op_mode_output)
		699	begin
		700	if (ioe == 'b0)
		701	temp = 'bz;
		702	else
		703	temp = tri_in;
		704	if (open_drain_output == "false")
		705	tri_in_new = temp;
		706	else if (open_drain_output == "true")
		707	begin
		708	if ((reg_source_mode == "data_in_to_pin") && (feedback_mode != "from_pin"))
		709	begin
		710	if (temp == 'b0)
		711	tri_in_new = 'b0;
		712	else
		713	tri_in_new = 'bz;
		714	end
		715	else
		716	begin
		717	if (idatain == 'b1)
		718	tri_in_new = 'bz;
		719	else
		720	tri_in_new = 'b0;
		721	end
		722	end
		723	end
		724	else if (op_mode_bidir && (ioe == 'b1))
		725	begin
		726	if (open_drain_output == "false")
		727	tri_in_new = tri_in;
		728	else if (open_drain_output == "true")
		729	begin
		730	if (tri_in == 'b0)
		731	tri_in_new = 'b0;
		732	else
		733	tri_in_new = 'bz;
		734	end
		735	end
		736	else
		737	tri_in_new = 'bz;
		738
		739	if (ifeedback_from_pin)
		740	begin
		741	tmp_dataout = tmp_comb;
		742	switch = 'b0;
		743	end
		744	else if (ifeedback_from_reg)
		745	begin
		746	tmp_dataout = 'b0;
		747	if (reg_indata == 'bx)
		748	switch = 'b0;
		749	else
		750	switch = 'b1;
		751	end
		752	end
		753
		754	and (dffeD, reg_indata, 1'b1);
		755	and (regout, dffeQ, switch, 1'b1);
		756	or (dataout, regout, tmp_dataout, 1'b0);
		757	pmos (padio, tri_in_new, 'b0);
		758
		759	endmodule
		760
		761	//////////////////////////////////////////////////////////////////////////////
		762	//
		763	// Module Name : FLEX10KE_ASYNCH_MEM
		764	//
		765	// Description : Timing simulation model for the asynchronous RAM array
		766	//
		767	//////////////////////////////////////////////////////////////////////////////
		768
		769	`timescale 1 ps/1 ps
		770	module flex10ke_asynch_mem (datain,
		771	we,
		772	re,
		773	raddr,
		774	waddr,
		775	modesel,
		776	dataout);
		777
		778	// INPUT PORTS
		779	input datain;
		780	input we;
		781	input re;
		782	input [10:0] raddr;
		783	input [10:0] waddr;
		784	input [15:0] modesel;
		785
		786	// OUTPUT PORTS
		787	output dataout;
		788
		789	// GLOBAL PARAMETERS
		790	parameter logical_ram_depth = 2048;
		791	parameter infile = "none";
		792	parameter address_width = 11;
		793	parameter first_address = 0;
		794	parameter last_address = 2047;
		795	parameter mem1 = 512'b0;
		796	parameter mem2 = 512'b0;
		797	parameter mem3 = 512'b0;
		798	parameter mem4 = 512'b0;
		799	parameter bit_number = 0;
		800	parameter write_logic_clock = "none";
		801	parameter read_enable_clock = "none";
		802	parameter data_out_clock = "none";
		803	parameter operation_mode = "single_port";
		804
		805	// INTERNAL VARIABLES AND NETS
		806	reg tmp_dataout;
		807	reg [10:0] rword;
		808	reg [10:0] wword;
		809	reg [2047:0] mem;
		810	reg write_en;
		811	reg read_en;
		812	reg write_en_last_value;
		813	wire [10:0] waddr_in;
		814	wire [10:0] raddr_in;
		815	integer i;
		816
		817	wire we_in;
		818	wire re_in;
		819	wire datain_in;
		820
		821	// BUFFER INPUTS
		822	buf (we_in, we);
		823	buf (re_in, re);
		824	buf (datain_in, datain);
		825
		826	buf (waddr_in[0], waddr[0]);
		827	buf (waddr_in[1], waddr[1]);
		828	buf (waddr_in[2], waddr[2]);
		829	buf (waddr_in[3], waddr[3]);
		830	buf (waddr_in[4], waddr[4]);
		831	buf (waddr_in[5], waddr[5]);
		832	buf (waddr_in[6], waddr[6]);
		833	buf (waddr_in[7], waddr[7]);
		834	buf (waddr_in[8], waddr[8]);
		835	buf (waddr_in[9], waddr[9]);
		836	buf (waddr_in[10], waddr[10]);
		837
		838	buf (raddr_in[0], raddr[0]);
		839	buf (raddr_in[1], raddr[1]);
		840	buf (raddr_in[2], raddr[2]);
		841	buf (raddr_in[3], raddr[3]);
		842	buf (raddr_in[4], raddr[4]);
		843	buf (raddr_in[5], raddr[5]);
		844	buf (raddr_in[6], raddr[6]);
		845	buf (raddr_in[7], raddr[7]);
		846	buf (raddr_in[8], raddr[8]);
		847	buf (raddr_in[9], raddr[9]);
		848	buf (raddr_in[10], raddr[10]);
		849
		850	// TIMING PATHS
		851	specify
		852
		853	$setup (waddr[0], posedge we &&& (~modesel[2]), 0);
		854	$setup (waddr[1], posedge we &&& (~modesel[2]), 0);
		855	$setup (waddr[2], posedge we &&& (~modesel[2]), 0);
		856	$setup (waddr[3], posedge we &&& (~modesel[2]), 0);
		857	$setup (waddr[4], posedge we &&& (~modesel[2]), 0);
		858	$setup (waddr[5], posedge we &&& (~modesel[2]), 0);
		859	$setup (waddr[6], posedge we &&& (~modesel[2]), 0);
		860	$setup (waddr[7], posedge we &&& (~modesel[2]), 0);
		861	$setup (waddr[8], posedge we &&& (~modesel[2]), 0);
		862	$setup (waddr[9], posedge we &&& (~modesel[2]), 0);
		863	$setup (waddr[10], posedge we &&& (~modesel[2]), 0);
		864
		865	$setuphold (negedge re &&& (~modesel[4]), raddr[0], 0, 0);
		866	$setuphold (negedge re &&& (~modesel[4]), raddr[1], 0, 0);
		867	$setuphold (negedge re &&& (~modesel[4]), raddr[2], 0, 0);
		868	$setuphold (negedge re &&& (~modesel[4]), raddr[3], 0, 0);
		869	$setuphold (negedge re &&& (~modesel[4]), raddr[4], 0, 0);
		870	$setuphold (negedge re &&& (~modesel[4]), raddr[5], 0, 0);
		871	$setuphold (negedge re &&& (~modesel[4]), raddr[6], 0, 0);
		872	$setuphold (negedge re &&& (~modesel[4]), raddr[7], 0, 0);
		873	$setuphold (negedge re &&& (~modesel[4]), raddr[8], 0, 0);
		874	$setuphold (negedge re &&& (~modesel[4]), raddr[9], 0, 0);
		875	$setuphold (negedge re &&& (~modesel[4]), raddr[10], 0, 0);
		876
		877	$setuphold (negedge we &&& (~modesel[0]), datain, 0, 0);
		878
		879	$hold (negedge we &&& (~modesel[2]), waddr[0], 0);
		880	$hold (negedge we &&& (~modesel[2]), waddr[1], 0);
		881	$hold (negedge we &&& (~modesel[2]), waddr[2], 0);
		882	$hold (negedge we &&& (~modesel[2]), waddr[3], 0);
		883	$hold (negedge we &&& (~modesel[2]), waddr[4], 0);
		884	$hold (negedge we &&& (~modesel[2]), waddr[5], 0);
		885	$hold (negedge we &&& (~modesel[2]), waddr[6], 0);
		886	$hold (negedge we &&& (~modesel[2]), waddr[7], 0);
		887	$hold (negedge we &&& (~modesel[2]), waddr[8], 0);
		888	$hold (negedge we &&& (~modesel[2]), waddr[9], 0);
		889	$hold (negedge we &&& (~modesel[2]), waddr[10], 0);
		890
		891	$nochange (posedge we &&& (~modesel[2]), waddr, 0, 0);
		892
		893	$width (posedge we, 0);
		894	$width (posedge re, 0);
		895
		896	(raddr[0] => dataout) = (0, 0);
		897	(raddr[1] => dataout) = (0, 0);
		898	(raddr[2] => dataout) = (0, 0);
		899	(raddr[3] => dataout) = (0, 0);
		900	(raddr[4] => dataout) = (0, 0);
		901	(raddr[5] => dataout) = (0, 0);
		902	(raddr[6] => dataout) = (0, 0);
		903	(raddr[7] => dataout) = (0, 0);
		904	(raddr[8] => dataout) = (0, 0);
		905	(raddr[9] => dataout) = (0, 0);
		906	(raddr[10] => dataout) = (0, 0);
		907	(waddr[0] => dataout) = (0, 0);
		908	(waddr[1] => dataout) = (0, 0);
		909	(waddr[2] => dataout) = (0, 0);
		910	(waddr[3] => dataout) = (0, 0);
		911	(waddr[4] => dataout) = (0, 0);
		912	(waddr[5] => dataout) = (0, 0);
		913	(waddr[6] => dataout) = (0, 0);
		914	(waddr[7] => dataout) = (0, 0);
		915	(waddr[8] => dataout) = (0, 0);
		916	(waddr[9] => dataout) = (0, 0);
		917	(waddr[10] => dataout) = (0, 0);
		918	(re => dataout) = (0, 0);
		919	(we => dataout) = (0, 0);
		920	(datain => dataout) = (0, 0);
		921
		922	endspecify
		923
		924	initial
		925	begin
		926	mem = {mem4, mem3, mem2, mem1};
		927
		928	// if WE is not registered, initial RAM content is X
		929	// note that if WE is not registered, the MIF file cannot be used
		930	if ((operation_mode != "rom") && (write_logic_clock == "none"))
		931	begin
		932	for (i = 0; i <= 2047; i=i+1)
		933	mem[i] = 'bx;
		934	end
		935
		936	tmp_dataout = 'b0;
		937	if ((operation_mode == "rom") \|\| (operation_mode == "single_port"))
		938	begin
		939	// re is always active
		940	tmp_dataout = mem[0];
		941	end
		942	else begin
		943	// re is inactive
		944	tmp_dataout = 'b0;
		945	end
		946	if (read_enable_clock != "none")
		947	begin
		948	if ((operation_mode == "rom") \|\| (operation_mode == "single_port"))
		949	begin
		950	// re is always active
		951	tmp_dataout = mem[0];
		952	end
		953	else begin
		954	// eab cell output powers up to VCC
		955	tmp_dataout = 'b1;
		956	end
		957	end
		958	end
		959
		960	always @(we_in or re_in or raddr_in or waddr_in or datain_in)
		961	begin
		962	rword = raddr_in[10:0];
		963	wword = waddr_in[10:0];
		964
		965	read_en = re_in;
		966	write_en = we_in;
		967
		968	if (modesel[14:13] == 2'b10)
		969	begin
		970	if (read_en == 1)
		971	tmp_dataout = mem[rword];
		972	end
		973	else if (modesel[14:13] == 2'b00)
		974	begin
		975	if ((write_en == 0) && (write_en_last_value == 1))
		976	mem[wword] = datain_in;
		977	if (write_en == 0)
		978	tmp_dataout = mem[wword];
		979	else if (write_en == 1)
		980	tmp_dataout = datain_in;
		981	else tmp_dataout = 'bx;
		982	end
		983	else if (modesel[14:13] == 2'b01)
		984	begin
		985	if ((write_en == 0) && (write_en_last_value == 1))
		986	mem[wword] = datain_in;
		987	if ((read_en == 1) && (rword == wword) && (write_en == 1))
		988	tmp_dataout = datain_in;
		989	else if (read_en == 1)
		990	tmp_dataout = mem[rword];
		991	end
		992	write_en_last_value = write_en;
		993	end
		994
		995	and (dataout, tmp_dataout, 'b1);
		996
		997	endmodule // flex10ke_asynch_mem
		998
		999	//////////////////////////////////////////////////////////////////////////////
		1000	//
		1001	// Module Name : PRIM_DFFE
		1002	//
		1003	// Description : State table for UDP PRIM_DFFE
		1004	//
		1005	//////////////////////////////////////////////////////////////////////////////
		1006
		1007	primitive PRIM_DFFE (Q, ENA, D, CLK, CLRN, PRN, notifier);
		1008	input D;
		1009	input CLRN;
		1010	input PRN;
		1011	input CLK;
		1012	input ENA;
		1013	input notifier;
		1014	output Q; reg Q;
		1015
		1016	initial Q = 1'b0;
		1017
		1018	table
		1019
		1020	// ENA D CLK CLRN PRN notifier : Qt : Qt+1
		1021
		1022	(??) ? ? 1 1 ? : ? : -; // pessimism
		1023	x ? ? 1 1 ? : ? : -; // pessimism
		1024	1 1 (01) 1 1 ? : ? : 1; // clocked data
		1025	1 1 (01) 1 x ? : ? : 1; // pessimism
		1026
		1027	1 1 ? 1 x ? : 1 : 1; // pessimism
		1028
		1029	1 0 0 1 x ? : 1 : 1; // pessimism
		1030	1 0 x 1 (?x) ? : 1 : 1; // pessimism
		1031	1 0 1 1 (?x) ? : 1 : 1; // pessimism
		1032
		1033	1 x 0 1 x ? : 1 : 1; // pessimism
		1034	1 x x 1 (?x) ? : 1 : 1; // pessimism
		1035	1 x 1 1 (?x) ? : 1 : 1; // pessimism
		1036
		1037	1 0 (01) 1 1 ? : ? : 0; // clocked data
		1038
		1039	1 0 (01) x 1 ? : ? : 0; // pessimism
		1040
		1041	1 0 ? x 1 ? : 0 : 0; // pessimism
		1042
		1043
		1044	1 1 0 x 1 ? : 0 : 0; // pessimism
		1045	1 1 x (?x) 1 ? : 0 : 0; // pessimism
		1046	1 1 1 (?x) 1 ? : 0 : 0; // pessimism
		1047
		1048	1 x 0 x 1 ? : 0 : 0; // pessimism
		1049	1 x x (?x) 1 ? : 0 : 0; // pessimism
		1050	1 x 1 (?x) 1 ? : 0 : 0; // pessimism
		1051
		1052	1 1 (x1) 1 1 ? : 1 : 1; // reducing pessimism
		1053	1 0 (x1) 1 1 ? : 0 : 0;
		1054	1 1 (0x) 1 1 ? : 1 : 1;
		1055	1 0 (0x) 1 1 ? : 0 : 0;
		1056
		1057	? ? ? 0 1 ? : ? : 0; // asynch clear
		1058
		1059	? ? ? 1 0 ? : ? : 1; // asynch set
		1060
		1061	1 ? (?0) 1 1 ? : ? : -; // ignore falling clock
		1062	1 ? (1x) 1 1 ? : ? : -; // ignore falling clock
		1063	1 * ? ? ? ? : ? : -; // ignore data edges
		1064
		1065	1 ? ? (?1) ? ? : ? : -; // ignore edges on
		1066	1 ? ? ? (?1) ? : ? : -; // set and clear
		1067
		1068
		1069
		1070	? ? ? 1 1 * : ? : x; // spr 36954 - at any
		1071	// notifier event,
		1072	// output 'x'
		1073	endtable
		1074
		1075	endprimitive // PRIM_DFFE
		1076
		1077	//////////////////////////////////////////////////////////////////////////////
		1078	//
		1079	// Module Name : FLEX10KE_DFFE
		1080	//
		1081	// Description : Timing simulation model for a DFFE register
		1082	//
		1083	//////////////////////////////////////////////////////////////////////////////
		1084
		1085	module flex10ke_dffe ( Q,
		1086	CLK,
		1087	ENA,
		1088	D,
		1089	CLRN,
		1090	PRN );
		1091
		1092	// INPUT PORTS
		1093	input D;
		1094	input CLK;
		1095	input CLRN;
		1096	input PRN;
		1097	input ENA;
		1098
		1099	// OUTPUT PORTS
		1100	output Q;
		1101
		1102	// INTERNAL VARIABLES AND NETS
		1103	wire legal;
		1104	reg viol_notifier;
		1105
		1106	// INSTANTIATE THE UDP
		1107	PRIM_DFFE ( Q, ENA, D, CLK, CLRN, PRN, viol_notifier );
		1108
		1109	// filter out illegal values like 'X'
		1110	and(legal, ENA, CLRN, PRN);
		1111
		1112	specify
		1113
		1114	specparam TREG = 0;
		1115	specparam TREN = 0;
		1116	specparam TRSU = 0;
		1117	specparam TRH = 0;
		1118	specparam TRPR = 0;
		1119	specparam TRCL = 0;
		1120
		1121	$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
		1122	$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
		1123	$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
		1124	$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
		1125
		1126	( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
		1127	( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
		1128	( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
		1129
		1130	endspecify
		1131
		1132	endmodule // flex10ke_dffe
		1133
		1134	//////////////////////////////////////////////////////////////////////////////
		1135	//
		1136	// Module Name : DFFE_IO
		1137	//
		1138	// Description : Timing simulation model for a DFFE register for IO atom
		1139	//
		1140	//////////////////////////////////////////////////////////////////////////////
		1141
		1142	module dffe_io ( Q, CLK, ENA, D, CLRN, PRN );
		1143	input D;
		1144	input CLK;
		1145	input CLRN;
		1146	input PRN;
		1147	input ENA;
		1148	output Q;
		1149
		1150	wire D_ipd;
		1151	wire ENA_ipd;
		1152	wire CLK_ipd;
		1153	wire PRN_ipd;
		1154	wire CLRN_ipd;
		1155
		1156	buf (D_ipd, D);
		1157	buf (ENA_ipd, ENA);
		1158	buf (CLK_ipd, CLK);
		1159	buf (PRN_ipd, PRN);
		1160	buf (CLRN_ipd, CLRN);
		1161
		1162	wire legal;
		1163	reg viol_notifier;
		1164
		1165	PRIM_DFFE ( Q, ENA_ipd, D_ipd, CLK_ipd, CLRN_ipd, PRN_ipd, viol_notifier);
		1166
		1167	and(legal, ENA_ipd, CLRN_ipd, PRN_ipd);
		1168
		1169	specify
		1170
		1171	specparam TREG = 0;
		1172	specparam TREN = 0;
		1173	specparam TRSU = 0;
		1174	specparam TRH = 0;
		1175	specparam TRPR = 0;
		1176	specparam TRCL = 0;
		1177
		1178	$setup ( D, posedge CLK &&& legal, TRSU, viol_notifier ) ;
		1179	$hold ( posedge CLK &&& legal, D, TRH, viol_notifier ) ;
		1180	$setup ( ENA, posedge CLK &&& legal, TREN, viol_notifier ) ;
		1181	$hold ( posedge CLK &&& legal, ENA, 0, viol_notifier ) ;
		1182
		1183	( negedge CLRN => (Q +: 1'b0)) = ( TRCL, TRCL) ;
		1184	( negedge PRN => (Q +: 1'b1)) = ( TRPR, TRPR) ;
		1185	( posedge CLK => (Q +: D)) = ( TREG, TREG) ;
		1186
		1187	endspecify
		1188	endmodule // dffe_io
		1189
		1190	//////////////////////////////////////////////////////////////////////////////
		1191	//
		1192	// Module Name : mux21
		1193	//
		1194	// Description : Simulation model for a 2 to 1 mux used in the RAM_SLICE
		1195	// This is a purely functional module, without any timing.
		1196	//
		1197	//////////////////////////////////////////////////////////////////////////////
		1198
		1199	module mux21 (MO,
		1200	A,
		1201	B,
		1202	S);
		1203	input A, B, S;
		1204	output MO;
		1205
		1206	assign MO = (S == 1) ? B : A;
		1207
		1208	endmodule // mux21
		1209
		1210	//////////////////////////////////////////////////////////////////////////////
		1211	//
		1212	// Module Name : and1
		1213	//
		1214	// Description : Simulation model for a 1-input AND gate
		1215	//
		1216	//////////////////////////////////////////////////////////////////////////////
		1217
		1218	module and1 (Y,
		1219	IN1);
		1220	input IN1;
		1221	output Y;
		1222
		1223	specify
		1224	(IN1 => Y) = (0, 0);
		1225	endspecify
		1226
		1227	buf (Y, IN1);
		1228	endmodule // and1
		1229
		1230	//////////////////////////////////////////////////////////////////////////////
		1231	//
		1232	// Module Name : and11
		1233	//
		1234	// Description : Simulation model for a 11-input AND gate
		1235	//
		1236	//////////////////////////////////////////////////////////////////////////////
		1237
		1238	module and11 (Y, IN1);
		1239	input [10:0] IN1;
		1240	output [10:0] Y;
		1241
		1242	specify
		1243	(IN1 => Y) = (0, 0);
		1244	endspecify
		1245
		1246	buf (Y[0], IN1[0]);
		1247	buf (Y[1], IN1[1]);
		1248	buf (Y[2], IN1[2]);
		1249	buf (Y[3], IN1[3]);
		1250	buf (Y[4], IN1[4]);
		1251	buf (Y[5], IN1[5]);
		1252	buf (Y[6], IN1[6]);
		1253	buf (Y[7], IN1[7]);
		1254	buf (Y[8], IN1[8]);
		1255	buf (Y[9], IN1[9]);
		1256	buf (Y[10], IN1[10]);
		1257
		1258	endmodule // and11
		1259
		1260	//////////////////////////////////////////////////////////////////////////////
		1261	//
		1262	// Module Name : nmux21
		1263	//
		1264	// Description : Simulation model for a 2 to 1 mux used in the RAM_SLICE
		1265	// The output is an inversion of the selected input.
		1266	// This is a purely functional module, without any timing.
		1267	//
		1268	//////////////////////////////////////////////////////////////////////////////
		1269
		1270	module nmux21 (MO,
		1271	A,
		1272	B,
		1273	S);
		1274	input A, B, S;
		1275	output MO;
		1276
		1277	assign MO = (S == 1) ? ~B : ~A;
		1278
		1279	endmodule // nmux21
		1280
		1281	//////////////////////////////////////////////////////////////////////////////
		1282	//
		1283	// Module Name : bmux21
		1284	//
		1285	// Description : Simulation model for a 2 to 1 mux used in the RAM_SLICE
		1286	// Each input is a 16-bit bus.
		1287	// This is a purely functional module, without any timing.
		1288	//
		1289	//////////////////////////////////////////////////////////////////////////////
		1290
		1291	module bmux21 (MO,
		1292	A,
		1293	B,
		1294	S);
		1295
		1296	input [10:0] A, B;
		1297	input S;
		1298	output [10:0] MO;
		1299
		1300	assign MO = (S == 1) ? B : A;
		1301
		1302	endmodule // bmux21
		1303
		1304	//////////////////////////////////////////////////////////////////////////////
		1305	//
		1306	// Module Name : b5mux21
		1307	//
		1308	// Description : Simulation model for a 2 to 1 mux used in the CAM_SLICE.
		1309	// Each input is a 5-bit bus.
		1310	// This is a purely functional module, without any timing.
		1311	//
		1312	//////////////////////////////////////////////////////////////////////////////
		1313
		1314	module b5mux21 (MO,
		1315	A,
		1316	B,
		1317	S);
		1318	input [4:0] A, B;
		1319	input S;
		1320	output [4:0] MO;
		1321
		1322	assign MO = (S == 1) ? B : A;
		1323
		1324	endmodule // b5mux21
		1325
		1326	//////////////////////////////////////////////////////////////////////////////
		1327	//
		1328	// Module Name : FLEX10KE_RAM_SLICE
		1329	//
		1330	// Description : Timing simulation model for a single RAM segment of the
		1331	// FLEX10KE family.
		1332	// This model is a top-level structural description of the
		1333	// RAM segment. It instantiates the peripheral registers,
		1334	// mode-control multiplexers and the asynchronous memory
		1335	// array.
		1336	//
		1337	//////////////////////////////////////////////////////////////////////////////
		1338
		1339	module flex10ke_ram_slice (datain,
		1340	clr0,
		1341	clk0,
		1342	clk1,
		1343	ena0,
		1344	ena1,
		1345	we,
		1346	re,
		1347	waddr,
		1348	raddr,
		1349	devclrn,
		1350	devpor,
		1351	modesel,
		1352	dataout
		1353	);
		1354
		1355	// INPUT PORTS
		1356	input datain;
		1357	input clk0;
		1358	input clk1;
		1359	input clr0;
		1360	input ena0;
		1361	input ena1;
		1362	input we;
		1363	input re;
		1364	input devclrn;
		1365	input devpor;
		1366	input [10:0] raddr;
		1367	input [10:0] waddr;
		1368	input [15:0] modesel;
		1369
		1370	// OUTPUT PORTS
		1371	output dataout;
		1372
		1373	// GLOBAL PARAMETERS
		1374	parameter operation_mode = "single_port";
		1375	parameter logical_ram_name = "ram_xxx";
		1376	parameter logical_ram_depth = "2k";
		1377	parameter logical_ram_width = "1";
		1378	parameter address_width = 11;
		1379	parameter data_in_clock = "none";
		1380	parameter data_in_clear = "none";
		1381	parameter write_logic_clock = "none";
		1382	parameter write_address_clear = "none";
		1383	parameter write_enable_clear = "none";
		1384	parameter read_enable_clock = "none";
		1385	parameter read_enable_clear = "none";
		1386	parameter read_address_clock = "none";
		1387	parameter read_address_clear = "none";
		1388	parameter data_out_clock = "none";
		1389	parameter data_out_clear = "none";
		1390	parameter init_file = "none";
		1391	parameter first_address = 0;
		1392	parameter last_address = 2047;
		1393	parameter bit_number = "1";
		1394	parameter mem1 = 512'b0;
		1395	parameter mem2 = 512'b0;
		1396	parameter mem3 = 512'b0;
		1397	parameter mem4 = 512'b0;
		1398
		1399	// INTERNAL NETS AND VARIABLES
		1400	wire datain_reg, we_reg, re_reg, dataout_reg;
		1401	wire we_reg_mux, we_reg_mux_delayed;
		1402	wire [10:0] raddr_reg, waddr_reg;
		1403	wire datain_int, we_int, re_int, dataout_int, dataout_tmp;
		1404	wire [10:0] raddr_int, waddr_int;
		1405	wire reen, raddren, dataouten;
		1406	wire datain_clr;
		1407	wire re_clk, raddr_clk;
		1408	wire datain_reg_sel, write_reg_sel, raddr_reg_sel;
		1409	wire re_reg_sel, dataout_reg_sel, re_clk_sel, re_en_sel;
		1410	wire raddr_clk_sel, raddr_en_sel;
		1411	wire dataout_en_sel;
		1412	wire datain_reg_clr, waddr_reg_clr, raddr_reg_clr;
		1413	wire re_reg_clr, dataout_reg_clr, we_reg_clr;
		1414	wire datain_reg_clr_sel;
		1415	wire waddr_reg_clr_sel;
		1416	wire we_reg_clr_sel;
		1417	wire raddr_reg_clr_sel;
		1418	wire re_reg_clr_sel, dataout_reg_clr_sel, NC;
		1419	wire we_pulse;
		1420
		1421	wire clk0_delayed;
		1422
		1423	reg we_int_delayed, datain_int_delayed;
		1424	reg [10:0] waddr_int_delayed;
		1425
		1426	// PULL UPs
		1427	tri1 iena0;
		1428	tri1 iena1;
		1429
		1430	// READ MODESEL PORT BITS
		1431	assign datain_reg_sel = modesel[0];
		1432	assign datain_reg_clr_sel = modesel[1];
		1433	assign write_reg_sel = modesel[2];
		1434	assign waddr_reg_clr_sel = modesel[15];
		1435	assign we_reg_clr_sel = modesel[3];
		1436	assign raddr_reg_sel = modesel[4];
		1437	assign raddr_reg_clr_sel = modesel[5];
		1438	assign re_reg_sel = modesel[6];
		1439	assign re_reg_clr_sel = modesel[7];
		1440	assign dataout_reg_sel = modesel[8];
		1441	assign dataout_reg_clr_sel = modesel[9];
		1442	assign re_clk_sel = modesel[10];
		1443	assign re_en_sel = modesel[10];
		1444	assign raddr_clk_sel = modesel[11];
		1445	assign raddr_en_sel = modesel[11];
		1446	assign dataout_en_sel = modesel[12];
		1447
		1448	assign iena0 = ena0;
		1449	assign iena1 = ena1;
		1450	assign NC = 0;
		1451
		1452
		1453	always @ (datain_int or waddr_int or we_int)
		1454	begin
		1455	we_int_delayed = we_int;
		1456	waddr_int_delayed <= waddr_int;
		1457	datain_int_delayed <= datain_int;
		1458	end
		1459
		1460	mux21 datainsel (datain_int,
		1461	datain,
		1462	datain_reg,
		1463	datain_reg_sel
		1464	);
		1465	nmux21 datainregclr (datain_reg_clr,
		1466	NC,
		1467	clr0,
		1468	datain_reg_clr_sel
		1469	);
		1470	bmux21 waddrsel (waddr_int,
		1471	waddr,
		1472	waddr_reg,
		1473	write_reg_sel
		1474	);
		1475	nmux21 waddrregclr (waddr_reg_clr,
		1476	NC,
		1477	clr0,
		1478	waddr_reg_clr_sel
		1479	);
		1480	nmux21 weregclr (we_reg_clr,
		1481	NC,
		1482	clr0,
		1483	we_reg_clr_sel
		1484	);
		1485	mux21 wesel2 (we_int,
		1486	we_reg_mux_delayed,
		1487	we_pulse,
		1488	write_reg_sel
		1489	);
		1490	mux21 wesel1 (we_reg_mux,
		1491	we,
		1492	we_reg,
		1493	write_reg_sel
		1494	);
		1495	bmux21 raddrsel (raddr_int,
		1496	raddr,
		1497	raddr_reg,
		1498	raddr_reg_sel
		1499	);
		1500	nmux21 raddrregclr (raddr_reg_clr,
		1501	NC,
		1502	clr0,
		1503	raddr_reg_clr_sel
		1504	);
		1505	mux21 resel (re_int,
		1506	re,
		1507	re_reg,
		1508	re_reg_sel
		1509	);
		1510	mux21 dataoutsel (dataout_tmp,
		1511	dataout_int,
		1512	dataout_reg,
		1513	dataout_reg_sel
		1514	);
		1515	nmux21 dataoutregclr (dataout_reg_clr,
		1516	NC,
		1517	clr0,
		1518	dataout_reg_clr_sel
		1519	);
		1520	mux21 raddrclksel (raddr_clk,
		1521	clk0,
		1522	clk1,
		1523	raddr_clk_sel
		1524	);
		1525	mux21 raddrensel (raddren,
		1526	iena0,
		1527	iena1,
		1528	raddr_en_sel
		1529	);
		1530	mux21 reclksel (re_clk,
		1531	clk0,
		1532	clk1,
		1533	re_clk_sel
		1534	);
		1535	mux21 reensel (reen,
		1536	iena0,
		1537	iena1,
		1538	re_en_sel
		1539	);
		1540	nmux21 reregclr (re_reg_clr,
		1541	NC,
		1542	clr0,
		1543	re_reg_clr_sel
		1544	);
		1545	mux21 dataoutensel (dataouten,
		1546	NC,
		1547	iena1,
		1548	dataout_en_sel
		1549	);
		1550	flex10ke_dffe dinreg (datain_reg,
		1551	clk0,
		1552	iena0,
		1553	datain,
		1554	datain_reg_clr && devclrn && devpor,
		1555	1'b1
		1556	);
		1557	flex10ke_dffe wereg (we_reg,
		1558	clk0,
		1559	iena0,
		1560	we,
		1561	we_reg_clr && devclrn && devpor,
		1562	1'b1
		1563	);
		1564
		1565	// clk0 for we_pulse should have same delay as clk of wereg
		1566	and1 clk0weregdelaybuf (clk0_delayed,
		1567	clk0
		1568	);
		1569	assign we_pulse = we_reg_mux_delayed && (~clk0_delayed);
		1570
		1571	and1 wedelaybuf (we_reg_mux_delayed,
		1572	we_reg_mux
		1573	);
		1574	flex10ke_dffe rereg (re_reg,
		1575	re_clk,
		1576	reen,
		1577	re,
		1578	re_reg_clr && devclrn && devpor,
		1579	1'b1
		1580	);
		1581	flex10ke_dffe dataoutreg (dataout_reg,
		1582	clk1,
		1583	dataouten,
		1584	dataout_int,
		1585	dataout_reg_clr && devclrn && devpor,
		1586	1'b1
		1587	);
		1588
		1589	flex10ke_dffe waddrreg_0 (waddr_reg[0],
		1590	clk0,
		1591	iena0,
		1592	waddr[0],
		1593	waddr_reg_clr && devclrn && devpor,
		1594	1'b1
		1595	);
		1596	flex10ke_dffe waddrreg_1 (waddr_reg[1],
		1597	clk0,
		1598	iena0,
		1599	waddr[1],
		1600	waddr_reg_clr && devclrn && devpor,
		1601	1'b1
		1602	);
		1603	flex10ke_dffe waddrreg_2 (waddr_reg[2],
		1604	clk0,
		1605	iena0,
		1606	waddr[2],
		1607	waddr_reg_clr && devclrn && devpor,
		1608	1'b1
		1609	);
		1610	flex10ke_dffe waddrreg_3 (waddr_reg[3],
		1611	clk0,
		1612	iena0,
		1613	waddr[3],
		1614	waddr_reg_clr && devclrn && devpor,
		1615	1'b1
		1616	);
		1617	flex10ke_dffe waddrreg_4 (waddr_reg[4],
		1618	clk0,
		1619	iena0,
		1620	waddr[4],
		1621	waddr_reg_clr && devclrn && devpor,
		1622	1'b1
		1623	);
		1624	flex10ke_dffe waddrreg_5 (waddr_reg[5],
		1625	clk0,
		1626	iena0,
		1627	waddr[5],
		1628	waddr_reg_clr && devclrn && devpor,
		1629	1'b1
		1630	);
		1631	flex10ke_dffe waddrreg_6 (waddr_reg[6],
		1632	clk0,
		1633	iena0,
		1634	waddr[6],
		1635	waddr_reg_clr && devclrn && devpor,
		1636	1'b1
		1637	);
		1638	flex10ke_dffe waddrreg_7 (waddr_reg[7],
		1639	clk0,
		1640	iena0,
		1641	waddr[7],
		1642	waddr_reg_clr && devclrn && devpor,
		1643	1'b1
		1644	);
		1645	flex10ke_dffe waddrreg_8 (waddr_reg[8],
		1646	clk0,
		1647	iena0,
		1648	waddr[8],
		1649	waddr_reg_clr && devclrn && devpor,
		1650	1'b1
		1651	);
		1652	flex10ke_dffe waddrreg_9 (waddr_reg[9],
		1653	clk0,
		1654	iena0,
		1655	waddr[9],
		1656	waddr_reg_clr && devclrn && devpor,
		1657	1'b1
		1658	);
		1659	flex10ke_dffe waddrreg_10 (waddr_reg[10],
		1660	clk0,
		1661	iena0,
		1662	waddr[10],
		1663	waddr_reg_clr && devclrn && devpor,
		1664	1'b1
		1665	);
		1666
		1667	flex10ke_dffe raddrreg_0 (raddr_reg[0],
		1668	raddr_clk,
		1669	raddren,
		1670	raddr[0],
		1671	raddr_reg_clr && devclrn && devpor,
		1672	1'b1
		1673	);
		1674	flex10ke_dffe raddrreg_1 (raddr_reg[1],
		1675	raddr_clk,
		1676	raddren,
		1677	raddr[1],
		1678	raddr_reg_clr && devclrn && devpor,
		1679	1'b1
		1680	);
		1681	flex10ke_dffe raddrreg_2 (raddr_reg[2],
		1682	raddr_clk,
		1683	raddren,
		1684	raddr[2],
		1685	raddr_reg_clr && devclrn && devpor,
		1686	1'b1
		1687	);
		1688	flex10ke_dffe raddrreg_3 (raddr_reg[3],
		1689	raddr_clk,
		1690	raddren,
		1691	raddr[3],
		1692	raddr_reg_clr && devclrn && devpor,
		1693	1'b1
		1694	);
		1695	flex10ke_dffe raddrreg_4 (raddr_reg[4],
		1696	raddr_clk,
		1697	raddren,
		1698	raddr[4],
		1699	raddr_reg_clr && devclrn && devpor,
		1700	1'b1
		1701	);
		1702	flex10ke_dffe raddrreg_5 (raddr_reg[5],
		1703	raddr_clk,
		1704	raddren,
		1705	raddr[5],
		1706	raddr_reg_clr && devclrn && devpor,
		1707	1'b1
		1708	);
		1709	flex10ke_dffe raddrreg_6 (raddr_reg[6],
		1710	raddr_clk,
		1711	raddren,
		1712	raddr[6],
		1713	raddr_reg_clr && devclrn && devpor,
		1714	1'b1
		1715	);
		1716	flex10ke_dffe raddrreg_7 (raddr_reg[7],
		1717	raddr_clk,
		1718	raddren,
		1719	raddr[7],
		1720	raddr_reg_clr && devclrn && devpor,
		1721	1'b1
		1722	);
		1723	flex10ke_dffe raddrreg_8 (raddr_reg[8],
		1724	raddr_clk,
		1725	raddren,
		1726	raddr[8],
		1727	raddr_reg_clr && devclrn && devpor,
		1728	1'b1
		1729	);
		1730	flex10ke_dffe raddrreg_9 (raddr_reg[9],
		1731	raddr_clk,
		1732	raddren,
		1733	raddr[9],
		1734	raddr_reg_clr && devclrn && devpor,
		1735	1'b1
		1736	);
		1737	flex10ke_dffe raddrreg_10 (raddr_reg[10],
		1738	raddr_clk,
		1739	raddren,
		1740	raddr[10],
		1741	raddr_reg_clr && devclrn && devpor,
		1742	1'b1
		1743	);
		1744
		1745	flex10ke_asynch_mem flexmem (datain_int_delayed,
		1746	we_int_delayed,
		1747	re_int,
		1748	raddr_int,
		1749	waddr_int_delayed,
		1750	modesel,
		1751	dataout_int
		1752	);
		1753
		1754	defparam
		1755	flexmem.address_width = address_width,
		1756	flexmem.bit_number = bit_number,
		1757	flexmem.logical_ram_depth = logical_ram_depth,
		1758	flexmem.first_address = first_address,
		1759	flexmem.last_address = last_address,
		1760	flexmem.write_logic_clock = write_logic_clock,
		1761	flexmem.read_enable_clock = read_enable_clock,
		1762	flexmem.data_out_clock = data_out_clock,
		1763	flexmem.infile = init_file,
		1764	flexmem.operation_mode = operation_mode,
		1765	flexmem.mem1 = mem1,
		1766	flexmem.mem2 = mem2,
		1767	flexmem.mem3 = mem3,
		1768	flexmem.mem4 = mem4;
		1769
		1770	assign dataout = dataout_tmp;
		1771
		1772	endmodule // flex10ke_ram_slice
		1773
		1774	/////////////////////////////////////////////////////////////////////////////
		1775	//
		1776	// Module Name : FLEX10KE_PLL
		1777	//
		1778	// Description : Simulation model for the FLEX10KE device family PLL.
		1779	//
		1780	/////////////////////////////////////////////////////////////////////////////
		1781
		1782	`timescale 1 ns / 1 ps
		1783	module flex10ke_pll (clk,
		1784	clk0,
		1785	clk1,
		1786	locked
		1787	);
		1788
		1789	// INPUT PORTS
		1790	input clk;
		1791
		1792	// OUTPUT PORTS
		1793	output clk0;
		1794	output clk1;
		1795	output locked;
		1796
		1797	// GLOBAL PARAMETERS
		1798	parameter clk0_multiply_by = 1;
		1799	parameter clk1_multiply_by = 1;
		1800	parameter input_frequency = 1000;
		1801
		1802	// INTERNAL VARIABLES AND NETS
		1803	reg start_inclk;
		1804	reg new_inclk0;
		1805	reg new_inclk1;
		1806	reg pll_lock;
		1807	reg clkout0_tmp;
		1808	reg clkout1_tmp;
		1809	reg locked_tmp;
		1810
		1811	real pll_last_rising_edge;
		1812	real pll_last_falling_edge;
		1813	real actual_clk_cycle;
		1814	real expected_clk_cycle;
		1815	real pll_duty_cycle;
		1816	real pll1_half_period;
		1817	real pll2_half_period;
		1818
		1819	integer pll_rising_edge_count;
		1820	integer clk0_count;
		1821	integer clk1_count;
		1822	integer i;
		1823	integer j;
		1824
		1825	specify
		1826
		1827	endspecify
		1828
		1829	initial
		1830	begin
		1831	clk0_count = -1;
		1832	clk1_count = -1;
		1833	pll_rising_edge_count = 0;
		1834	pll_lock = 1;
		1835	clkout0_tmp = 1'b0;
		1836	clkout1_tmp = 1'b0;
		1837	locked_tmp = 1'b0;
		1838
		1839	// resolve the parameters
		1840
		1841	if (clk0_multiply_by > clk1_multiply_by)
		1842	$display("");
		1843	end
		1844
		1845	always @(posedge clk)
		1846	begin
		1847	if (pll_rising_edge_count == 0) // this is first rising edge
		1848	start_inclk = clk;
		1849	else if (pll_rising_edge_count == 1) // this is second rising edge
		1850	begin
		1851	expected_clk_cycle = input_frequency / 1000.0; // convert to ns
		1852	actual_clk_cycle = $realtime - pll_last_rising_edge;
		1853	if (actual_clk_cycle < (expected_clk_cycle - 1.0) \|\|
		1854	actual_clk_cycle > (expected_clk_cycle + 1.0))
		1855	begin
		1856	$display($realtime, "Warning: Input frequency Violation");
		1857	pll_lock = 0;
		1858	locked_tmp = 0;
		1859	end
		1860	if ( ($realtime - pll_last_falling_edge) < (pll_duty_cycle - 0.1) \|\| ($realtime - pll_last_falling_edge) > (pll_duty_cycle + 0.1) )
		1861	begin
		1862	$display($realtime, "Warning: Duty Cycle Violation");
		1863	pll_lock = 0;
		1864	locked_tmp = 0;
		1865	end
		1866	end
		1867	else if ( ($realtime - pll_last_rising_edge) < (actual_clk_cycle - 0.1) \|\|
		1868	($realtime - pll_last_rising_edge) > (actual_clk_cycle + 0.1) )
		1869	begin
		1870	$display($realtime, "Warning : Cycle Violation");
		1871	pll_lock = 0;
		1872	locked_tmp = 0;
		1873	end
		1874	pll_rising_edge_count = pll_rising_edge_count + 1;
		1875	pll_last_rising_edge = $realtime;
		1876	end
		1877
		1878	always @(negedge clk)
		1879	begin
		1880	if (pll_rising_edge_count == 1)
		1881	begin
		1882	pll1_half_period = ($realtime - pll_last_rising_edge)/clk0_multiply_by;
		1883	pll2_half_period = ($realtime - pll_last_rising_edge)/clk1_multiply_by;
		1884	pll_duty_cycle = $realtime - pll_last_rising_edge;
		1885	end
		1886	else if ( ($realtime - pll_last_rising_edge) < (pll_duty_cycle - 0.1) \|\|
		1887	($realtime - pll_last_rising_edge) > (pll_duty_cycle + 0.1) )
		1888	begin
		1889	$display($realtime, "Warning: Duty Cycle Violation");
		1890	pll_lock = 0;
		1891	locked_tmp = 0;
		1892	end
		1893	pll_last_falling_edge = $realtime;
		1894	end
		1895
		1896	always @(pll_rising_edge_count)
		1897	begin
		1898	if (pll_rising_edge_count > 2)
		1899	begin
		1900	for (i=1; i<= 2*clk0_multiply_by - 1; i=i+1)
		1901	begin
		1902	clk0_count = clk0_count + 1;
		1903	#pll1_half_period;
		1904	end
		1905	clk0_count = clk0_count + 1;
		1906	end
		1907	else
		1908	clk0_count = 0;
		1909	end
		1910
		1911	always @(pll_rising_edge_count)
		1912	begin
		1913	if (pll_rising_edge_count > 2) // pll locks after 2 cycles
		1914	begin
		1915	for (j=1; j<= 2*clk1_multiply_by - 1; j=j+1)
		1916	begin
		1917	clk1_count = clk1_count + 1;
		1918	#pll2_half_period;
		1919	end
		1920	clk1_count = clk1_count + 1;
		1921	end
		1922	else
		1923	clk1_count = 0;
		1924	end
		1925
		1926	always @(clk0_count)
		1927	begin
		1928	if (clk0_count <= 0)
		1929	clkout0_tmp = 1'b0;
		1930	else if (pll_lock == 0)
		1931	clkout0_tmp = 1'b0;
		1932	else if (clk0_count == 1)
		1933	begin
		1934	locked_tmp = 1'b1;
		1935	clkout0_tmp = start_inclk;
		1936	new_inclk0 = ~start_inclk;
		1937	end
		1938	else
		1939	begin
		1940	clkout0_tmp = new_inclk0;
		1941	new_inclk0 = ~new_inclk0;
		1942	end
		1943	end
		1944
		1945	always @(clk1_count)
		1946	begin
		1947	if (clk1_count <= 0)
		1948	clkout1_tmp = 1'b0;
		1949	else if (pll_lock == 0)
		1950	clkout1_tmp = 1'b0;
		1951	else if (clk1_count == 1)
		1952	begin
		1953	locked_tmp = 1'b1;
		1954	clkout1_tmp = start_inclk;
		1955	new_inclk1 = ~start_inclk;
		1956	end
		1957	else
		1958	begin
		1959	clkout1_tmp = new_inclk1;
		1960	new_inclk1 = ~new_inclk1;
		1961	end
		1962	end
		1963
		1964	// ACCELERATE OUTPUTS
		1965	assign clk0 = clkout0_tmp;
		1966	assign clk1 = clkout1_tmp;
		1967	assign locked = locked_tmp;
		1968
		1969	endmodule
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Subversion Repositories pentevo

(root)/fpga/base_trdemu/trunk/sim_top/gate/flex10ke_atoms.v – Rev 905