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668 lvd 1 
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
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//
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// reset generator
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/*
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    This file is part of ZX-Evo Base Configuration firmware.
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    ZX-Evo Base Configuration firmware is free software:
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    you can redistribute it and/or modify it under the terms of
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    the GNU General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    ZX-Evo Base Configuration firmware is distributed in the hope that
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    it will be useful, but WITHOUT ANY WARRANTY; without even
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    the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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    See the GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with ZX-Evo Base Configuration firmware.
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    If not, see <http://www.gnu.org/licenses/>.
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*/
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425 lvd 24 
`include "../include/tune.v"
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4 lvd 26 
module resetter(
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        clk,
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        rst_in_n,
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        rst_out_n );
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parameter RST_CNT_SIZE = 4;
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        input clk;
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        input rst_in_n; // input of external asynchronous reset
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        output rst_out_n; // output of end-synchronized reset (beginning is asynchronous to clock)
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        reg    rst_out_n;
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        reg [RST_CNT_SIZE:0] rst_cnt; // one bit more for counter stopping
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        reg rst1_n,rst2_n;
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`ifdef SIMULATE
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        initial
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        begin
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                rst_cnt = 0;
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                rst1_n = 1'b0;
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                rst2_n = 1'b0;
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                rst_out_n = 1'b0;
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        end
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`endif
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4 lvd 63 
        always @(posedge clk, negedge rst_in_n)
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        if( !rst_in_n ) // external asynchronous reset
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        begin
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                rst_cnt <= 0;
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                rst1_n <= 1'b0;
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                rst2_n <= 1'b0;
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                rst_out_n <= 1'b0; // this zeroing also happens after FPGA configuration, so also power-up reset happens
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        end
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        else // clocking
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        begin
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                rst1_n <= 1'b1;
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                rst2_n <= rst1_n;
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                if( rst2_n && !rst_cnt[RST_CNT_SIZE] )
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                begin
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                        rst_cnt <= rst_cnt + 1;
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                end
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                if( rst_cnt[RST_CNT_SIZE] )
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                begin
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                        rst_out_n <= 1'b1;
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                end
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        end
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endmodule
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