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4 | lvd | 1 | -- **** |
2 | -- T80(b) core. In an effort to merge and maintain bug fixes .... |
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3 | -- |
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4 | -- |
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5 | -- Ver 300 started tidyup |
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6 | -- MikeJ March 2005 |
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7 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) |
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8 | -- |
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9 | -- **** |
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10 | -- |
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11 | -- Z80 compatible microprocessor core |
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12 | -- |
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13 | -- Version : 0242 |
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14 | -- |
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15 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
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16 | -- |
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17 | -- All rights reserved |
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18 | -- |
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19 | -- Redistribution and use in source and synthezised forms, with or without |
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20 | -- modification, are permitted provided that the following conditions are met: |
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21 | -- |
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22 | -- Redistributions of source code must retain the above copyright notice, |
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23 | -- this list of conditions and the following disclaimer. |
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24 | -- |
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25 | -- Redistributions in synthesized form must reproduce the above copyright |
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26 | -- notice, this list of conditions and the following disclaimer in the |
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27 | -- documentation and/or other materials provided with the distribution. |
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28 | -- |
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29 | -- Neither the name of the author nor the names of other contributors may |
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30 | -- be used to endorse or promote products derived from this software without |
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31 | -- specific prior written permission. |
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32 | -- |
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33 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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34 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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35 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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36 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
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37 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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38 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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39 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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40 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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41 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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42 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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43 | -- POSSIBILITY OF SUCH DAMAGE. |
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44 | -- |
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45 | -- Please report bugs to the author, but before you do so, please |
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46 | -- make sure that this is not a derivative work and that |
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47 | -- you have the latest version of this file. |
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48 | -- |
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49 | -- The latest version of this file can be found at: |
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50 | -- http://www.opencores.org/cvsweb.shtml/t80/ |
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51 | -- |
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52 | -- Limitations : |
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53 | -- |
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54 | -- File history : |
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55 | -- |
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56 | |||
57 | library IEEE; |
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58 | use IEEE.std_logic_1164.all; |
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59 | |||
60 | package T80_Pack is |
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61 | |||
62 | component T80 |
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63 | generic( |
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64 | Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB |
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65 | IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle |
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66 | Flag_C : integer := 0; |
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67 | Flag_N : integer := 1; |
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68 | Flag_P : integer := 2; |
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69 | Flag_X : integer := 3; |
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70 | Flag_H : integer := 4; |
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71 | Flag_Y : integer := 5; |
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72 | Flag_Z : integer := 6; |
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73 | Flag_S : integer := 7 |
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74 | ); |
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75 | port( |
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76 | RESET_n : in std_logic; |
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77 | CLK_n : in std_logic; |
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78 | CEN : in std_logic; |
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79 | WAIT_n : in std_logic; |
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80 | INT_n : in std_logic; |
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81 | NMI_n : in std_logic; |
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82 | BUSRQ_n : in std_logic; |
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83 | M1_n : out std_logic; |
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84 | IORQ : out std_logic; |
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85 | NoRead : out std_logic; |
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86 | Write : out std_logic; |
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87 | RFSH_n : out std_logic; |
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88 | HALT_n : out std_logic; |
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89 | BUSAK_n : out std_logic; |
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90 | A : out std_logic_vector(15 downto 0); |
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91 | DInst : in std_logic_vector(7 downto 0); |
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92 | DI : in std_logic_vector(7 downto 0); |
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93 | DO : out std_logic_vector(7 downto 0); |
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94 | MC : out std_logic_vector(2 downto 0); |
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95 | TS : out std_logic_vector(2 downto 0); |
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96 | IntCycle_n : out std_logic; |
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97 | IntE : out std_logic; |
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684 | lvd | 98 | Stop : out std_logic; |
99 | ResetPC : in std_logic_vector(15 downto 0); |
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100 | ResetSP : in std_logic_vector(15 downto 0) |
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4 | lvd | 101 | ); |
102 | end component; |
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103 | |||
104 | component T80_Reg |
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105 | port( |
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106 | Clk : in std_logic; |
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107 | CEN : in std_logic; |
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108 | WEH : in std_logic; |
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109 | WEL : in std_logic; |
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110 | AddrA : in std_logic_vector(2 downto 0); |
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111 | AddrB : in std_logic_vector(2 downto 0); |
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112 | AddrC : in std_logic_vector(2 downto 0); |
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113 | DIH : in std_logic_vector(7 downto 0); |
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114 | DIL : in std_logic_vector(7 downto 0); |
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115 | DOAH : out std_logic_vector(7 downto 0); |
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116 | DOAL : out std_logic_vector(7 downto 0); |
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117 | DOBH : out std_logic_vector(7 downto 0); |
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118 | DOBL : out std_logic_vector(7 downto 0); |
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119 | DOCH : out std_logic_vector(7 downto 0); |
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120 | DOCL : out std_logic_vector(7 downto 0) |
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121 | ); |
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122 | end component; |
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123 | |||
124 | component T80_MCode |
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125 | generic( |
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126 | Mode : integer := 0; |
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127 | Flag_C : integer := 0; |
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128 | Flag_N : integer := 1; |
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129 | Flag_P : integer := 2; |
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130 | Flag_X : integer := 3; |
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131 | Flag_H : integer := 4; |
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132 | Flag_Y : integer := 5; |
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133 | Flag_Z : integer := 6; |
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134 | Flag_S : integer := 7 |
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135 | ); |
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136 | port( |
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137 | IR : in std_logic_vector(7 downto 0); |
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138 | ISet : in std_logic_vector(1 downto 0); |
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139 | MCycle : in std_logic_vector(2 downto 0); |
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140 | F : in std_logic_vector(7 downto 0); |
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141 | NMICycle : in std_logic; |
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142 | IntCycle : in std_logic; |
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143 | MCycles : out std_logic_vector(2 downto 0); |
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144 | TStates : out std_logic_vector(2 downto 0); |
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145 | Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD |
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146 | Inc_PC : out std_logic; |
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147 | Inc_WZ : out std_logic; |
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148 | IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc |
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149 | Read_To_Reg : out std_logic; |
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150 | Read_To_Acc : out std_logic; |
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151 | Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F |
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152 | Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 |
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153 | ALU_Op : out std_logic_vector(3 downto 0); |
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154 | -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None |
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155 | Save_ALU : out std_logic; |
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156 | PreserveC : out std_logic; |
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157 | Arith16 : out std_logic; |
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158 | Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI |
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159 | IORQ : out std_logic; |
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160 | Jump : out std_logic; |
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161 | JumpE : out std_logic; |
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162 | JumpXY : out std_logic; |
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163 | Call : out std_logic; |
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164 | RstP : out std_logic; |
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165 | LDZ : out std_logic; |
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166 | LDW : out std_logic; |
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167 | LDSPHL : out std_logic; |
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168 | Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None |
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169 | ExchangeDH : out std_logic; |
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170 | ExchangeRp : out std_logic; |
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171 | ExchangeAF : out std_logic; |
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172 | ExchangeRS : out std_logic; |
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173 | I_DJNZ : out std_logic; |
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174 | I_CPL : out std_logic; |
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175 | I_CCF : out std_logic; |
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176 | I_SCF : out std_logic; |
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177 | I_RETN : out std_logic; |
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178 | I_BT : out std_logic; |
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179 | I_BC : out std_logic; |
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180 | I_BTR : out std_logic; |
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181 | I_RLD : out std_logic; |
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182 | I_RRD : out std_logic; |
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183 | I_INRC : out std_logic; |
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184 | SetDI : out std_logic; |
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185 | SetEI : out std_logic; |
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186 | IMode : out std_logic_vector(1 downto 0); |
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187 | Halt : out std_logic; |
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188 | NoRead : out std_logic; |
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189 | Write : out std_logic |
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190 | ); |
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191 | end component; |
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192 | |||
193 | component T80_ALU |
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194 | generic( |
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195 | Mode : integer := 0; |
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196 | Flag_C : integer := 0; |
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197 | Flag_N : integer := 1; |
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198 | Flag_P : integer := 2; |
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199 | Flag_X : integer := 3; |
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200 | Flag_H : integer := 4; |
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201 | Flag_Y : integer := 5; |
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202 | Flag_Z : integer := 6; |
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203 | Flag_S : integer := 7 |
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204 | ); |
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205 | port( |
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206 | Arith16 : in std_logic; |
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207 | Z16 : in std_logic; |
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208 | ALU_Op : in std_logic_vector(3 downto 0); |
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209 | IR : in std_logic_vector(5 downto 0); |
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210 | ISet : in std_logic_vector(1 downto 0); |
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211 | BusA : in std_logic_vector(7 downto 0); |
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212 | BusB : in std_logic_vector(7 downto 0); |
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213 | F_In : in std_logic_vector(7 downto 0); |
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214 | Q : out std_logic_vector(7 downto 0); |
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215 | F_Out : out std_logic_vector(7 downto 0) |
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216 | ); |
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217 | end component; |
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218 | |||
219 | end; |