WebSVN – pentevo – Blame – /fpga/current/quartus/top.qsf

Rev	Author	Line No.	Line
4	lvd	1	# Copyright (C) 1991-2006 Altera Corporation
134	ddp	2	# Your use of Altera Corporation's design tools, logic functions
		3	# and other software and tools, and its AMPP partner logic
		4	# functions, and any output files from any of the foregoing
		5	# (including device programming or simulation files), and any
		6	# associated documentation or information are expressly subject
		7	# to the terms and conditions of the Altera Program License
		8	# Subscription Agreement, Altera MegaCore Function License
		9	# Agreement, or other applicable license agreement, including,
		10	# without limitation, that your use is for the sole purpose of
		11	# programming logic devices manufactured by Altera and sold by
		12	# Altera or its authorized distributors. Please refer to the
4	lvd	13	# applicable agreement for further details.
		14
		15
		16	# The default values for assignments are stored in the file
		17	# top_assignment_defaults.qdf
		18	# If this file doesn't exist, and for assignments not listed, see file
		19	# assignment_defaults.qdf
		20
		21	# Altera recommends that you do not modify this file. This
		22	# file is updated automatically by the Quartus II software
		23	# and any changes you make may be lost or overwritten.
		24
		25
		26	set_global_assignment -name DEVICE "EP1K50QC208-3"
		27	set_global_assignment -name FAMILY ACEX1K
		28	set_global_assignment -name TOP_LEVEL_ENTITY top
		29	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
		30	set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:03:44 NOVEMBER 07, 2009"
742	DimkaM	31	set_global_assignment -name LAST_QUARTUS_VERSION 8.1
4	lvd	32	set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
		33	set_global_assignment -name DEVICE_FILTER_PIN_COUNT 208
		34	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 3
		35	set_location_assignment PIN_7 -to iorq_n
		36	set_location_assignment PIN_8 -to mreq_n
		37	set_location_assignment PIN_9 -to nmi_n
		38	set_location_assignment PIN_10 -to int_n
		39	set_location_assignment PIN_11 -to d[7]
		40	set_location_assignment PIN_12 -to d[6]
		41	set_location_assignment PIN_13 -to d[5]
		42	set_location_assignment PIN_14 -to d[4]
		43	set_location_assignment PIN_15 -to d[3]
		44	set_location_assignment PIN_16 -to d[2]
		45	set_location_assignment PIN_17 -to d[1]
		46	set_location_assignment PIN_18 -to d[0]
		47	set_location_assignment PIN_19 -to a[15]
		48	set_location_assignment PIN_24 -to a[14]
		49	set_location_assignment PIN_25 -to a[13]
		50	set_location_assignment PIN_26 -to a[12]
		51	set_location_assignment PIN_27 -to a[11]
		52	set_location_assignment PIN_28 -to a[10]
		53	set_location_assignment PIN_29 -to a[9]
		54	set_location_assignment PIN_30 -to a[8]
		55	set_location_assignment PIN_31 -to a[7]
		56	set_location_assignment PIN_36 -to a[6]
		57	set_location_assignment PIN_37 -to a[5]
		58	set_location_assignment PIN_38 -to a[4]
		59	set_location_assignment PIN_39 -to a[3]
		60	set_location_assignment PIN_40 -to a[2]
		61	set_location_assignment PIN_41 -to a[1]
		62	set_location_assignment PIN_44 -to a[0]
		63	set_location_assignment PIN_45 -to vg_cs_n
		64	set_location_assignment PIN_46 -to step
		65	set_location_assignment PIN_47 -to vg_sl
		66	set_location_assignment PIN_53 -to vg_sr
		67	set_location_assignment PIN_54 -to vg_res_n
		68	set_location_assignment PIN_55 -to vg_hrdy
		69	set_location_assignment PIN_56 -to vg_clk
		70	set_location_assignment PIN_57 -to vg_rclk
		71	set_location_assignment PIN_58 -to vg_rawr
		72	set_location_assignment PIN_60 -to vg_tr43
		73	set_location_assignment PIN_61 -to vg_wd
		74	set_location_assignment PIN_62 -to vg_wf_de
		75	set_location_assignment PIN_63 -to vg_drq
		76	set_location_assignment PIN_64 -to vg_irq
		77	set_location_assignment PIN_65 -to vg_side
		78	set_location_assignment PIN_67 -to vg_wrd
		79	set_location_assignment PIN_68 -to rdat_b_n
		80	set_location_assignment PIN_69 -to vg_a[0]
		81	set_location_assignment PIN_70 -to vg_a[1]
		82	set_location_assignment PIN_71 -to ide_d[8]
		83	set_location_assignment PIN_73 -to ide_d[7]
		84	set_location_assignment PIN_74 -to ide_d[9]
		85	set_location_assignment PIN_75 -to ide_d[6]
		86	set_location_assignment PIN_78 -to iorqge1
		87	set_location_assignment PIN_79 -to clkz_in
		88	set_location_assignment PIN_80 -to iorqge2
		89	set_location_assignment PIN_83 -to ide_d[10]
		90	set_location_assignment PIN_85 -to ide_d[5]
		91	set_location_assignment PIN_86 -to ide_d[11]
		92	set_location_assignment PIN_87 -to ide_d[4]
		93	set_location_assignment PIN_88 -to ide_d[12]
		94	set_location_assignment PIN_89 -to ide_d[3]
		95	set_location_assignment PIN_92 -to ide_d[2]
		96	set_location_assignment PIN_93 -to ide_d[14]
		97	set_location_assignment PIN_94 -to ide_d[1]
		98	set_location_assignment PIN_95 -to ide_d[15]
		99	set_location_assignment PIN_96 -to ide_d[0]
		100	set_location_assignment PIN_97 -to ide_dir
		101	set_location_assignment PIN_99 -to ide_rdy
		102	set_location_assignment PIN_100 -to ide_wr_n
		103	set_location_assignment PIN_101 -to ide_rd_n
		104	set_location_assignment PIN_102 -to ide_rs_n
		105	set_location_assignment PIN_103 -to ide_a[1]
		106	set_location_assignment PIN_104 -to ide_a[0]
		107	set_location_assignment PIN_111 -to ide_a[2]
		108	set_location_assignment PIN_112 -to ide_cs1_n
		109	set_location_assignment PIN_113 -to ide_cs0_n
		110	set_location_assignment PIN_114 -to sdclk
		111	set_location_assignment PIN_115 -to sddi
		112	set_location_assignment PIN_116 -to sddo
		113	set_location_assignment PIN_119 -to sdcs_n
		114	set_location_assignment PIN_120 -to vvsync
		115	set_location_assignment PIN_121 -to vhsync
		116	set_location_assignment PIN_122 -to vcsync
		117	set_location_assignment PIN_125 -to vblu[0]
		118	set_location_assignment PIN_126 -to vblu[1]
		119	set_location_assignment PIN_127 -to vgrn[0]
		120	set_location_assignment PIN_128 -to vgrn[1]
		121	set_location_assignment PIN_131 -to vred[0]
		122	set_location_assignment PIN_132 -to vred[1]
		123	set_location_assignment PIN_133 -to beep
		124	set_location_assignment PIN_134 -to ay_clk
		125	set_location_assignment PIN_135 -to ay_bdir
		126	set_location_assignment PIN_136 -to ay_bc1
		127	set_location_assignment PIN_139 -to clkz_out
		128	set_location_assignment PIN_140 -to wr_n
		129	set_location_assignment PIN_141 -to rd_n
		130	set_location_assignment PIN_142 -to res
		131	set_location_assignment PIN_143 -to wait_n
		132	set_location_assignment PIN_144 -to m1_n
		133	set_location_assignment PIN_147 -to rfsh_n
		134	set_location_assignment PIN_148 -to iorq1_n
		135	set_location_assignment PIN_149 -to iorq2_n
		136	set_location_assignment PIN_150 -to csrom
		137	set_location_assignment PIN_157 -to spido
		138	set_location_assignment PIN_158 -to spidi
		139	set_location_assignment PIN_159 -to spiint_n
		140	set_location_assignment PIN_160 -to dos_n
		141	set_location_assignment PIN_161 -to rompg0_n
		142	set_location_assignment PIN_162 -to rompg4
		143	set_location_assignment PIN_163 -to rompg3
		144	set_location_assignment PIN_164 -to rompg2
		145	set_location_assignment PIN_166 -to romwe_n
		146	set_location_assignment PIN_167 -to romoe_n
		147	set_location_assignment PIN_168 -to rras1_n
		148	set_location_assignment PIN_169 -to ra[4]
		149	set_location_assignment PIN_170 -to ra[3]
		150	set_location_assignment PIN_172 -to ra[5]
		151	set_location_assignment PIN_173 -to ra[2]
		152	set_location_assignment PIN_174 -to ra[6]
		153	set_location_assignment PIN_175 -to ra[1]
		154	set_location_assignment PIN_176 -to ra[7]
		155	set_location_assignment PIN_177 -to ra[0]
		156	set_location_assignment PIN_179 -to ra[8]
		157	set_location_assignment PIN_180 -to ra[9]
		158	set_location_assignment PIN_182 -to spics_n
		159	set_location_assignment PIN_183 -to fclk
		160	set_location_assignment PIN_184 -to spick
		161	set_location_assignment PIN_186 -to rucas_n
		162	set_location_assignment PIN_187 -to rwe_n
		163	set_location_assignment PIN_189 -to rlcas_n
		164	set_location_assignment PIN_190 -to rras0_n
		165	set_location_assignment PIN_191 -to rd[8]
		166	set_location_assignment PIN_192 -to rd[7]
		167	set_location_assignment PIN_193 -to rd[9]
		168	set_location_assignment PIN_195 -to rd[6]
		169	set_location_assignment PIN_196 -to rd[10]
		170	set_location_assignment PIN_197 -to rd[5]
		171	set_location_assignment PIN_198 -to rd[11]
		172	set_location_assignment PIN_199 -to rd[4]
		173	set_location_assignment PIN_200 -to rd[12]
		174	set_location_assignment PIN_202 -to rd[3]
		175	set_location_assignment PIN_203 -to rd[13]
		176	set_location_assignment PIN_204 -to rd[2]
		177	set_location_assignment PIN_205 -to rd[14]
		178	set_location_assignment PIN_206 -to rd[1]
		179	set_location_assignment PIN_207 -to rd[15]
		180	set_location_assignment PIN_208 -to rd[0]
		181	set_location_assignment PIN_90 -to ide_d[13]
		182	set_instance_assignment -name CLOCK_SETTINGS "FPGA clock" -to fclk
		183	set_instance_assignment -name FAST_OUTPUT_REGISTER OFF -to clkz_out
		184	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rras0_n
		185	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rras1_n
		186	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rucas_n
		187	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rlcas_n
		188	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to rwe_n
		189	set_instance_assignment -name GLOBAL_SIGNAL ON -to fclk
		190	set_instance_assignment -name GLOBAL_SIGNAL ON -to clkz_in
		191	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to vred
		192	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to vgrn
		193	set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to vblu
		194	set_instance_assignment -name GLOBAL_SIGNAL ON -to spick
		195	set_instance_assignment -name GLOBAL_SIGNAL ON -to spics_n
		196	set_instance_assignment -name CUT ON -from rddata -to zd_out
		197	set_instance_assignment -name CLOCK_SETTINGS "Z80 clock" -to clkz_in
		198	set_instance_assignment -name CLOCK_SETTINGS "SPI clock" -to spick
		199	set_global_assignment -name FMAX_REQUIREMENT "28 MHz" -section_id "FPGA clock"
		200	set_global_assignment -name FMAX_REQUIREMENT "5.5296 MHz" -section_id "SPI clock"
		201	set_global_assignment -name BASED_ON_CLOCK_SETTINGS "FPGA clock" -section_id "Z80 clock"
		202	set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 2 -section_id "Z80 clock"
41	lvd	203	set_global_assignment -name OFFSET_FROM_BASE_CLOCK "-8 ns" -section_id "Z80 clock"
4	lvd	204	set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
		205	set_global_assignment -name GENERATE_RBF_FILE ON
		206	set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
		207	set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
		208	set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD LVTTL/LVCMOS
		209	set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
67	lvd	210	set_global_assignment -name MESSAGE_SUPPRESSION_RULE_FILE top.srf
287	ddp	211	set_global_assignment -name SMART_RECOMPILE OFF
425	lvd	212	set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
		213	set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
360	lvd	214	set_global_assignment -name VERILOG_FILE ../sound/sound.v
340	lvd	215	set_global_assignment -name VERILOG_FILE ../video/video_fontrom.v
		216	set_global_assignment -name VERILOG_FILE ../video/video_vga_sync_h.v
		217	set_global_assignment -name VERILOG_FILE ../video/video_addrgen.v
		218	set_global_assignment -name VERILOG_FILE ../video/video_fetch.v
		219	set_global_assignment -name VERILOG_FILE ../video/video_modedecode.v
		220	set_global_assignment -name VERILOG_FILE ../video/video_outmux.v
		221	set_global_assignment -name VERILOG_FILE ../video/video_palframe.v
		222	set_global_assignment -name VERILOG_FILE ../video/video_render.v
		223	set_global_assignment -name VERILOG_FILE ../video/video_sync_h.v
		224	set_global_assignment -name VERILOG_FILE ../video/video_sync_v.v
		225	set_global_assignment -name VERILOG_FILE ../video/video_top.v
		226	set_global_assignment -name VERILOG_FILE ../video/video_vga_double.v
200	lvd	227	set_global_assignment -name VERILOG_FILE ../z80/zdos.v
		228	set_global_assignment -name VERILOG_FILE ../mem/atm_pager.v
88	lvd	229	set_global_assignment -name VERILOG_FILE ../z80/zwait.v
67	lvd	230	set_global_assignment -name VERILOG_FILE ../z80/zkbdmus.v
4	lvd	231	set_global_assignment -name VERILOG_FILE ../z80/zports.v
		232	set_global_assignment -name VERILOG_FILE ../z80/zclock.v
		233	set_global_assignment -name VERILOG_FILE ../z80/zint.v
		234	set_global_assignment -name VERILOG_FILE ../z80/zmem.v
		235	set_global_assignment -name VERILOG_FILE ../z80/zbus.v
576	lvd	236	set_global_assignment -name VERILOG_FILE ../z80/znmi.v
		237	set_global_assignment -name VERILOG_FILE ../z80/zbreak.v
4	lvd	238	set_global_assignment -name VERILOG_FILE ../vg93/vg93.v
492	lvd	239	set_global_assignment -name VERILOG_FILE ../vg93/fapch_counter.v
		240	set_global_assignment -name VERILOG_FILE ../vg93/fapch_zek.v
4	lvd	241	set_global_assignment -name VERILOG_FILE ../slave/slavespi.v
		242	set_global_assignment -name VERILOG_FILE ../dram/dram.v
		243	set_global_assignment -name VERILOG_FILE ../dram/arbiter.v
543	lvd	244	set_global_assignment -name VERILOG_FILE ../spihub/spi2.v
		245	set_global_assignment -name VERILOG_FILE ../spihub/spihub.v
4	lvd	246	set_global_assignment -name VERILOG_FILE ../common/resetter.v
343	lvd	247	set_global_assignment -name VERILOG_FILE ../top.v
471	lvd	248	set_global_assignment -name MIF_FILE ../video/r0bat_font.mif
477	lvd	249	set_instance_assignment -name CUT ON -from clkz_in -to fclk
		250	set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
		251	set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
492	lvd	252	set_global_assignment -name SLOW_SLEW_RATE ON

Subversion Repositories pentevo

(root)/fpga/current/quartus/top.qsf – Rev 742