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| Rev | Author | Line No. | Line |
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| 4 | lvd | 1 | -- **** |
| 2 | -- T80(b) core. In an effort to merge and maintain bug fixes .... |
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| 3 | -- |
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| 4 | -- |
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| 5 | -- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle |
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| 6 | -- Ver 300 started tidyup |
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| 7 | -- MikeJ March 2005 |
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| 8 | -- Latest version from www.fpgaarcade.com (original www.opencores.org) |
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| 9 | -- |
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| 10 | -- **** |
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| 11 | -- |
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| 12 | -- Z80 compatible microprocessor core |
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| 13 | -- |
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| 14 | -- Version : 0247 |
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| 15 | -- |
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| 16 | -- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) |
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| 17 | -- |
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| 18 | -- All rights reserved |
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| 19 | -- |
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| 20 | -- Redistribution and use in source and synthezised forms, with or without |
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| 21 | -- modification, are permitted provided that the following conditions are met: |
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| 22 | -- |
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| 23 | -- Redistributions of source code must retain the above copyright notice, |
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| 24 | -- this list of conditions and the following disclaimer. |
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| 25 | -- |
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| 26 | -- Redistributions in synthesized form must reproduce the above copyright |
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| 27 | -- notice, this list of conditions and the following disclaimer in the |
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| 28 | -- documentation and/or other materials provided with the distribution. |
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| 29 | -- |
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| 30 | -- Neither the name of the author nor the names of other contributors may |
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| 31 | -- be used to endorse or promote products derived from this software without |
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| 32 | -- specific prior written permission. |
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| 33 | -- |
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| 34 | -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 35 | -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
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| 36 | -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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| 37 | -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE |
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| 38 | -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 39 | -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 40 | -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 41 | -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 42 | -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 43 | -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 44 | -- POSSIBILITY OF SUCH DAMAGE. |
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| 45 | -- |
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| 46 | -- Please report bugs to the author, but before you do so, please |
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| 47 | -- make sure that this is not a derivative work and that |
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| 48 | -- you have the latest version of this file. |
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| 49 | -- |
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| 50 | -- The latest version of this file can be found at: |
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| 51 | -- http://www.opencores.org/cvsweb.shtml/t80/ |
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| 52 | -- |
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| 53 | -- Limitations : |
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| 54 | -- |
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| 55 | -- File history : |
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| 56 | -- |
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| 57 | -- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test |
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| 58 | -- |
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| 59 | -- 0238 : Fixed zero flag for 16 bit SBC and ADC |
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| 60 | -- |
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| 61 | -- 0240 : Added GB operations |
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| 62 | -- |
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| 63 | -- 0242 : Cleanup |
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| 64 | -- |
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| 65 | -- 0247 : Cleanup |
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| 66 | -- |
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| 67 | |||
| 68 | library IEEE; |
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| 69 | use IEEE.std_logic_1164.all; |
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| 70 | use IEEE.numeric_std.all; |
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| 71 | |||
| 72 | entity T80_ALU is |
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| 73 | generic( |
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| 74 | Mode : integer := 0; |
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| 75 | Flag_C : integer := 0; |
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| 76 | Flag_N : integer := 1; |
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| 77 | Flag_P : integer := 2; |
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| 78 | Flag_X : integer := 3; |
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| 79 | Flag_H : integer := 4; |
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| 80 | Flag_Y : integer := 5; |
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| 81 | Flag_Z : integer := 6; |
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| 82 | Flag_S : integer := 7 |
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| 83 | ); |
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| 84 | port( |
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| 85 | Arith16 : in std_logic; |
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| 86 | Z16 : in std_logic; |
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| 87 | ALU_Op : in std_logic_vector(3 downto 0); |
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| 88 | IR : in std_logic_vector(5 downto 0); |
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| 89 | ISet : in std_logic_vector(1 downto 0); |
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| 90 | BusA : in std_logic_vector(7 downto 0); |
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| 91 | BusB : in std_logic_vector(7 downto 0); |
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| 92 | F_In : in std_logic_vector(7 downto 0); |
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| 93 | Q : out std_logic_vector(7 downto 0); |
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| 94 | F_Out : out std_logic_vector(7 downto 0) |
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| 95 | ); |
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| 96 | end T80_ALU; |
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| 97 | |||
| 98 | architecture rtl of T80_ALU is |
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| 99 | |||
| 100 | procedure AddSub(A : std_logic_vector; |
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| 101 | B : std_logic_vector; |
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| 102 | Sub : std_logic; |
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| 103 | Carry_In : std_logic; |
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| 104 | signal Res : out std_logic_vector; |
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| 105 | signal Carry : out std_logic) is |
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| 106 | |||
| 107 | variable B_i : unsigned(A'length - 1 downto 0); |
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| 108 | variable Res_i : unsigned(A'length + 1 downto 0); |
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| 109 | begin |
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| 110 | if Sub = '1' then |
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| 111 | B_i := not unsigned(B); |
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| 112 | else |
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| 113 | B_i := unsigned(B); |
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| 114 | end if; |
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| 115 | |||
| 116 | Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); |
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| 117 | Carry <= Res_i(A'length + 1); |
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| 118 | Res <= std_logic_vector(Res_i(A'length downto 1)); |
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| 119 | end; |
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| 120 | |||
| 121 | -- AddSub variables (temporary signals) |
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| 122 | signal UseCarry : std_logic; |
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| 123 | signal Carry7_v : std_logic; |
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| 124 | signal Overflow_v : std_logic; |
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| 125 | signal HalfCarry_v : std_logic; |
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| 126 | signal Carry_v : std_logic; |
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| 127 | signal Q_v : std_logic_vector(7 downto 0); |
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| 128 | |||
| 129 | signal BitMask : std_logic_vector(7 downto 0); |
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| 130 | |||
| 131 | begin |
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| 132 | |||
| 133 | with IR(5 downto 3) select BitMask <= "00000001" when "000", |
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| 134 | "00000010" when "001", |
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| 135 | "00000100" when "010", |
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| 136 | "00001000" when "011", |
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| 137 | "00010000" when "100", |
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| 138 | "00100000" when "101", |
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| 139 | "01000000" when "110", |
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| 140 | "10000000" when others; |
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| 141 | |||
| 142 | UseCarry <= not ALU_Op(2) and ALU_Op(0); |
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| 143 | AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); |
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| 144 | AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); |
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| 145 | AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); |
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| 146 | |||
| 147 | -- bug fix - parity flag is just parity for 8080, also overflow for Z80 |
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| 148 | process (Carry_v, Carry7_v, Q_v) |
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| 149 | begin |
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| 150 | if(Mode=2) then |
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| 151 | OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor |
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| 152 | Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else |
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| 153 | OverFlow_v <= Carry_v xor Carry7_v; |
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| 154 | end if; |
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| 155 | end process; |
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| 156 | |||
| 157 | process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) |
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| 158 | variable Q_t : std_logic_vector(7 downto 0); |
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| 159 | variable DAA_Q : unsigned(8 downto 0); |
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| 160 | begin |
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| 161 | Q_t := "--------"; |
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| 162 | F_Out <= F_In; |
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| 163 | DAA_Q := "---------"; |
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| 164 | case ALU_Op is |
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| 165 | when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => |
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| 166 | F_Out(Flag_N) <= '0'; |
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| 167 | F_Out(Flag_C) <= '0'; |
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| 168 | case ALU_OP(2 downto 0) is |
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| 169 | when "000" | "001" => -- ADD, ADC |
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| 170 | Q_t := Q_v; |
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| 171 | F_Out(Flag_C) <= Carry_v; |
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| 172 | F_Out(Flag_H) <= HalfCarry_v; |
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| 173 | F_Out(Flag_P) <= OverFlow_v; |
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| 174 | when "010" | "011" | "111" => -- SUB, SBC, CP |
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| 175 | Q_t := Q_v; |
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| 176 | F_Out(Flag_N) <= '1'; |
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| 177 | F_Out(Flag_C) <= not Carry_v; |
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| 178 | F_Out(Flag_H) <= not HalfCarry_v; |
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| 179 | F_Out(Flag_P) <= OverFlow_v; |
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| 180 | when "100" => -- AND |
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| 181 | Q_t(7 downto 0) := BusA and BusB; |
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| 182 | F_Out(Flag_H) <= '1'; |
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| 183 | when "101" => -- XOR |
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| 184 | Q_t(7 downto 0) := BusA xor BusB; |
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| 185 | F_Out(Flag_H) <= '0'; |
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| 186 | when others => -- OR "110" |
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| 187 | Q_t(7 downto 0) := BusA or BusB; |
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| 188 | F_Out(Flag_H) <= '0'; |
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| 189 | end case; |
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| 190 | if ALU_Op(2 downto 0) = "111" then -- CP |
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| 191 | F_Out(Flag_X) <= BusB(3); |
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| 192 | F_Out(Flag_Y) <= BusB(5); |
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| 193 | else |
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| 194 | F_Out(Flag_X) <= Q_t(3); |
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| 195 | F_Out(Flag_Y) <= Q_t(5); |
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| 196 | end if; |
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| 197 | if Q_t(7 downto 0) = "00000000" then |
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| 198 | F_Out(Flag_Z) <= '1'; |
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| 199 | if Z16 = '1' then |
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| 200 | F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC |
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| 201 | end if; |
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| 202 | else |
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| 203 | F_Out(Flag_Z) <= '0'; |
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| 204 | end if; |
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| 205 | F_Out(Flag_S) <= Q_t(7); |
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| 206 | case ALU_Op(2 downto 0) is |
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| 207 | when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP |
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| 208 | when others => |
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| 209 | F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor |
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| 210 | Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); |
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| 211 | end case; |
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| 212 | if Arith16 = '1' then |
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| 213 | F_Out(Flag_S) <= F_In(Flag_S); |
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| 214 | F_Out(Flag_Z) <= F_In(Flag_Z); |
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| 215 | F_Out(Flag_P) <= F_In(Flag_P); |
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| 216 | end if; |
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| 217 | when "1100" => |
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| 218 | -- DAA |
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| 219 | F_Out(Flag_H) <= F_In(Flag_H); |
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| 220 | F_Out(Flag_C) <= F_In(Flag_C); |
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| 221 | DAA_Q(7 downto 0) := unsigned(BusA); |
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| 222 | DAA_Q(8) := '0'; |
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| 223 | if F_In(Flag_N) = '0' then |
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| 224 | -- After addition |
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| 225 | -- Alow > 9 or H = 1 |
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| 226 | if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then |
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| 227 | if (DAA_Q(3 downto 0) > 9) then |
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| 228 | F_Out(Flag_H) <= '1'; |
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| 229 | else |
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| 230 | F_Out(Flag_H) <= '0'; |
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| 231 | end if; |
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| 232 | DAA_Q := DAA_Q + 6; |
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| 233 | end if; |
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| 234 | -- new Ahigh > 9 or C = 1 |
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| 235 | if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then |
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| 236 | DAA_Q := DAA_Q + 96; -- 0x60 |
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| 237 | end if; |
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| 238 | else |
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| 239 | -- After subtraction |
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| 240 | if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then |
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| 241 | if DAA_Q(3 downto 0) > 5 then |
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| 242 | F_Out(Flag_H) <= '0'; |
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| 243 | end if; |
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| 244 | DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; |
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| 245 | end if; |
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| 246 | if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then |
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| 247 | DAA_Q := DAA_Q - 352; -- 0x160 |
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| 248 | end if; |
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| 249 | end if; |
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| 250 | F_Out(Flag_X) <= DAA_Q(3); |
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| 251 | F_Out(Flag_Y) <= DAA_Q(5); |
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| 252 | F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); |
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| 253 | Q_t := std_logic_vector(DAA_Q(7 downto 0)); |
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| 254 | if DAA_Q(7 downto 0) = "00000000" then |
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| 255 | F_Out(Flag_Z) <= '1'; |
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| 256 | else |
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| 257 | F_Out(Flag_Z) <= '0'; |
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| 258 | end if; |
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| 259 | F_Out(Flag_S) <= DAA_Q(7); |
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| 260 | F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor |
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| 261 | DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); |
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| 262 | when "1101" | "1110" => |
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| 263 | -- RLD, RRD |
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| 264 | Q_t(7 downto 4) := BusA(7 downto 4); |
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| 265 | if ALU_Op(0) = '1' then |
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| 266 | Q_t(3 downto 0) := BusB(7 downto 4); |
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| 267 | else |
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| 268 | Q_t(3 downto 0) := BusB(3 downto 0); |
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| 269 | end if; |
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| 270 | F_Out(Flag_H) <= '0'; |
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| 271 | F_Out(Flag_N) <= '0'; |
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| 272 | F_Out(Flag_X) <= Q_t(3); |
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| 273 | F_Out(Flag_Y) <= Q_t(5); |
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| 274 | if Q_t(7 downto 0) = "00000000" then |
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| 275 | F_Out(Flag_Z) <= '1'; |
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| 276 | else |
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| 277 | F_Out(Flag_Z) <= '0'; |
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| 278 | end if; |
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| 279 | F_Out(Flag_S) <= Q_t(7); |
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| 280 | F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor |
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| 281 | Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); |
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| 282 | when "1001" => |
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| 283 | -- BIT |
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| 284 | Q_t(7 downto 0) := BusB and BitMask; |
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| 285 | F_Out(Flag_S) <= Q_t(7); |
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| 286 | if Q_t(7 downto 0) = "00000000" then |
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| 287 | F_Out(Flag_Z) <= '1'; |
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| 288 | F_Out(Flag_P) <= '1'; |
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| 289 | else |
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| 290 | F_Out(Flag_Z) <= '0'; |
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| 291 | F_Out(Flag_P) <= '0'; |
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| 292 | end if; |
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| 293 | F_Out(Flag_H) <= '1'; |
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| 294 | F_Out(Flag_N) <= '0'; |
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| 295 | F_Out(Flag_X) <= '0'; |
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| 296 | F_Out(Flag_Y) <= '0'; |
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| 297 | if IR(2 downto 0) /= "110" then |
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| 298 | F_Out(Flag_X) <= BusB(3); |
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| 299 | F_Out(Flag_Y) <= BusB(5); |
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| 300 | end if; |
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| 301 | when "1010" => |
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| 302 | -- SET |
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| 303 | Q_t(7 downto 0) := BusB or BitMask; |
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| 304 | when "1011" => |
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| 305 | -- RES |
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| 306 | Q_t(7 downto 0) := BusB and not BitMask; |
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| 307 | when "1000" => |
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| 308 | -- ROT |
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| 309 | case IR(5 downto 3) is |
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| 310 | when "000" => -- RLC |
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| 311 | Q_t(7 downto 1) := BusA(6 downto 0); |
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| 312 | Q_t(0) := BusA(7); |
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| 313 | F_Out(Flag_C) <= BusA(7); |
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| 314 | when "010" => -- RL |
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| 315 | Q_t(7 downto 1) := BusA(6 downto 0); |
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| 316 | Q_t(0) := F_In(Flag_C); |
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| 317 | F_Out(Flag_C) <= BusA(7); |
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| 318 | when "001" => -- RRC |
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| 319 | Q_t(6 downto 0) := BusA(7 downto 1); |
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| 320 | Q_t(7) := BusA(0); |
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| 321 | F_Out(Flag_C) <= BusA(0); |
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| 322 | when "011" => -- RR |
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| 323 | Q_t(6 downto 0) := BusA(7 downto 1); |
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| 324 | Q_t(7) := F_In(Flag_C); |
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| 325 | F_Out(Flag_C) <= BusA(0); |
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| 326 | when "100" => -- SLA |
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| 327 | Q_t(7 downto 1) := BusA(6 downto 0); |
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| 328 | Q_t(0) := '0'; |
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| 329 | F_Out(Flag_C) <= BusA(7); |
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| 330 | when "110" => -- SLL (Undocumented) / SWAP |
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| 331 | if Mode = 3 then |
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| 332 | Q_t(7 downto 4) := BusA(3 downto 0); |
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| 333 | Q_t(3 downto 0) := BusA(7 downto 4); |
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| 334 | F_Out(Flag_C) <= '0'; |
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| 335 | else |
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| 336 | Q_t(7 downto 1) := BusA(6 downto 0); |
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| 337 | Q_t(0) := '1'; |
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| 338 | F_Out(Flag_C) <= BusA(7); |
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| 339 | end if; |
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| 340 | when "101" => -- SRA |
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| 341 | Q_t(6 downto 0) := BusA(7 downto 1); |
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| 342 | Q_t(7) := BusA(7); |
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| 343 | F_Out(Flag_C) <= BusA(0); |
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| 344 | when others => -- SRL |
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| 345 | Q_t(6 downto 0) := BusA(7 downto 1); |
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| 346 | Q_t(7) := '0'; |
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| 347 | F_Out(Flag_C) <= BusA(0); |
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| 348 | end case; |
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| 349 | F_Out(Flag_H) <= '0'; |
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| 350 | F_Out(Flag_N) <= '0'; |
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| 351 | F_Out(Flag_X) <= Q_t(3); |
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| 352 | F_Out(Flag_Y) <= Q_t(5); |
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| 353 | F_Out(Flag_S) <= Q_t(7); |
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| 354 | if Q_t(7 downto 0) = "00000000" then |
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| 355 | F_Out(Flag_Z) <= '1'; |
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| 356 | else |
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| 357 | F_Out(Flag_Z) <= '0'; |
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| 358 | end if; |
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| 359 | F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor |
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| 360 | Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); |
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| 361 | if ISet = "00" then |
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| 362 | F_Out(Flag_P) <= F_In(Flag_P); |
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| 363 | F_Out(Flag_S) <= F_In(Flag_S); |
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| 364 | F_Out(Flag_Z) <= F_In(Flag_Z); |
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| 365 | end if; |
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| 366 | when others => |
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| 367 | null; |
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| 368 | end case; |
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| 369 | Q <= Q_t; |
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| 370 | end process; |
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| 371 | end; |