WebSVN – ngs – Blame – /fpga/current/tb/z80/T80a.vhd

Rev	Author	Line No.	Line
89	lvd	1	-- ****
		2	-- T80(b) core. In an effort to merge and maintain bug fixes ....
		3	--
		4	--
		5	-- Ver 300 started tidyup
		6	-- MikeJ March 2005
		7	-- Latest version from www.fpgaarcade.com (original www.opencores.org)
		8	--
		9	-- ****
		10	--
		11	-- Z80 compatible microprocessor core, asynchronous top level
		12	--
		13	-- Version : 0247
		14	--
		15	-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
		16	--
		17	-- All rights reserved
		18	--
		19	-- Redistribution and use in source and synthezised forms, with or without
		20	-- modification, are permitted provided that the following conditions are met:
		21	--
		22	-- Redistributions of source code must retain the above copyright notice,
		23	-- this list of conditions and the following disclaimer.
		24	--
		25	-- Redistributions in synthesized form must reproduce the above copyright
		26	-- notice, this list of conditions and the following disclaimer in the
		27	-- documentation and/or other materials provided with the distribution.
		28	--
		29	-- Neither the name of the author nor the names of other contributors may
		30	-- be used to endorse or promote products derived from this software without
		31	-- specific prior written permission.
		32	--
		33	-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
		34	-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
		35	-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
		36	-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
		37	-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
		38	-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
		39	-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
		40	-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
		41	-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
		42	-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
		43	-- POSSIBILITY OF SUCH DAMAGE.
		44	--
		45	-- Please report bugs to the author, but before you do so, please
		46	-- make sure that this is not a derivative work and that
		47	-- you have the latest version of this file.
		48	--
		49	-- The latest version of this file can be found at:
		50	-- http://www.opencores.org/cvsweb.shtml/t80/
		51	--
		52	-- Limitations :
		53	--
		54	-- File history :
		55	--
		56	-- 0208 : First complete release
		57	--
		58	-- 0211 : Fixed interrupt cycle
		59	--
		60	-- 0235 : Updated for T80 interface change
		61	--
		62	-- 0238 : Updated for T80 interface change
		63	--
		64	-- 0240 : Updated for T80 interface change
		65	--
		66	-- 0242 : Updated for T80 interface change
		67	--
		68	-- 0247 : Fixed bus req/ack cycle
		69	--
		70
		71	library IEEE;
		72	use IEEE.std_logic_1164.all;
		73	use IEEE.numeric_std.all;
		74	use work.T80_Pack.all;
		75
		76	entity T80a is
		77	generic(
		78	Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
		79	);
		80	port(
		81	RESET_n : in std_logic;
		82	CLK_n : in std_logic;
		83	WAIT_n : in std_logic;
		84	INT_n : in std_logic;
		85	NMI_n : in std_logic;
		86	BUSRQ_n : in std_logic;
		87	M1_n : out std_logic;
		88	MREQ_n : out std_logic;
		89	IORQ_n : out std_logic;
		90	RD_n : out std_logic;
		91	WR_n : out std_logic;
		92	RFSH_n : out std_logic;
		93	HALT_n : out std_logic;
		94	BUSAK_n : out std_logic;
		95	A : out std_logic_vector(15 downto 0);
		96	D : inout std_logic_vector(7 downto 0);
		97	D_I : in std_logic_vector(7 downto 0);
		98	D_O : out std_logic_vector(7 downto 0)
		99
		100	);
		101	end T80a;
		102
		103	architecture rtl of T80a is
		104
		105	signal CEN : std_logic;
		106	signal Reset_s : std_logic;
		107	signal IntCycle_n : std_logic;
		108	signal IORQ : std_logic;
		109	signal NoRead : std_logic;
		110	signal Write : std_logic;
		111	signal MREQ : std_logic;
		112	signal MReq_Inhibit : std_logic;
		113	signal Req_Inhibit : std_logic;
		114	signal RD : std_logic;
		115	signal MREQ_n_i : std_logic;
		116	signal IORQ_n_i : std_logic;
		117	signal RD_n_i : std_logic;
		118	signal WR_n_i : std_logic;
		119	signal RFSH_n_i : std_logic;
		120	signal BUSAK_n_i : std_logic;
		121	signal A_i : std_logic_vector(15 downto 0);
		122	signal DO : std_logic_vector(7 downto 0);
		123	signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
		124	signal Wait_s : std_logic;
		125	signal MCycle : std_logic_vector(2 downto 0);
		126	signal TState : std_logic_vector(2 downto 0);
		127
		128	begin
		129
		130	CEN <= '1';
		131
		132	BUSAK_n <= BUSAK_n_i;
		133	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
		134	RD_n_i <= not RD or Req_Inhibit;
		135
		136	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
		137	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
		138	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
		139	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
		140	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
		141	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
		142	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
		143
		144	D_O <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
		145
		146
		147	process (RESET_n, CLK_n)
		148	begin
		149	if RESET_n = '0' then
		150	Reset_s <= '0';
		151	elsif CLK_n'event and CLK_n = '1' then
		152	Reset_s <= '1';
		153	end if;
		154	end process;
		155
		156	u0 : T80
		157	generic map(
		158	Mode => Mode,
		159	IOWait => 1)
		160	port map(
		161	CEN => CEN,
		162	M1_n => M1_n,
		163	IORQ => IORQ,
		164	NoRead => NoRead,
		165	Write => Write,
		166	RFSH_n => RFSH_n_i,
		167	HALT_n => HALT_n,
		168	WAIT_n => Wait_s,
		169	INT_n => INT_n,
		170	NMI_n => NMI_n,
		171	RESET_n => Reset_s,
		172	BUSRQ_n => BUSRQ_n,
		173	BUSAK_n => BUSAK_n_i,
		174	CLK_n => CLK_n,
		175	A => A_i,
		176	DInst => D_I, -- D -> D_I
		177	DI => DI_Reg,
		178	DO => DO,
		179	MC => MCycle,
		180	TS => TState,
		181	IntCycle_n => IntCycle_n);
		182
		183	process (CLK_n)
		184	begin
		185	if CLK_n'event and CLK_n = '0' then
		186	Wait_s <= WAIT_n;
		187	if TState = "011" and BUSAK_n_i = '1' then
		188	DI_Reg <= to_x01(D_I); -- D -> D_I
		189	end if;
		190	end if;
		191	end process;
		192
		193	process (Reset_s,CLK_n)
		194	begin
		195	if Reset_s = '0' then
		196	WR_n_i <= '1';
		197	elsif CLK_n'event and CLK_n = '1' then
		198	WR_n_i <= '1';
		199	if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
		200	WR_n_i <= not Write;
		201	end if;
		202	end if;
		203	end process;
		204
		205	process (Reset_s,CLK_n)
		206	begin
		207	if Reset_s = '0' then
		208	Req_Inhibit <= '0';
		209	elsif CLK_n'event and CLK_n = '1' then
		210	if MCycle = "001" and TState = "010" then
		211	Req_Inhibit <= '1';
		212	else
		213	Req_Inhibit <= '0';
		214	end if;
		215	end if;
		216	end process;
		217
		218	process (Reset_s,CLK_n)
		219	begin
		220	if Reset_s = '0' then
		221	MReq_Inhibit <= '0';
		222	elsif CLK_n'event and CLK_n = '0' then
		223	if MCycle = "001" and TState = "010" then
		224	MReq_Inhibit <= '1';
		225	else
		226	MReq_Inhibit <= '0';
		227	end if;
		228	end if;
		229	end process;
		230
		231	process(Reset_s,CLK_n)
		232	begin
		233	if Reset_s = '0' then
		234	RD <= '0';
		235	IORQ_n_i <= '1';
		236	MREQ <= '0';
		237	elsif CLK_n'event and CLK_n = '0' then
		238
		239	if MCycle = "001" then
		240	if TState = "001" then
		241	RD <= IntCycle_n;
		242	MREQ <= IntCycle_n;
		243	IORQ_n_i <= IntCycle_n;
		244	end if;
		245	if TState = "011" then
		246	RD <= '0';
		247	IORQ_n_i <= '1';
		248	MREQ <= '1';
		249	end if;
		250	if TState = "100" then
		251	MREQ <= '0';
		252	end if;
		253	else
		254	if TState = "001" and NoRead = '0' then
		255	RD <= not Write;
		256	IORQ_n_i <= not IORQ;
		257	MREQ <= not IORQ;
		258	end if;
		259	if TState = "011" then
		260	RD <= '0';
		261	IORQ_n_i <= '1';
		262	MREQ <= '0';
		263	end if;
		264	end if;
		265	end if;
		266	end process;
		267
		268	end;

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(root)/fpga/current/tb/z80/T80a.vhd – Rev 89