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| Rev | Author | Line No. | Line |
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| 92 | lvd | 1 | // |
| 2 | // TV80 8-Bit Microprocessor Core |
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| 3 | // Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org) |
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| 4 | // |
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| 5 | // Copyright (c) 2004,2007 Guy Hutchison (ghutchis@opencores.org) |
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| 6 | // |
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| 7 | // Permission is hereby granted, free of charge, to any person obtaining a |
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| 8 | // copy of this software and associated documentation files (the "Software"), |
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| 9 | // to deal in the Software without restriction, including without limitation |
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| 10 | // the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 11 | // and/or sell copies of the Software, and to permit persons to whom the |
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| 12 | // Software is furnished to do so, subject to the following conditions: |
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| 13 | // |
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| 14 | // The above copyright notice and this permission notice shall be included |
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| 15 | // in all copies or substantial portions of the Software. |
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| 16 | // |
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| 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 18 | // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 19 | // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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| 20 | // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
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| 21 | // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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| 22 | // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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| 23 | // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 24 | |||
| 25 | module tv80_mcode |
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| 26 | (/*AUTOARG*/ |
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| 27 | // Outputs |
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| 28 | MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg, |
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| 29 | Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC, |
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| 30 | Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ, |
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| 31 | LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF, |
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| 32 | ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR, |
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| 33 | I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write, |
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| 34 | // Inputs |
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| 35 | IR, ISet, MCycle, F, NMICycle, IntCycle |
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| 36 | ); |
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| 37 | |||
| 38 | parameter Mode = 0; |
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| 39 | parameter Flag_C = 0; |
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| 40 | parameter Flag_N = 1; |
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| 41 | parameter Flag_P = 2; |
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| 42 | parameter Flag_X = 3; |
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| 43 | parameter Flag_H = 4; |
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| 44 | parameter Flag_Y = 5; |
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| 45 | parameter Flag_Z = 6; |
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| 46 | parameter Flag_S = 7; |
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| 47 | |||
| 48 | input [7:0] IR; |
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| 49 | input [1:0] ISet ; |
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| 50 | input [6:0] MCycle ; |
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| 51 | input [7:0] F ; |
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| 52 | input NMICycle ; |
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| 53 | input IntCycle ; |
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| 54 | output [2:0] MCycles ; |
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| 55 | output [2:0] TStates ; |
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| 56 | output [1:0] Prefix ; // None,BC,ED,DD/FD |
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| 57 | output Inc_PC ; |
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| 58 | output Inc_WZ ; |
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| 59 | output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc |
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| 60 | output Read_To_Reg ; |
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| 61 | output Read_To_Acc ; |
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| 62 | output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F |
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| 63 | output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 |
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| 64 | output [3:0] ALU_Op ; |
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| 65 | output Save_ALU ; |
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| 66 | output PreserveC ; |
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| 67 | output Arith16 ; |
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| 68 | output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI |
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| 69 | output IORQ ; |
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| 70 | output Jump ; |
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| 71 | output JumpE ; |
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| 72 | output JumpXY ; |
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| 73 | output Call ; |
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| 74 | output RstP ; |
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| 75 | output LDZ ; |
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| 76 | output LDW ; |
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| 77 | output LDSPHL ; |
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| 78 | output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None |
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| 79 | output ExchangeDH ; |
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| 80 | output ExchangeRp ; |
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| 81 | output ExchangeAF ; |
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| 82 | output ExchangeRS ; |
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| 83 | output I_DJNZ ; |
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| 84 | output I_CPL ; |
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| 85 | output I_CCF ; |
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| 86 | output I_SCF ; |
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| 87 | output I_RETN ; |
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| 88 | output I_BT ; |
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| 89 | output I_BC ; |
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| 90 | output I_BTR ; |
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| 91 | output I_RLD ; |
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| 92 | output I_RRD ; |
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| 93 | output I_INRC ; |
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| 94 | output SetDI ; |
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| 95 | output SetEI ; |
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| 96 | output [1:0] IMode ; |
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| 97 | output Halt ; |
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| 98 | output NoRead ; |
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| 99 | output Write ; |
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| 100 | |||
| 101 | // regs |
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| 102 | reg [2:0] MCycles ; |
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| 103 | reg [2:0] TStates ; |
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| 104 | reg [1:0] Prefix ; // None,BC,ED,DD/FD |
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| 105 | reg Inc_PC ; |
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| 106 | reg Inc_WZ ; |
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| 107 | reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc |
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| 108 | reg Read_To_Reg ; |
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| 109 | reg Read_To_Acc ; |
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| 110 | reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F |
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| 111 | reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 |
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| 112 | reg [3:0] ALU_Op ; |
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| 113 | reg Save_ALU ; |
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| 114 | reg PreserveC ; |
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| 115 | reg Arith16 ; |
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| 116 | reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI |
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| 117 | reg IORQ ; |
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| 118 | reg Jump ; |
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| 119 | reg JumpE ; |
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| 120 | reg JumpXY ; |
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| 121 | reg Call ; |
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| 122 | reg RstP ; |
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| 123 | reg LDZ ; |
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| 124 | reg LDW ; |
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| 125 | reg LDSPHL ; |
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| 126 | reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None |
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| 127 | reg ExchangeDH ; |
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| 128 | reg ExchangeRp ; |
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| 129 | reg ExchangeAF ; |
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| 130 | reg ExchangeRS ; |
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| 131 | reg I_DJNZ ; |
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| 132 | reg I_CPL ; |
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| 133 | reg I_CCF ; |
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| 134 | reg I_SCF ; |
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| 135 | reg I_RETN ; |
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| 136 | reg I_BT ; |
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| 137 | reg I_BC ; |
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| 138 | reg I_BTR ; |
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| 139 | reg I_RLD ; |
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| 140 | reg I_RRD ; |
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| 141 | reg I_INRC ; |
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| 142 | reg SetDI ; |
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| 143 | reg SetEI ; |
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| 144 | reg [1:0] IMode ; |
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| 145 | reg Halt ; |
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| 146 | reg NoRead ; |
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| 147 | reg Write ; |
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| 148 | |||
| 149 | parameter aNone = 3'b111; |
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| 150 | parameter aBC = 3'b000; |
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| 151 | parameter aDE = 3'b001; |
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| 152 | parameter aXY = 3'b010; |
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| 153 | parameter aIOA = 3'b100; |
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| 154 | parameter aSP = 3'b101; |
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| 155 | parameter aZI = 3'b110; |
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| 156 | // constant aNone : std_logic_vector[2:0] = 3'b000; |
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| 157 | // constant aXY : std_logic_vector[2:0] = 3'b001; |
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| 158 | // constant aIOA : std_logic_vector[2:0] = 3'b010; |
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| 159 | // constant aSP : std_logic_vector[2:0] = 3'b011; |
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| 160 | // constant aBC : std_logic_vector[2:0] = 3'b100; |
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| 161 | // constant aDE : std_logic_vector[2:0] = 3'b101; |
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| 162 | // constant aZI : std_logic_vector[2:0] = 3'b110; |
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| 163 | |||
| 164 | function is_cc_true; |
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| 165 | input [7:0] FF; |
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| 166 | input [2:0] cc; |
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| 167 | begin |
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| 168 | if (Mode == 3 ) |
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| 169 | begin |
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| 170 | case (cc) |
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| 171 | 3'b000 : is_cc_true = FF[7] == 1'b0; // NZ |
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| 172 | 3'b001 : is_cc_true = FF[7] == 1'b1; // Z |
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| 173 | 3'b010 : is_cc_true = FF[4] == 1'b0; // NC |
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| 174 | 3'b011 : is_cc_true = FF[4] == 1'b1; // C |
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| 175 | 3'b100 : is_cc_true = 0; |
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| 176 | 3'b101 : is_cc_true = 0; |
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| 177 | 3'b110 : is_cc_true = 0; |
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| 178 | 3'b111 : is_cc_true = 0; |
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| 179 | endcase |
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| 180 | end |
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| 181 | else |
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| 182 | begin |
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| 183 | case (cc) |
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| 184 | 3'b000 : is_cc_true = FF[6] == 1'b0; // NZ |
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| 185 | 3'b001 : is_cc_true = FF[6] == 1'b1; // Z |
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| 186 | 3'b010 : is_cc_true = FF[0] == 1'b0; // NC |
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| 187 | 3'b011 : is_cc_true = FF[0] == 1'b1; // C |
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| 188 | 3'b100 : is_cc_true = FF[2] == 1'b0; // PO |
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| 189 | 3'b101 : is_cc_true = FF[2] == 1'b1; // PE |
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| 190 | 3'b110 : is_cc_true = FF[7] == 1'b0; // P |
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| 191 | 3'b111 : is_cc_true = FF[7] == 1'b1; // M |
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| 192 | endcase |
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| 193 | end |
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| 194 | end |
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| 195 | endfunction // is_cc_true |
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| 196 | |||
| 197 | |||
| 198 | reg [2:0] DDD; |
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| 199 | reg [2:0] SSS; |
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| 200 | reg [1:0] DPAIR; |
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| 201 | |||
| 202 | always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle |
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| 203 | or NMICycle) |
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| 204 | begin |
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| 205 | DDD = IR[5:3]; |
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| 206 | SSS = IR[2:0]; |
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| 207 | DPAIR = IR[5:4]; |
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| 208 | |||
| 209 | MCycles = 3'b001; |
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| 210 | if (MCycle[0] ) |
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| 211 | begin |
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| 212 | TStates = 3'b100; |
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| 213 | end |
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| 214 | else |
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| 215 | begin |
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| 216 | TStates = 3'b011; |
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| 217 | end |
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| 218 | Prefix = 2'b00; |
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| 219 | Inc_PC = 1'b0; |
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| 220 | Inc_WZ = 1'b0; |
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| 221 | IncDec_16 = 4'b0000; |
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| 222 | Read_To_Acc = 1'b0; |
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| 223 | Read_To_Reg = 1'b0; |
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| 224 | Set_BusB_To = 4'b0000; |
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| 225 | Set_BusA_To = 4'b0000; |
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| 226 | ALU_Op = { 1'b0, IR[5:3] }; |
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| 227 | Save_ALU = 1'b0; |
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| 228 | PreserveC = 1'b0; |
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| 229 | Arith16 = 1'b0; |
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| 230 | IORQ = 1'b0; |
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| 231 | Set_Addr_To = aNone; |
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| 232 | Jump = 1'b0; |
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| 233 | JumpE = 1'b0; |
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| 234 | JumpXY = 1'b0; |
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| 235 | Call = 1'b0; |
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| 236 | RstP = 1'b0; |
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| 237 | LDZ = 1'b0; |
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| 238 | LDW = 1'b0; |
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| 239 | LDSPHL = 1'b0; |
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| 240 | Special_LD = 3'b000; |
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| 241 | ExchangeDH = 1'b0; |
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| 242 | ExchangeRp = 1'b0; |
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| 243 | ExchangeAF = 1'b0; |
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| 244 | ExchangeRS = 1'b0; |
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| 245 | I_DJNZ = 1'b0; |
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| 246 | I_CPL = 1'b0; |
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| 247 | I_CCF = 1'b0; |
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| 248 | I_SCF = 1'b0; |
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| 249 | I_RETN = 1'b0; |
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| 250 | I_BT = 1'b0; |
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| 251 | I_BC = 1'b0; |
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| 252 | I_BTR = 1'b0; |
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| 253 | I_RLD = 1'b0; |
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| 254 | I_RRD = 1'b0; |
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| 255 | I_INRC = 1'b0; |
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| 256 | SetDI = 1'b0; |
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| 257 | SetEI = 1'b0; |
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| 258 | IMode = 2'b11; |
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| 259 | Halt = 1'b0; |
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| 260 | NoRead = 1'b0; |
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| 261 | Write = 1'b0; |
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| 262 | |||
| 263 | case (ISet) |
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| 264 | 2'b00 : |
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| 265 | begin |
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| 266 | |||
| 267 | //---------------------------------------------------------------------------- |
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| 268 | // |
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| 269 | // Unprefixed instructions |
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| 270 | // |
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| 271 | //---------------------------------------------------------------------------- |
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| 272 | |||
| 273 | casez (IR) |
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| 274 | // 8 BIT LOAD GROUP |
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| 275 | 8'b01zzzzzz : |
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| 276 | begin |
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| 277 | if (IR[5:0] == 6'b110110) |
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| 278 | Halt = 1'b1; |
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| 279 | else if (IR[2:0] == 3'b110) |
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| 280 | begin |
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| 281 | // LD r,(HL) |
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| 282 | MCycles = 3'b010; |
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| 283 | if (MCycle[0]) |
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| 284 | Set_Addr_To = aXY; |
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| 285 | if (MCycle[1]) |
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| 286 | begin |
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| 287 | Set_BusA_To[2:0] = DDD; |
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| 288 | Read_To_Reg = 1'b1; |
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| 289 | end |
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| 290 | end // if (IR[2:0] == 3'b110) |
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| 291 | else if (IR[5:3] == 3'b110) |
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| 292 | begin |
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| 293 | // LD (HL),r |
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| 294 | MCycles = 3'b010; |
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| 295 | if (MCycle[0]) |
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| 296 | begin |
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| 297 | Set_Addr_To = aXY; |
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| 298 | Set_BusB_To[2:0] = SSS; |
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| 299 | Set_BusB_To[3] = 1'b0; |
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| 300 | end |
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| 301 | if (MCycle[1]) |
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| 302 | Write = 1'b1; |
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| 303 | end // if (IR[5:3] == 3'b110) |
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| 304 | else |
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| 305 | begin |
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| 306 | Set_BusB_To[2:0] = SSS; |
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| 307 | ExchangeRp = 1'b1; |
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| 308 | Set_BusA_To[2:0] = DDD; |
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| 309 | Read_To_Reg = 1'b1; |
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| 310 | end // else: !if(IR[5:3] == 3'b110) |
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| 311 | end // case: 8'b01zzzzzz |
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| 312 | |||
| 313 | 8'b00zzz110 : |
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| 314 | begin |
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| 315 | if (IR[5:3] == 3'b110) |
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| 316 | begin |
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| 317 | // LD (HL),n |
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| 318 | MCycles = 3'b011; |
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| 319 | if (MCycle[1]) |
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| 320 | begin |
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| 321 | Inc_PC = 1'b1; |
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| 322 | Set_Addr_To = aXY; |
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| 323 | Set_BusB_To[2:0] = SSS; |
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| 324 | Set_BusB_To[3] = 1'b0; |
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| 325 | end |
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| 326 | if (MCycle[2]) |
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| 327 | Write = 1'b1; |
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| 328 | end // if (IR[5:3] == 3'b110) |
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| 329 | else |
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| 330 | begin |
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| 331 | // LD r,n |
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| 332 | MCycles = 3'b010; |
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| 333 | if (MCycle[1]) |
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| 334 | begin |
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| 335 | Inc_PC = 1'b1; |
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| 336 | Set_BusA_To[2:0] = DDD; |
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| 337 | Read_To_Reg = 1'b1; |
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| 338 | end |
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| 339 | end |
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| 340 | end |
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| 341 | |||
| 342 | 8'b00001010 : |
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| 343 | begin |
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| 344 | // LD A,(BC) |
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| 345 | MCycles = 3'b010; |
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| 346 | if (MCycle[0]) |
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| 347 | Set_Addr_To = aBC; |
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| 348 | if (MCycle[1]) |
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| 349 | Read_To_Acc = 1'b1; |
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| 350 | end // case: 8'b00001010 |
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| 351 | |||
| 352 | 8'b00011010 : |
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| 353 | begin |
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| 354 | // LD A,(DE) |
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| 355 | MCycles = 3'b010; |
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| 356 | if (MCycle[0]) |
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| 357 | Set_Addr_To = aDE; |
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| 358 | if (MCycle[1]) |
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| 359 | Read_To_Acc = 1'b1; |
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| 360 | end // case: 8'b00011010 |
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| 361 | |||
| 362 | 8'b00111010 : |
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| 363 | begin |
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| 364 | if (Mode == 3 ) |
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| 365 | begin |
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| 366 | // LDD A,(HL) |
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| 367 | MCycles = 3'b010; |
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| 368 | if (MCycle[0]) |
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| 369 | Set_Addr_To = aXY; |
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| 370 | if (MCycle[1]) |
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| 371 | begin |
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| 372 | Read_To_Acc = 1'b1; |
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| 373 | IncDec_16 = 4'b1110; |
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| 374 | end |
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| 375 | end |
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| 376 | else |
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| 377 | begin |
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| 378 | // LD A,(nn) |
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| 379 | MCycles = 3'b100; |
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| 380 | if (MCycle[1]) |
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| 381 | begin |
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| 382 | Inc_PC = 1'b1; |
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| 383 | LDZ = 1'b1; |
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| 384 | end |
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| 385 | if (MCycle[2]) |
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| 386 | begin |
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| 387 | Set_Addr_To = aZI; |
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| 388 | Inc_PC = 1'b1; |
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| 389 | end |
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| 390 | if (MCycle[3]) |
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| 391 | begin |
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| 392 | Read_To_Acc = 1'b1; |
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| 393 | end |
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| 394 | end // else: !if(Mode == 3 ) |
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| 395 | end // case: 8'b00111010 |
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| 396 | |||
| 397 | 8'b00000010 : |
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| 398 | begin |
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| 399 | // LD (BC),A |
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| 400 | MCycles = 3'b010; |
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| 401 | if (MCycle[0]) |
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| 402 | begin |
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| 403 | Set_Addr_To = aBC; |
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| 404 | Set_BusB_To = 4'b0111; |
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| 405 | end |
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| 406 | if (MCycle[1]) |
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| 407 | begin |
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| 408 | Write = 1'b1; |
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| 409 | end |
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| 410 | end // case: 8'b00000010 |
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| 411 | |||
| 412 | 8'b00010010 : |
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| 413 | begin |
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| 414 | // LD (DE),A |
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| 415 | MCycles = 3'b010; |
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| 416 | case (1'b1) // MCycle |
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| 417 | MCycle[0] : |
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| 418 | begin |
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| 419 | Set_Addr_To = aDE; |
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| 420 | Set_BusB_To = 4'b0111; |
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| 421 | end |
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| 422 | MCycle[1] : |
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| 423 | Write = 1'b1; |
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| 424 | default :; |
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| 425 | endcase // case(MCycle) |
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| 426 | end // case: 8'b00010010 |
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| 427 | |||
| 428 | 8'b00110010 : |
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| 429 | begin |
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| 430 | if (Mode == 3 ) |
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| 431 | begin |
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| 432 | // LDD (HL),A |
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| 433 | MCycles = 3'b010; |
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| 434 | case (1'b1) // MCycle |
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| 435 | MCycle[0] : |
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| 436 | begin |
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| 437 | Set_Addr_To = aXY; |
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| 438 | Set_BusB_To = 4'b0111; |
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| 439 | end |
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| 440 | MCycle[1] : |
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| 441 | begin |
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| 442 | Write = 1'b1; |
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| 443 | IncDec_16 = 4'b1110; |
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| 444 | end |
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| 445 | default :; |
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| 446 | endcase // case(MCycle) |
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| 447 | |||
| 448 | end |
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| 449 | else |
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| 450 | begin |
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| 451 | // LD (nn),A |
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| 452 | MCycles = 3'b100; |
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| 453 | case (1'b1) // MCycle |
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| 454 | MCycle[1] : |
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| 455 | begin |
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| 456 | Inc_PC = 1'b1; |
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| 457 | LDZ = 1'b1; |
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| 458 | end |
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| 459 | MCycle[2] : |
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| 460 | begin |
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| 461 | Set_Addr_To = aZI; |
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| 462 | Inc_PC = 1'b1; |
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| 463 | Set_BusB_To = 4'b0111; |
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| 464 | end |
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| 465 | MCycle[3] : |
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| 466 | begin |
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| 467 | Write = 1'b1; |
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| 468 | end |
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| 469 | default :; |
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| 470 | endcase |
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| 471 | end // else: !if(Mode == 3 ) |
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| 472 | end // case: 8'b00110010 |
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| 473 | |||
| 474 | |||
| 475 | // 16 BIT LOAD GROUP |
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| 476 | 8'b00000001,8'b00010001,8'b00100001,8'b00110001 : |
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| 477 | begin |
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| 478 | // LD dd,nn |
||
| 479 | MCycles = 3'b011; |
||
| 480 | case (1'b1) // MCycle |
||
| 481 | MCycle[1] : |
||
| 482 | begin |
||
| 483 | Inc_PC = 1'b1; |
||
| 484 | Read_To_Reg = 1'b1; |
||
| 485 | if (DPAIR == 2'b11 ) |
||
| 486 | begin |
||
| 487 | Set_BusA_To[3:0] = 4'b1000; |
||
| 488 | end |
||
| 489 | else |
||
| 490 | begin |
||
| 491 | Set_BusA_To[2:1] = DPAIR; |
||
| 492 | Set_BusA_To[0] = 1'b1; |
||
| 493 | end |
||
| 494 | end // case: 2 |
||
| 495 | |||
| 496 | MCycle[2] : |
||
| 497 | begin |
||
| 498 | Inc_PC = 1'b1; |
||
| 499 | Read_To_Reg = 1'b1; |
||
| 500 | if (DPAIR == 2'b11 ) |
||
| 501 | begin |
||
| 502 | Set_BusA_To[3:0] = 4'b1001; |
||
| 503 | end |
||
| 504 | else |
||
| 505 | begin |
||
| 506 | Set_BusA_To[2:1] = DPAIR; |
||
| 507 | Set_BusA_To[0] = 1'b0; |
||
| 508 | end |
||
| 509 | end // case: 3 |
||
| 510 | |||
| 511 | default :; |
||
| 512 | endcase // case(MCycle) |
||
| 513 | end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001 |
||
| 514 | |||
| 515 | 8'b00101010 : |
||
| 516 | begin |
||
| 517 | if (Mode == 3 ) |
||
| 518 | begin |
||
| 519 | // LDI A,(HL) |
||
| 520 | MCycles = 3'b010; |
||
| 521 | case (1'b1) // MCycle |
||
| 522 | MCycle[0] : |
||
| 523 | Set_Addr_To = aXY; |
||
| 524 | MCycle[1] : |
||
| 525 | begin |
||
| 526 | Read_To_Acc = 1'b1; |
||
| 527 | IncDec_16 = 4'b0110; |
||
| 528 | end |
||
| 529 | |||
| 530 | default :; |
||
| 531 | endcase |
||
| 532 | end |
||
| 533 | else |
||
| 534 | begin |
||
| 535 | // LD HL,(nn) |
||
| 536 | MCycles = 3'b101; |
||
| 537 | case (1'b1) // MCycle |
||
| 538 | MCycle[1] : |
||
| 539 | begin |
||
| 540 | Inc_PC = 1'b1; |
||
| 541 | LDZ = 1'b1; |
||
| 542 | end |
||
| 543 | MCycle[2] : |
||
| 544 | begin |
||
| 545 | Set_Addr_To = aZI; |
||
| 546 | Inc_PC = 1'b1; |
||
| 547 | LDW = 1'b1; |
||
| 548 | end |
||
| 549 | MCycle[3] : |
||
| 550 | begin |
||
| 551 | Set_BusA_To[2:0] = 3'b101; // L |
||
| 552 | Read_To_Reg = 1'b1; |
||
| 553 | Inc_WZ = 1'b1; |
||
| 554 | Set_Addr_To = aZI; |
||
| 555 | end |
||
| 556 | MCycle[4] : |
||
| 557 | begin |
||
| 558 | Set_BusA_To[2:0] = 3'b100; // H |
||
| 559 | Read_To_Reg = 1'b1; |
||
| 560 | end |
||
| 561 | default :; |
||
| 562 | endcase |
||
| 563 | end // else: !if(Mode == 3 ) |
||
| 564 | end // case: 8'b00101010 |
||
| 565 | |||
| 566 | 8'b00100010 : |
||
| 567 | begin |
||
| 568 | if (Mode == 3 ) |
||
| 569 | begin |
||
| 570 | // LDI (HL),A |
||
| 571 | MCycles = 3'b010; |
||
| 572 | case (1'b1) // MCycle |
||
| 573 | MCycle[0] : |
||
| 574 | begin |
||
| 575 | Set_Addr_To = aXY; |
||
| 576 | Set_BusB_To = 4'b0111; |
||
| 577 | end |
||
| 578 | MCycle[1] : |
||
| 579 | begin |
||
| 580 | Write = 1'b1; |
||
| 581 | IncDec_16 = 4'b0110; |
||
| 582 | end |
||
| 583 | default :; |
||
| 584 | endcase |
||
| 585 | end |
||
| 586 | else |
||
| 587 | begin |
||
| 588 | // LD (nn),HL |
||
| 589 | MCycles = 3'b101; |
||
| 590 | case (1'b1) // MCycle |
||
| 591 | MCycle[1] : |
||
| 592 | begin |
||
| 593 | Inc_PC = 1'b1; |
||
| 594 | LDZ = 1'b1; |
||
| 595 | end |
||
| 596 | |||
| 597 | MCycle[2] : |
||
| 598 | begin |
||
| 599 | Set_Addr_To = aZI; |
||
| 600 | Inc_PC = 1'b1; |
||
| 601 | LDW = 1'b1; |
||
| 602 | Set_BusB_To = 4'b0101; // L |
||
| 603 | end |
||
| 604 | |||
| 605 | MCycle[3] : |
||
| 606 | begin |
||
| 607 | Inc_WZ = 1'b1; |
||
| 608 | Set_Addr_To = aZI; |
||
| 609 | Write = 1'b1; |
||
| 610 | Set_BusB_To = 4'b0100; // H |
||
| 611 | end |
||
| 612 | MCycle[4] : |
||
| 613 | Write = 1'b1; |
||
| 614 | default :; |
||
| 615 | endcase |
||
| 616 | end // else: !if(Mode == 3 ) |
||
| 617 | end // case: 8'b00100010 |
||
| 618 | |||
| 619 | 8'b11111001 : |
||
| 620 | begin |
||
| 621 | // LD SP,HL |
||
| 622 | TStates = 3'b110; |
||
| 623 | LDSPHL = 1'b1; |
||
| 624 | end |
||
| 625 | |||
| 626 | 8'b11zz0101 : |
||
| 627 | begin |
||
| 628 | // PUSH qq |
||
| 629 | MCycles = 3'b011; |
||
| 630 | case (1'b1) // MCycle |
||
| 631 | MCycle[0] : |
||
| 632 | begin |
||
| 633 | TStates = 3'b101; |
||
| 634 | IncDec_16 = 4'b1111; |
||
| 635 | Set_Addr_To = aSP; |
||
| 636 | if (DPAIR == 2'b11 ) |
||
| 637 | begin |
||
| 638 | Set_BusB_To = 4'b0111; |
||
| 639 | end |
||
| 640 | else |
||
| 641 | begin |
||
| 642 | Set_BusB_To[2:1] = DPAIR; |
||
| 643 | Set_BusB_To[0] = 1'b0; |
||
| 644 | Set_BusB_To[3] = 1'b0; |
||
| 645 | end |
||
| 646 | end // case: 1 |
||
| 647 | |||
| 648 | MCycle[1] : |
||
| 649 | begin |
||
| 650 | IncDec_16 = 4'b1111; |
||
| 651 | Set_Addr_To = aSP; |
||
| 652 | if (DPAIR == 2'b11 ) |
||
| 653 | begin |
||
| 654 | Set_BusB_To = 4'b1011; |
||
| 655 | end |
||
| 656 | else |
||
| 657 | begin |
||
| 658 | Set_BusB_To[2:1] = DPAIR; |
||
| 659 | Set_BusB_To[0] = 1'b1; |
||
| 660 | Set_BusB_To[3] = 1'b0; |
||
| 661 | end |
||
| 662 | Write = 1'b1; |
||
| 663 | end // case: 2 |
||
| 664 | |||
| 665 | MCycle[2] : |
||
| 666 | Write = 1'b1; |
||
| 667 | default :; |
||
| 668 | endcase // case(MCycle) |
||
| 669 | end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101 |
||
| 670 | |||
| 671 | 8'b11zz0001 : |
||
| 672 | begin |
||
| 673 | // POP qq |
||
| 674 | MCycles = 3'b011; |
||
| 675 | case (1'b1) // MCycle |
||
| 676 | MCycle[0] : |
||
| 677 | Set_Addr_To = aSP; |
||
| 678 | MCycle[1] : |
||
| 679 | begin |
||
| 680 | IncDec_16 = 4'b0111; |
||
| 681 | Set_Addr_To = aSP; |
||
| 682 | Read_To_Reg = 1'b1; |
||
| 683 | if (DPAIR == 2'b11 ) |
||
| 684 | begin |
||
| 685 | Set_BusA_To[3:0] = 4'b1011; |
||
| 686 | end |
||
| 687 | else |
||
| 688 | begin |
||
| 689 | Set_BusA_To[2:1] = DPAIR; |
||
| 690 | Set_BusA_To[0] = 1'b1; |
||
| 691 | end |
||
| 692 | end // case: 2 |
||
| 693 | |||
| 694 | MCycle[2] : |
||
| 695 | begin |
||
| 696 | IncDec_16 = 4'b0111; |
||
| 697 | Read_To_Reg = 1'b1; |
||
| 698 | if (DPAIR == 2'b11 ) |
||
| 699 | begin |
||
| 700 | Set_BusA_To[3:0] = 4'b0111; |
||
| 701 | end |
||
| 702 | else |
||
| 703 | begin |
||
| 704 | Set_BusA_To[2:1] = DPAIR; |
||
| 705 | Set_BusA_To[0] = 1'b0; |
||
| 706 | end |
||
| 707 | end // case: 3 |
||
| 708 | |||
| 709 | default :; |
||
| 710 | endcase // case(MCycle) |
||
| 711 | end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001 |
||
| 712 | |||
| 713 | |||
| 714 | // EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP |
||
| 715 | 8'b11101011 : |
||
| 716 | begin |
||
| 717 | if (Mode != 3 ) |
||
| 718 | begin |
||
| 719 | // EX DE,HL |
||
| 720 | ExchangeDH = 1'b1; |
||
| 721 | end |
||
| 722 | end |
||
| 723 | |||
| 724 | 8'b00001000 : |
||
| 725 | begin |
||
| 726 | if (Mode == 3 ) |
||
| 727 | begin |
||
| 728 | // LD (nn),SP |
||
| 729 | MCycles = 3'b101; |
||
| 730 | case (1'b1) // MCycle |
||
| 731 | MCycle[1] : |
||
| 732 | begin |
||
| 733 | Inc_PC = 1'b1; |
||
| 734 | LDZ = 1'b1; |
||
| 735 | end |
||
| 736 | |||
| 737 | MCycle[2] : |
||
| 738 | begin |
||
| 739 | Set_Addr_To = aZI; |
||
| 740 | Inc_PC = 1'b1; |
||
| 741 | LDW = 1'b1; |
||
| 742 | Set_BusB_To = 4'b1000; |
||
| 743 | end |
||
| 744 | |||
| 745 | MCycle[3] : |
||
| 746 | begin |
||
| 747 | Inc_WZ = 1'b1; |
||
| 748 | Set_Addr_To = aZI; |
||
| 749 | Write = 1'b1; |
||
| 750 | Set_BusB_To = 4'b1001; |
||
| 751 | end |
||
| 752 | |||
| 753 | MCycle[4] : |
||
| 754 | Write = 1'b1; |
||
| 755 | default :; |
||
| 756 | endcase |
||
| 757 | end |
||
| 758 | else if (Mode < 2 ) |
||
| 759 | begin |
||
| 760 | // EX AF,AF' |
||
| 761 | ExchangeAF = 1'b1; |
||
| 762 | end |
||
| 763 | end // case: 8'b00001000 |
||
| 764 | |||
| 765 | 8'b11011001 : |
||
| 766 | begin |
||
| 767 | if (Mode == 3 ) |
||
| 768 | begin |
||
| 769 | // RETI |
||
| 770 | MCycles = 3'b011; |
||
| 771 | case (1'b1) // MCycle |
||
| 772 | MCycle[0] : |
||
| 773 | Set_Addr_To = aSP; |
||
| 774 | MCycle[1] : |
||
| 775 | begin |
||
| 776 | IncDec_16 = 4'b0111; |
||
| 777 | Set_Addr_To = aSP; |
||
| 778 | LDZ = 1'b1; |
||
| 779 | end |
||
| 780 | |||
| 781 | MCycle[2] : |
||
| 782 | begin |
||
| 783 | Jump = 1'b1; |
||
| 784 | IncDec_16 = 4'b0111; |
||
| 785 | I_RETN = 1'b1; |
||
| 786 | SetEI = 1'b1; |
||
| 787 | end |
||
| 788 | default :; |
||
| 789 | endcase |
||
| 790 | end |
||
| 791 | else if (Mode < 2 ) |
||
| 792 | begin |
||
| 793 | // EXX |
||
| 794 | ExchangeRS = 1'b1; |
||
| 795 | end |
||
| 796 | end // case: 8'b11011001 |
||
| 797 | |||
| 798 | 8'b11100011 : |
||
| 799 | begin |
||
| 800 | if (Mode != 3 ) |
||
| 801 | begin |
||
| 802 | // EX (SP),HL |
||
| 803 | MCycles = 3'b101; |
||
| 804 | case (1'b1) // MCycle |
||
| 805 | MCycle[0] : |
||
| 806 | Set_Addr_To = aSP; |
||
| 807 | MCycle[1] : |
||
| 808 | begin |
||
| 809 | Read_To_Reg = 1'b1; |
||
| 810 | Set_BusA_To = 4'b0101; |
||
| 811 | Set_BusB_To = 4'b0101; |
||
| 812 | Set_Addr_To = aSP; |
||
| 813 | end |
||
| 814 | MCycle[2] : |
||
| 815 | begin |
||
| 816 | IncDec_16 = 4'b0111; |
||
| 817 | Set_Addr_To = aSP; |
||
| 818 | TStates = 3'b100; |
||
| 819 | Write = 1'b1; |
||
| 820 | end |
||
| 821 | MCycle[3] : |
||
| 822 | begin |
||
| 823 | Read_To_Reg = 1'b1; |
||
| 824 | Set_BusA_To = 4'b0100; |
||
| 825 | Set_BusB_To = 4'b0100; |
||
| 826 | Set_Addr_To = aSP; |
||
| 827 | end |
||
| 828 | MCycle[4] : |
||
| 829 | begin |
||
| 830 | IncDec_16 = 4'b1111; |
||
| 831 | TStates = 3'b101; |
||
| 832 | Write = 1'b1; |
||
| 833 | end |
||
| 834 | |||
| 835 | default :; |
||
| 836 | endcase |
||
| 837 | end // if (Mode != 3 ) |
||
| 838 | end // case: 8'b11100011 |
||
| 839 | |||
| 840 | |||
| 841 | // 8 BIT ARITHMETIC AND LOGICAL GROUP |
||
| 842 | 8'b10zzzzzz : |
||
| 843 | begin |
||
| 844 | if (IR[2:0] == 3'b110) |
||
| 845 | begin |
||
| 846 | // ADD A,(HL) |
||
| 847 | // ADC A,(HL) |
||
| 848 | // SUB A,(HL) |
||
| 849 | // SBC A,(HL) |
||
| 850 | // AND A,(HL) |
||
| 851 | // OR A,(HL) |
||
| 852 | // XOR A,(HL) |
||
| 853 | // CP A,(HL) |
||
| 854 | MCycles = 3'b010; |
||
| 855 | case (1'b1) // MCycle |
||
| 856 | MCycle[0] : |
||
| 857 | Set_Addr_To = aXY; |
||
| 858 | MCycle[1] : |
||
| 859 | begin |
||
| 860 | Read_To_Reg = 1'b1; |
||
| 861 | Save_ALU = 1'b1; |
||
| 862 | Set_BusB_To[2:0] = SSS; |
||
| 863 | Set_BusA_To[2:0] = 3'b111; |
||
| 864 | end |
||
| 865 | |||
| 866 | default :; |
||
| 867 | endcase // case(MCycle) |
||
| 868 | end // if (IR[2:0] == 3'b110) |
||
| 869 | else |
||
| 870 | begin |
||
| 871 | // ADD A,r |
||
| 872 | // ADC A,r |
||
| 873 | // SUB A,r |
||
| 874 | // SBC A,r |
||
| 875 | // AND A,r |
||
| 876 | // OR A,r |
||
| 877 | // XOR A,r |
||
| 878 | // CP A,r |
||
| 879 | Set_BusB_To[2:0] = SSS; |
||
| 880 | Set_BusA_To[2:0] = 3'b111; |
||
| 881 | Read_To_Reg = 1'b1; |
||
| 882 | Save_ALU = 1'b1; |
||
| 883 | end // else: !if(IR[2:0] == 3'b110) |
||
| 884 | end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... |
||
| 885 | |||
| 886 | 8'b11zzz110 : |
||
| 887 | begin |
||
| 888 | // ADD A,n |
||
| 889 | // ADC A,n |
||
| 890 | // SUB A,n |
||
| 891 | // SBC A,n |
||
| 892 | // AND A,n |
||
| 893 | // OR A,n |
||
| 894 | // XOR A,n |
||
| 895 | // CP A,n |
||
| 896 | MCycles = 3'b010; |
||
| 897 | if (MCycle[1] ) |
||
| 898 | begin |
||
| 899 | Inc_PC = 1'b1; |
||
| 900 | Read_To_Reg = 1'b1; |
||
| 901 | Save_ALU = 1'b1; |
||
| 902 | Set_BusB_To[2:0] = SSS; |
||
| 903 | Set_BusA_To[2:0] = 3'b111; |
||
| 904 | end |
||
| 905 | end |
||
| 906 | |||
| 907 | 8'b00zzz100 : |
||
| 908 | begin |
||
| 909 | if (IR[5:3] == 3'b110) |
||
| 910 | begin |
||
| 911 | // INC (HL) |
||
| 912 | MCycles = 3'b011; |
||
| 913 | case (1'b1) // MCycle |
||
| 914 | MCycle[0] : |
||
| 915 | Set_Addr_To = aXY; |
||
| 916 | MCycle[1] : |
||
| 917 | begin |
||
| 918 | TStates = 3'b100; |
||
| 919 | Set_Addr_To = aXY; |
||
| 920 | Read_To_Reg = 1'b1; |
||
| 921 | Save_ALU = 1'b1; |
||
| 922 | PreserveC = 1'b1; |
||
| 923 | ALU_Op = 4'b0000; |
||
| 924 | Set_BusB_To = 4'b1010; |
||
| 925 | Set_BusA_To[2:0] = DDD; |
||
| 926 | end // case: 2 |
||
| 927 | |||
| 928 | MCycle[2] : |
||
| 929 | Write = 1'b1; |
||
| 930 | default :; |
||
| 931 | endcase // case(MCycle) |
||
| 932 | end // case: 8'b00110100 |
||
| 933 | else |
||
| 934 | begin |
||
| 935 | // INC r |
||
| 936 | Set_BusB_To = 4'b1010; |
||
| 937 | Set_BusA_To[2:0] = DDD; |
||
| 938 | Read_To_Reg = 1'b1; |
||
| 939 | Save_ALU = 1'b1; |
||
| 940 | PreserveC = 1'b1; |
||
| 941 | ALU_Op = 4'b0000; |
||
| 942 | end |
||
| 943 | end |
||
| 944 | |||
| 945 | 8'b00zzz101 : |
||
| 946 | begin |
||
| 947 | if (IR[5:3] == 3'b110) |
||
| 948 | begin |
||
| 949 | // DEC (HL) |
||
| 950 | MCycles = 3'b011; |
||
| 951 | case (1'b1) // MCycle |
||
| 952 | MCycle[0] : |
||
| 953 | Set_Addr_To = aXY; |
||
| 954 | MCycle[1] : |
||
| 955 | begin |
||
| 956 | TStates = 3'b100; |
||
| 957 | Set_Addr_To = aXY; |
||
| 958 | ALU_Op = 4'b0010; |
||
| 959 | Read_To_Reg = 1'b1; |
||
| 960 | Save_ALU = 1'b1; |
||
| 961 | PreserveC = 1'b1; |
||
| 962 | Set_BusB_To = 4'b1010; |
||
| 963 | Set_BusA_To[2:0] = DDD; |
||
| 964 | end // case: 2 |
||
| 965 | |||
| 966 | MCycle[2] : |
||
| 967 | Write = 1'b1; |
||
| 968 | default :; |
||
| 969 | endcase // case(MCycle) |
||
| 970 | end |
||
| 971 | else |
||
| 972 | begin |
||
| 973 | // DEC r |
||
| 974 | Set_BusB_To = 4'b1010; |
||
| 975 | Set_BusA_To[2:0] = DDD; |
||
| 976 | Read_To_Reg = 1'b1; |
||
| 977 | Save_ALU = 1'b1; |
||
| 978 | PreserveC = 1'b1; |
||
| 979 | ALU_Op = 4'b0010; |
||
| 980 | end |
||
| 981 | end |
||
| 982 | |||
| 983 | // GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS |
||
| 984 | 8'b00100111 : |
||
| 985 | begin |
||
| 986 | // DAA |
||
| 987 | Set_BusA_To[2:0] = 3'b111; |
||
| 988 | Read_To_Reg = 1'b1; |
||
| 989 | ALU_Op = 4'b1100; |
||
| 990 | Save_ALU = 1'b1; |
||
| 991 | end |
||
| 992 | |||
| 993 | 8'b00101111 : |
||
| 994 | // CPL |
||
| 995 | I_CPL = 1'b1; |
||
| 996 | |||
| 997 | 8'b00111111 : |
||
| 998 | // CCF |
||
| 999 | I_CCF = 1'b1; |
||
| 1000 | |||
| 1001 | 8'b00110111 : |
||
| 1002 | // SCF |
||
| 1003 | I_SCF = 1'b1; |
||
| 1004 | |||
| 1005 | 8'b00000000 : |
||
| 1006 | begin |
||
| 1007 | if (NMICycle == 1'b1 ) |
||
| 1008 | begin |
||
| 1009 | // NMI |
||
| 1010 | MCycles = 3'b011; |
||
| 1011 | case (1'b1) // MCycle |
||
| 1012 | MCycle[0] : |
||
| 1013 | begin |
||
| 1014 | TStates = 3'b101; |
||
| 1015 | IncDec_16 = 4'b1111; |
||
| 1016 | Set_Addr_To = aSP; |
||
| 1017 | Set_BusB_To = 4'b1101; |
||
| 1018 | end |
||
| 1019 | |||
| 1020 | MCycle[1] : |
||
| 1021 | begin |
||
| 1022 | TStates = 3'b100; |
||
| 1023 | Write = 1'b1; |
||
| 1024 | IncDec_16 = 4'b1111; |
||
| 1025 | Set_Addr_To = aSP; |
||
| 1026 | Set_BusB_To = 4'b1100; |
||
| 1027 | end |
||
| 1028 | |||
| 1029 | MCycle[2] : |
||
| 1030 | begin |
||
| 1031 | TStates = 3'b100; |
||
| 1032 | Write = 1'b1; |
||
| 1033 | end |
||
| 1034 | |||
| 1035 | default :; |
||
| 1036 | endcase // case(MCycle) |
||
| 1037 | |||
| 1038 | end |
||
| 1039 | else if (IntCycle == 1'b1 ) |
||
| 1040 | begin |
||
| 1041 | // INT (IM 2) |
||
| 1042 | MCycles = 3'b101; |
||
| 1043 | case (1'b1) // MCycle |
||
| 1044 | MCycle[0] : |
||
| 1045 | begin |
||
| 1046 | LDZ = 1'b1; |
||
| 1047 | TStates = 3'b101; |
||
| 1048 | IncDec_16 = 4'b1111; |
||
| 1049 | Set_Addr_To = aSP; |
||
| 1050 | Set_BusB_To = 4'b1101; |
||
| 1051 | end |
||
| 1052 | |||
| 1053 | MCycle[1] : |
||
| 1054 | begin |
||
| 1055 | TStates = 3'b100; |
||
| 1056 | Write = 1'b1; |
||
| 1057 | IncDec_16 = 4'b1111; |
||
| 1058 | Set_Addr_To = aSP; |
||
| 1059 | Set_BusB_To = 4'b1100; |
||
| 1060 | end |
||
| 1061 | |||
| 1062 | MCycle[2] : |
||
| 1063 | begin |
||
| 1064 | TStates = 3'b100; |
||
| 1065 | Write = 1'b1; |
||
| 1066 | end |
||
| 1067 | |||
| 1068 | MCycle[3] : |
||
| 1069 | begin |
||
| 1070 | Inc_PC = 1'b1; |
||
| 1071 | LDZ = 1'b1; |
||
| 1072 | end |
||
| 1073 | |||
| 1074 | MCycle[4] : |
||
| 1075 | Jump = 1'b1; |
||
| 1076 | default :; |
||
| 1077 | endcase |
||
| 1078 | end |
||
| 1079 | end // case: 8'b00000000 |
||
| 1080 | |||
| 1081 | 8'b11110011 : |
||
| 1082 | // DI |
||
| 1083 | SetDI = 1'b1; |
||
| 1084 | |||
| 1085 | 8'b11111011 : |
||
| 1086 | // EI |
||
| 1087 | SetEI = 1'b1; |
||
| 1088 | |||
| 1089 | // 16 BIT ARITHMETIC GROUP |
||
| 1090 | 8'b00zz1001 : |
||
| 1091 | begin |
||
| 1092 | // ADD HL,ss |
||
| 1093 | MCycles = 3'b011; |
||
| 1094 | case (1'b1) // MCycle |
||
| 1095 | MCycle[1] : |
||
| 1096 | begin |
||
| 1097 | NoRead = 1'b1; |
||
| 1098 | ALU_Op = 4'b0000; |
||
| 1099 | Read_To_Reg = 1'b1; |
||
| 1100 | Save_ALU = 1'b1; |
||
| 1101 | Set_BusA_To[2:0] = 3'b101; |
||
| 1102 | case (IR[5:4]) |
||
| 1103 | 0,1,2 : |
||
| 1104 | begin |
||
| 1105 | Set_BusB_To[2:1] = IR[5:4]; |
||
| 1106 | Set_BusB_To[0] = 1'b1; |
||
| 1107 | end |
||
| 1108 | |||
| 1109 | default : |
||
| 1110 | Set_BusB_To = 4'b1000; |
||
| 1111 | endcase // case(IR[5:4]) |
||
| 1112 | |||
| 1113 | TStates = 3'b100; |
||
| 1114 | Arith16 = 1'b1; |
||
| 1115 | end // case: 2 |
||
| 1116 | |||
| 1117 | MCycle[2] : |
||
| 1118 | begin |
||
| 1119 | NoRead = 1'b1; |
||
| 1120 | Read_To_Reg = 1'b1; |
||
| 1121 | Save_ALU = 1'b1; |
||
| 1122 | ALU_Op = 4'b0001; |
||
| 1123 | Set_BusA_To[2:0] = 3'b100; |
||
| 1124 | case (IR[5:4]) |
||
| 1125 | 0,1,2 : |
||
| 1126 | Set_BusB_To[2:1] = IR[5:4]; |
||
| 1127 | default : |
||
| 1128 | Set_BusB_To = 4'b1001; |
||
| 1129 | endcase |
||
| 1130 | Arith16 = 1'b1; |
||
| 1131 | end // case: 3 |
||
| 1132 | |||
| 1133 | default :; |
||
| 1134 | endcase // case(MCycle) |
||
| 1135 | end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001 |
||
| 1136 | |||
| 1137 | 8'b00zz0011 : |
||
| 1138 | begin |
||
| 1139 | // INC ss |
||
| 1140 | TStates = 3'b110; |
||
| 1141 | IncDec_16[3:2] = 2'b01; |
||
| 1142 | IncDec_16[1:0] = DPAIR; |
||
| 1143 | end |
||
| 1144 | |||
| 1145 | 8'b00zz1011 : |
||
| 1146 | begin |
||
| 1147 | // DEC ss |
||
| 1148 | TStates = 3'b110; |
||
| 1149 | IncDec_16[3:2] = 2'b11; |
||
| 1150 | IncDec_16[1:0] = DPAIR; |
||
| 1151 | end |
||
| 1152 | |||
| 1153 | // ROTATE AND SHIFT GROUP |
||
| 1154 | 8'b00000111, |
||
| 1155 | // RLCA |
||
| 1156 | 8'b00010111, |
||
| 1157 | // RLA |
||
| 1158 | 8'b00001111, |
||
| 1159 | // RRCA |
||
| 1160 | 8'b00011111 : |
||
| 1161 | // RRA |
||
| 1162 | begin |
||
| 1163 | Set_BusA_To[2:0] = 3'b111; |
||
| 1164 | ALU_Op = 4'b1000; |
||
| 1165 | Read_To_Reg = 1'b1; |
||
| 1166 | Save_ALU = 1'b1; |
||
| 1167 | end // case: 8'b00000111,... |
||
| 1168 | |||
| 1169 | |||
| 1170 | // JUMP GROUP |
||
| 1171 | 8'b11000011 : |
||
| 1172 | begin |
||
| 1173 | // JP nn |
||
| 1174 | MCycles = 3'b011; |
||
| 1175 | if (MCycle[1]) |
||
| 1176 | begin |
||
| 1177 | Inc_PC = 1'b1; |
||
| 1178 | LDZ = 1'b1; |
||
| 1179 | end |
||
| 1180 | |||
| 1181 | if (MCycle[2]) |
||
| 1182 | begin |
||
| 1183 | Inc_PC = 1'b1; |
||
| 1184 | Jump = 1'b1; |
||
| 1185 | end |
||
| 1186 | |||
| 1187 | end // case: 8'b11000011 |
||
| 1188 | |||
| 1189 | 8'b11zzz010 : |
||
| 1190 | begin |
||
| 1191 | if (IR[5] == 1'b1 && Mode == 3 ) |
||
| 1192 | begin |
||
| 1193 | case (IR[4:3]) |
||
| 1194 | 2'b00 : |
||
| 1195 | begin |
||
| 1196 | // LD ($FF00+C),A |
||
| 1197 | MCycles = 3'b010; |
||
| 1198 | case (1'b1) // MCycle |
||
| 1199 | MCycle[0] : |
||
| 1200 | begin |
||
| 1201 | Set_Addr_To = aBC; |
||
| 1202 | Set_BusB_To = 4'b0111; |
||
| 1203 | end |
||
| 1204 | MCycle[1] : |
||
| 1205 | begin |
||
| 1206 | Write = 1'b1; |
||
| 1207 | IORQ = 1'b1; |
||
| 1208 | end |
||
| 1209 | |||
| 1210 | default :; |
||
| 1211 | endcase // case(MCycle) |
||
| 1212 | end // case: 2'b00 |
||
| 1213 | |||
| 1214 | 2'b01 : |
||
| 1215 | begin |
||
| 1216 | // LD (nn),A |
||
| 1217 | MCycles = 3'b100; |
||
| 1218 | case (1'b1) // MCycle |
||
| 1219 | MCycle[1] : |
||
| 1220 | begin |
||
| 1221 | Inc_PC = 1'b1; |
||
| 1222 | LDZ = 1'b1; |
||
| 1223 | end |
||
| 1224 | |||
| 1225 | MCycle[2] : |
||
| 1226 | begin |
||
| 1227 | Set_Addr_To = aZI; |
||
| 1228 | Inc_PC = 1'b1; |
||
| 1229 | Set_BusB_To = 4'b0111; |
||
| 1230 | end |
||
| 1231 | |||
| 1232 | MCycle[3] : |
||
| 1233 | Write = 1'b1; |
||
| 1234 | default :; |
||
| 1235 | endcase // case(MCycle) |
||
| 1236 | end // case: default :... |
||
| 1237 | |||
| 1238 | 2'b10 : |
||
| 1239 | begin |
||
| 1240 | // LD A,($FF00+C) |
||
| 1241 | MCycles = 3'b010; |
||
| 1242 | case (1'b1) // MCycle |
||
| 1243 | MCycle[0] : |
||
| 1244 | Set_Addr_To = aBC; |
||
| 1245 | MCycle[1] : |
||
| 1246 | begin |
||
| 1247 | Read_To_Acc = 1'b1; |
||
| 1248 | IORQ = 1'b1; |
||
| 1249 | end |
||
| 1250 | default :; |
||
| 1251 | endcase // case(MCycle) |
||
| 1252 | end // case: 2'b10 |
||
| 1253 | |||
| 1254 | 2'b11 : |
||
| 1255 | begin |
||
| 1256 | // LD A,(nn) |
||
| 1257 | MCycles = 3'b100; |
||
| 1258 | case (1'b1) // MCycle |
||
| 1259 | MCycle[1] : |
||
| 1260 | begin |
||
| 1261 | Inc_PC = 1'b1; |
||
| 1262 | LDZ = 1'b1; |
||
| 1263 | end |
||
| 1264 | MCycle[2] : |
||
| 1265 | begin |
||
| 1266 | Set_Addr_To = aZI; |
||
| 1267 | Inc_PC = 1'b1; |
||
| 1268 | end |
||
| 1269 | MCycle[3] : |
||
| 1270 | Read_To_Acc = 1'b1; |
||
| 1271 | default :; |
||
| 1272 | endcase // case(MCycle) |
||
| 1273 | end |
||
| 1274 | endcase |
||
| 1275 | end |
||
| 1276 | else |
||
| 1277 | begin |
||
| 1278 | // JP cc,nn |
||
| 1279 | MCycles = 3'b011; |
||
| 1280 | case (1'b1) // MCycle |
||
| 1281 | MCycle[1] : |
||
| 1282 | begin |
||
| 1283 | Inc_PC = 1'b1; |
||
| 1284 | LDZ = 1'b1; |
||
| 1285 | end |
||
| 1286 | MCycle[2] : |
||
| 1287 | begin |
||
| 1288 | Inc_PC = 1'b1; |
||
| 1289 | if (is_cc_true(F, IR[5:3]) ) |
||
| 1290 | begin |
||
| 1291 | Jump = 1'b1; |
||
| 1292 | end |
||
| 1293 | end |
||
| 1294 | |||
| 1295 | default :; |
||
| 1296 | endcase |
||
| 1297 | end // else: !if(DPAIR == 2'b11 ) |
||
| 1298 | end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 |
||
| 1299 | |||
| 1300 | 8'b00011000 : |
||
| 1301 | begin |
||
| 1302 | if (Mode != 2 ) |
||
| 1303 | begin |
||
| 1304 | // JR e |
||
| 1305 | MCycles = 3'b011; |
||
| 1306 | case (1'b1) // MCycle |
||
| 1307 | MCycle[1] : |
||
| 1308 | Inc_PC = 1'b1; |
||
| 1309 | MCycle[2] : |
||
| 1310 | begin |
||
| 1311 | NoRead = 1'b1; |
||
| 1312 | JumpE = 1'b1; |
||
| 1313 | TStates = 3'b101; |
||
| 1314 | end |
||
| 1315 | default :; |
||
| 1316 | endcase |
||
| 1317 | end // if (Mode != 2 ) |
||
| 1318 | end // case: 8'b00011000 |
||
| 1319 | |||
| 1320 | // Conditional relative jumps (JR [C/NC/Z/NZ], e) |
||
| 1321 | 8'b001zz000 : |
||
| 1322 | begin |
||
| 1323 | if (Mode != 2 ) |
||
| 1324 | begin |
||
| 1325 | MCycles = 3'd3; |
||
| 1326 | case (1'b1) // MCycle |
||
| 1327 | MCycle[1] : |
||
| 1328 | begin |
||
| 1329 | Inc_PC = 1'b1; |
||
| 1330 | |||
| 1331 | case (IR[4:3]) |
||
| 1332 | |||
| 1333 | 1 : MCycles = (!F[Flag_Z]) ? 3'd2 : 3'd3; |
||
| 1334 | 2 : MCycles = (F[Flag_C]) ? 3'd2 : 3'd3; |
||
| 1335 | 3 : MCycles = (!F[Flag_C]) ? 3'd2 : 3'd3; |
||
| 1336 | endcase |
||
| 1337 | end |
||
| 1338 | |||
| 1339 | MCycle[2] : |
||
| 1340 | begin |
||
| 1341 | NoRead = 1'b1; |
||
| 1342 | JumpE = 1'b1; |
||
| 1343 | TStates = 3'd5; |
||
| 1344 | end |
||
| 1345 | default :; |
||
| 1346 | endcase |
||
| 1347 | end // if (Mode != 2 ) |
||
| 1348 | end // case: 8'b00111000 |
||
| 1349 | |||
| 1350 | 8'b11101001 : |
||
| 1351 | // JP (HL) |
||
| 1352 | JumpXY = 1'b1; |
||
| 1353 | |||
| 1354 | 8'b00010000 : |
||
| 1355 | begin |
||
| 1356 | if (Mode == 3 ) |
||
| 1357 | begin |
||
| 1358 | I_DJNZ = 1'b1; |
||
| 1359 | end |
||
| 1360 | else if (Mode < 2 ) |
||
| 1361 | begin |
||
| 1362 | // DJNZ,e |
||
| 1363 | MCycles = 3'b011; |
||
| 1364 | case (1'b1) // MCycle |
||
| 1365 | MCycle[0] : |
||
| 1366 | begin |
||
| 1367 | TStates = 3'b101; |
||
| 1368 | I_DJNZ = 1'b1; |
||
| 1369 | Set_BusB_To = 4'b1010; |
||
| 1370 | Set_BusA_To[2:0] = 3'b000; |
||
| 1371 | Read_To_Reg = 1'b1; |
||
| 1372 | Save_ALU = 1'b1; |
||
| 1373 | ALU_Op = 4'b0010; |
||
| 1374 | end |
||
| 1375 | MCycle[1] : |
||
| 1376 | begin |
||
| 1377 | I_DJNZ = 1'b1; |
||
| 1378 | Inc_PC = 1'b1; |
||
| 1379 | end |
||
| 1380 | MCycle[2] : |
||
| 1381 | begin |
||
| 1382 | NoRead = 1'b1; |
||
| 1383 | JumpE = 1'b1; |
||
| 1384 | TStates = 3'b101; |
||
| 1385 | end |
||
| 1386 | default :; |
||
| 1387 | endcase |
||
| 1388 | end // if (Mode < 2 ) |
||
| 1389 | end // case: 8'b00010000 |
||
| 1390 | |||
| 1391 | |||
| 1392 | // CALL AND RETURN GROUP |
||
| 1393 | 8'b11001101 : |
||
| 1394 | begin |
||
| 1395 | // CALL nn |
||
| 1396 | MCycles = 3'b101; |
||
| 1397 | case (1'b1) // MCycle |
||
| 1398 | MCycle[1] : |
||
| 1399 | begin |
||
| 1400 | Inc_PC = 1'b1; |
||
| 1401 | LDZ = 1'b1; |
||
| 1402 | end |
||
| 1403 | MCycle[2] : |
||
| 1404 | begin |
||
| 1405 | IncDec_16 = 4'b1111; |
||
| 1406 | Inc_PC = 1'b1; |
||
| 1407 | TStates = 3'b100; |
||
| 1408 | Set_Addr_To = aSP; |
||
| 1409 | LDW = 1'b1; |
||
| 1410 | Set_BusB_To = 4'b1101; |
||
| 1411 | end |
||
| 1412 | MCycle[3] : |
||
| 1413 | begin |
||
| 1414 | Write = 1'b1; |
||
| 1415 | IncDec_16 = 4'b1111; |
||
| 1416 | Set_Addr_To = aSP; |
||
| 1417 | Set_BusB_To = 4'b1100; |
||
| 1418 | end |
||
| 1419 | MCycle[4] : |
||
| 1420 | begin |
||
| 1421 | Write = 1'b1; |
||
| 1422 | Call = 1'b1; |
||
| 1423 | end |
||
| 1424 | default :; |
||
| 1425 | endcase // case(MCycle) |
||
| 1426 | end // case: 8'b11001101 |
||
| 1427 | |||
| 1428 | 8'b11zzz100 : |
||
| 1429 | begin |
||
| 1430 | if (IR[5] == 1'b0 || Mode != 3 ) |
||
| 1431 | begin |
||
| 1432 | // CALL cc,nn |
||
| 1433 | MCycles = 3'b101; |
||
| 1434 | case (1'b1) // MCycle |
||
| 1435 | MCycle[1] : |
||
| 1436 | begin |
||
| 1437 | Inc_PC = 1'b1; |
||
| 1438 | LDZ = 1'b1; |
||
| 1439 | end |
||
| 1440 | MCycle[2] : |
||
| 1441 | begin |
||
| 1442 | Inc_PC = 1'b1; |
||
| 1443 | LDW = 1'b1; |
||
| 1444 | if (is_cc_true(F, IR[5:3]) ) |
||
| 1445 | begin |
||
| 1446 | IncDec_16 = 4'b1111; |
||
| 1447 | Set_Addr_To = aSP; |
||
| 1448 | TStates = 3'b100; |
||
| 1449 | Set_BusB_To = 4'b1101; |
||
| 1450 | end |
||
| 1451 | else |
||
| 1452 | begin |
||
| 1453 | MCycles = 3'b011; |
||
| 1454 | end // else: !if(is_cc_true(F, IR[5:3]) ) |
||
| 1455 | end // case: 3 |
||
| 1456 | |||
| 1457 | MCycle[3] : |
||
| 1458 | begin |
||
| 1459 | Write = 1'b1; |
||
| 1460 | IncDec_16 = 4'b1111; |
||
| 1461 | Set_Addr_To = aSP; |
||
| 1462 | Set_BusB_To = 4'b1100; |
||
| 1463 | end |
||
| 1464 | |||
| 1465 | MCycle[4] : |
||
| 1466 | begin |
||
| 1467 | Write = 1'b1; |
||
| 1468 | Call = 1'b1; |
||
| 1469 | end |
||
| 1470 | |||
| 1471 | default :; |
||
| 1472 | endcase |
||
| 1473 | end // if (IR[5] == 1'b0 || Mode != 3 ) |
||
| 1474 | end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 |
||
| 1475 | |||
| 1476 | 8'b11001001 : |
||
| 1477 | begin |
||
| 1478 | // RET |
||
| 1479 | MCycles = 3'b011; |
||
| 1480 | case (1'b1) // MCycle |
||
| 1481 | MCycle[0] : |
||
| 1482 | begin |
||
| 1483 | TStates = 3'b101; |
||
| 1484 | Set_Addr_To = aSP; |
||
| 1485 | end |
||
| 1486 | |||
| 1487 | MCycle[1] : |
||
| 1488 | begin |
||
| 1489 | IncDec_16 = 4'b0111; |
||
| 1490 | Set_Addr_To = aSP; |
||
| 1491 | LDZ = 1'b1; |
||
| 1492 | end |
||
| 1493 | |||
| 1494 | MCycle[2] : |
||
| 1495 | begin |
||
| 1496 | Jump = 1'b1; |
||
| 1497 | IncDec_16 = 4'b0111; |
||
| 1498 | end |
||
| 1499 | |||
| 1500 | default :; |
||
| 1501 | endcase // case(MCycle) |
||
| 1502 | end // case: 8'b11001001 |
||
| 1503 | |||
| 1504 | 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 : |
||
| 1505 | begin |
||
| 1506 | if (IR[5] == 1'b1 && Mode == 3 ) |
||
| 1507 | begin |
||
| 1508 | case (IR[4:3]) |
||
| 1509 | 2'b00 : |
||
| 1510 | begin |
||
| 1511 | // LD ($FF00+nn),A |
||
| 1512 | MCycles = 3'b011; |
||
| 1513 | case (1'b1) // MCycle |
||
| 1514 | MCycle[1] : |
||
| 1515 | begin |
||
| 1516 | Inc_PC = 1'b1; |
||
| 1517 | Set_Addr_To = aIOA; |
||
| 1518 | Set_BusB_To = 4'b0111; |
||
| 1519 | end |
||
| 1520 | |||
| 1521 | MCycle[2] : |
||
| 1522 | Write = 1'b1; |
||
| 1523 | default :; |
||
| 1524 | endcase // case(MCycle) |
||
| 1525 | end // case: 2'b00 |
||
| 1526 | |||
| 1527 | 2'b01 : |
||
| 1528 | begin |
||
| 1529 | // ADD SP,n |
||
| 1530 | MCycles = 3'b011; |
||
| 1531 | case (1'b1) // MCycle |
||
| 1532 | MCycle[1] : |
||
| 1533 | begin |
||
| 1534 | ALU_Op = 4'b0000; |
||
| 1535 | Inc_PC = 1'b1; |
||
| 1536 | Read_To_Reg = 1'b1; |
||
| 1537 | Save_ALU = 1'b1; |
||
| 1538 | Set_BusA_To = 4'b1000; |
||
| 1539 | Set_BusB_To = 4'b0110; |
||
| 1540 | end |
||
| 1541 | |||
| 1542 | MCycle[2] : |
||
| 1543 | begin |
||
| 1544 | NoRead = 1'b1; |
||
| 1545 | Read_To_Reg = 1'b1; |
||
| 1546 | Save_ALU = 1'b1; |
||
| 1547 | ALU_Op = 4'b0001; |
||
| 1548 | Set_BusA_To = 4'b1001; |
||
| 1549 | Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! |
||
| 1550 | end |
||
| 1551 | |||
| 1552 | default :; |
||
| 1553 | endcase // case(MCycle) |
||
| 1554 | end // case: 2'b01 |
||
| 1555 | |||
| 1556 | 2'b10 : |
||
| 1557 | begin |
||
| 1558 | // LD A,($FF00+nn) |
||
| 1559 | MCycles = 3'b011; |
||
| 1560 | case (1'b1) // MCycle |
||
| 1561 | MCycle[1] : |
||
| 1562 | begin |
||
| 1563 | Inc_PC = 1'b1; |
||
| 1564 | Set_Addr_To = aIOA; |
||
| 1565 | end |
||
| 1566 | |||
| 1567 | MCycle[2] : |
||
| 1568 | Read_To_Acc = 1'b1; |
||
| 1569 | default :; |
||
| 1570 | endcase // case(MCycle) |
||
| 1571 | end // case: 2'b10 |
||
| 1572 | |||
| 1573 | 2'b11 : |
||
| 1574 | begin |
||
| 1575 | // LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! |
||
| 1576 | MCycles = 3'b101; |
||
| 1577 | case (1'b1) // MCycle |
||
| 1578 | MCycle[1] : |
||
| 1579 | begin |
||
| 1580 | Inc_PC = 1'b1; |
||
| 1581 | LDZ = 1'b1; |
||
| 1582 | end |
||
| 1583 | |||
| 1584 | MCycle[2] : |
||
| 1585 | begin |
||
| 1586 | Set_Addr_To = aZI; |
||
| 1587 | Inc_PC = 1'b1; |
||
| 1588 | LDW = 1'b1; |
||
| 1589 | end |
||
| 1590 | |||
| 1591 | MCycle[3] : |
||
| 1592 | begin |
||
| 1593 | Set_BusA_To[2:0] = 3'b101; // L |
||
| 1594 | Read_To_Reg = 1'b1; |
||
| 1595 | Inc_WZ = 1'b1; |
||
| 1596 | Set_Addr_To = aZI; |
||
| 1597 | end |
||
| 1598 | |||
| 1599 | MCycle[4] : |
||
| 1600 | begin |
||
| 1601 | Set_BusA_To[2:0] = 3'b100; // H |
||
| 1602 | Read_To_Reg = 1'b1; |
||
| 1603 | end |
||
| 1604 | |||
| 1605 | default :; |
||
| 1606 | endcase // case(MCycle) |
||
| 1607 | end // case: 2'b11 |
||
| 1608 | |||
| 1609 | endcase // case(IR[4:3]) |
||
| 1610 | |||
| 1611 | end |
||
| 1612 | else |
||
| 1613 | begin |
||
| 1614 | // RET cc |
||
| 1615 | MCycles = 3'b011; |
||
| 1616 | case (1'b1) // MCycle |
||
| 1617 | MCycle[0] : |
||
| 1618 | begin |
||
| 1619 | if (is_cc_true(F, IR[5:3]) ) |
||
| 1620 | begin |
||
| 1621 | Set_Addr_To = aSP; |
||
| 1622 | end |
||
| 1623 | else |
||
| 1624 | begin |
||
| 1625 | MCycles = 3'b001; |
||
| 1626 | end |
||
| 1627 | TStates = 3'b101; |
||
| 1628 | end // case: 1 |
||
| 1629 | |||
| 1630 | MCycle[1] : |
||
| 1631 | begin |
||
| 1632 | IncDec_16 = 4'b0111; |
||
| 1633 | Set_Addr_To = aSP; |
||
| 1634 | LDZ = 1'b1; |
||
| 1635 | end |
||
| 1636 | MCycle[2] : |
||
| 1637 | begin |
||
| 1638 | Jump = 1'b1; |
||
| 1639 | IncDec_16 = 4'b0111; |
||
| 1640 | end |
||
| 1641 | default :; |
||
| 1642 | endcase |
||
| 1643 | end // else: !if(IR[5] == 1'b1 && Mode == 3 ) |
||
| 1644 | end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 |
||
| 1645 | |||
| 1646 | 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 : |
||
| 1647 | begin |
||
| 1648 | // RST p |
||
| 1649 | MCycles = 3'b011; |
||
| 1650 | case (1'b1) // MCycle |
||
| 1651 | MCycle[0] : |
||
| 1652 | begin |
||
| 1653 | TStates = 3'b101; |
||
| 1654 | IncDec_16 = 4'b1111; |
||
| 1655 | Set_Addr_To = aSP; |
||
| 1656 | Set_BusB_To = 4'b1101; |
||
| 1657 | end |
||
| 1658 | |||
| 1659 | MCycle[1] : |
||
| 1660 | begin |
||
| 1661 | Write = 1'b1; |
||
| 1662 | IncDec_16 = 4'b1111; |
||
| 1663 | Set_Addr_To = aSP; |
||
| 1664 | Set_BusB_To = 4'b1100; |
||
| 1665 | end |
||
| 1666 | |||
| 1667 | MCycle[2] : |
||
| 1668 | begin |
||
| 1669 | Write = 1'b1; |
||
| 1670 | RstP = 1'b1; |
||
| 1671 | end |
||
| 1672 | |||
| 1673 | default :; |
||
| 1674 | endcase // case(MCycle) |
||
| 1675 | end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 |
||
| 1676 | |||
| 1677 | // INPUT AND OUTPUT GROUP |
||
| 1678 | 8'b11011011 : |
||
| 1679 | begin |
||
| 1680 | if (Mode != 3 ) |
||
| 1681 | begin |
||
| 1682 | // IN A,(n) |
||
| 1683 | MCycles = 3'b011; |
||
| 1684 | case (1'b1) // MCycle |
||
| 1685 | MCycle[1] : |
||
| 1686 | begin |
||
| 1687 | Inc_PC = 1'b1; |
||
| 1688 | Set_Addr_To = aIOA; |
||
| 1689 | end |
||
| 1690 | |||
| 1691 | MCycle[2] : |
||
| 1692 | begin |
||
| 1693 | Read_To_Acc = 1'b1; |
||
| 1694 | IORQ = 1'b1; |
||
| 1695 | end |
||
| 1696 | |||
| 1697 | default :; |
||
| 1698 | endcase |
||
| 1699 | end // if (Mode != 3 ) |
||
| 1700 | end // case: 8'b11011011 |
||
| 1701 | |||
| 1702 | 8'b11010011 : |
||
| 1703 | begin |
||
| 1704 | if (Mode != 3 ) |
||
| 1705 | begin |
||
| 1706 | // OUT (n),A |
||
| 1707 | MCycles = 3'b011; |
||
| 1708 | case (1'b1) // MCycle |
||
| 1709 | MCycle[1] : |
||
| 1710 | begin |
||
| 1711 | Inc_PC = 1'b1; |
||
| 1712 | Set_Addr_To = aIOA; |
||
| 1713 | Set_BusB_To = 4'b0111; |
||
| 1714 | end |
||
| 1715 | |||
| 1716 | MCycle[2] : |
||
| 1717 | begin |
||
| 1718 | Write = 1'b1; |
||
| 1719 | IORQ = 1'b1; |
||
| 1720 | end |
||
| 1721 | |||
| 1722 | default :; |
||
| 1723 | endcase |
||
| 1724 | end // if (Mode != 3 ) |
||
| 1725 | end // case: 8'b11010011 |
||
| 1726 | |||
| 1727 | |||
| 1728 | //---------------------------------------------------------------------------- |
||
| 1729 | //---------------------------------------------------------------------------- |
||
| 1730 | // MULTIBYTE INSTRUCTIONS |
||
| 1731 | //---------------------------------------------------------------------------- |
||
| 1732 | //---------------------------------------------------------------------------- |
||
| 1733 | |||
| 1734 | 8'b11001011 : |
||
| 1735 | begin |
||
| 1736 | if (Mode != 2 ) |
||
| 1737 | begin |
||
| 1738 | Prefix = 2'b01; |
||
| 1739 | end |
||
| 1740 | end |
||
| 1741 | |||
| 1742 | 8'b11101101 : |
||
| 1743 | begin |
||
| 1744 | if (Mode < 2 ) |
||
| 1745 | begin |
||
| 1746 | Prefix = 2'b10; |
||
| 1747 | end |
||
| 1748 | end |
||
| 1749 | |||
| 1750 | 8'b11011101,8'b11111101 : |
||
| 1751 | begin |
||
| 1752 | if (Mode < 2 ) |
||
| 1753 | begin |
||
| 1754 | Prefix = 2'b11; |
||
| 1755 | end |
||
| 1756 | end |
||
| 1757 | |||
| 1758 | endcase // case(IR) |
||
| 1759 | end // case: 2'b00 |
||
| 1760 | |||
| 1761 | |||
| 1762 | 2'b01 : |
||
| 1763 | begin |
||
| 1764 | |||
| 1765 | |||
| 1766 | //---------------------------------------------------------------------------- |
||
| 1767 | // |
||
| 1768 | // CB prefixed instructions |
||
| 1769 | // |
||
| 1770 | //---------------------------------------------------------------------------- |
||
| 1771 | |||
| 1772 | Set_BusA_To[2:0] = IR[2:0]; |
||
| 1773 | Set_BusB_To[2:0] = IR[2:0]; |
||
| 1774 | |||
| 1775 | casez (IR) |
||
| 1776 | 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111, |
||
| 1777 | 8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111, |
||
| 1778 | 8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111, |
||
| 1779 | 8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111, |
||
| 1780 | 8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111, |
||
| 1781 | 8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111, |
||
| 1782 | 8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111, |
||
| 1783 | 8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 : |
||
| 1784 | begin |
||
| 1785 | // RLC r |
||
| 1786 | // RL r |
||
| 1787 | // RRC r |
||
| 1788 | // RR r |
||
| 1789 | // SLA r |
||
| 1790 | // SRA r |
||
| 1791 | // SRL r |
||
| 1792 | // SLL r (Undocumented) / SWAP r |
||
| 1793 | if (MCycle[0] ) begin |
||
| 1794 | ALU_Op = 4'b1000; |
||
| 1795 | Read_To_Reg = 1'b1; |
||
| 1796 | Save_ALU = 1'b1; |
||
| 1797 | end |
||
| 1798 | end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,... |
||
| 1799 | |||
| 1800 | 8'b00zzz110 : |
||
| 1801 | begin |
||
| 1802 | // RLC (HL) |
||
| 1803 | // RL (HL) |
||
| 1804 | // RRC (HL) |
||
| 1805 | // RR (HL) |
||
| 1806 | // SRA (HL) |
||
| 1807 | // SRL (HL) |
||
| 1808 | // SLA (HL) |
||
| 1809 | // SLL (HL) (Undocumented) / SWAP (HL) |
||
| 1810 | MCycles = 3'b011; |
||
| 1811 | case (1'b1) // MCycle |
||
| 1812 | MCycle[0], MCycle[6] : |
||
| 1813 | Set_Addr_To = aXY; |
||
| 1814 | MCycle[1] : |
||
| 1815 | begin |
||
| 1816 | ALU_Op = 4'b1000; |
||
| 1817 | Read_To_Reg = 1'b1; |
||
| 1818 | Save_ALU = 1'b1; |
||
| 1819 | Set_Addr_To = aXY; |
||
| 1820 | TStates = 3'b100; |
||
| 1821 | end |
||
| 1822 | |||
| 1823 | MCycle[2] : |
||
| 1824 | Write = 1'b1; |
||
| 1825 | default :; |
||
| 1826 | endcase // case(MCycle) |
||
| 1827 | end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 |
||
| 1828 | |||
| 1829 | 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111, |
||
| 1830 | 8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111, |
||
| 1831 | 8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111, |
||
| 1832 | 8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111, |
||
| 1833 | 8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111, |
||
| 1834 | 8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111, |
||
| 1835 | 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111, |
||
| 1836 | 8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 : |
||
| 1837 | begin |
||
| 1838 | // BIT b,r |
||
| 1839 | if (MCycle[0] ) |
||
| 1840 | begin |
||
| 1841 | Set_BusB_To[2:0] = IR[2:0]; |
||
| 1842 | ALU_Op = 4'b1001; |
||
| 1843 | end |
||
| 1844 | end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,... |
||
| 1845 | |||
| 1846 | 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 : |
||
| 1847 | begin |
||
| 1848 | // BIT b,(HL) |
||
| 1849 | MCycles = 3'b010; |
||
| 1850 | case (1'b1) // MCycle |
||
| 1851 | MCycle[0], MCycle[6] : |
||
| 1852 | Set_Addr_To = aXY; |
||
| 1853 | MCycle[1] : |
||
| 1854 | begin |
||
| 1855 | ALU_Op = 4'b1001; |
||
| 1856 | TStates = 3'b100; |
||
| 1857 | end |
||
| 1858 | |||
| 1859 | default :; |
||
| 1860 | endcase // case(MCycle) |
||
| 1861 | end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 |
||
| 1862 | |||
| 1863 | 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111, |
||
| 1864 | 8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111, |
||
| 1865 | 8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111, |
||
| 1866 | 8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111, |
||
| 1867 | 8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111, |
||
| 1868 | 8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111, |
||
| 1869 | 8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111, |
||
| 1870 | 8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 : |
||
| 1871 | begin |
||
| 1872 | // SET b,r |
||
| 1873 | if (MCycle[0] ) |
||
| 1874 | begin |
||
| 1875 | ALU_Op = 4'b1010; |
||
| 1876 | Read_To_Reg = 1'b1; |
||
| 1877 | Save_ALU = 1'b1; |
||
| 1878 | end |
||
| 1879 | end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,... |
||
| 1880 | |||
| 1881 | 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 : |
||
| 1882 | begin |
||
| 1883 | // SET b,(HL) |
||
| 1884 | MCycles = 3'b011; |
||
| 1885 | case (1'b1) // MCycle |
||
| 1886 | MCycle[0], MCycle[6] : |
||
| 1887 | Set_Addr_To = aXY; |
||
| 1888 | MCycle[1] : |
||
| 1889 | begin |
||
| 1890 | ALU_Op = 4'b1010; |
||
| 1891 | Read_To_Reg = 1'b1; |
||
| 1892 | Save_ALU = 1'b1; |
||
| 1893 | Set_Addr_To = aXY; |
||
| 1894 | TStates = 3'b100; |
||
| 1895 | end |
||
| 1896 | MCycle[2] : |
||
| 1897 | Write = 1'b1; |
||
| 1898 | default :; |
||
| 1899 | endcase // case(MCycle) |
||
| 1900 | end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 |
||
| 1901 | |||
| 1902 | 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111, |
||
| 1903 | 8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111, |
||
| 1904 | 8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111, |
||
| 1905 | 8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111, |
||
| 1906 | 8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111, |
||
| 1907 | 8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111, |
||
| 1908 | 8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111, |
||
| 1909 | 8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 : |
||
| 1910 | begin |
||
| 1911 | // RES b,r |
||
| 1912 | if (MCycle[0] ) |
||
| 1913 | begin |
||
| 1914 | ALU_Op = 4'b1011; |
||
| 1915 | Read_To_Reg = 1'b1; |
||
| 1916 | Save_ALU = 1'b1; |
||
| 1917 | end |
||
| 1918 | end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,... |
||
| 1919 | |||
| 1920 | 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 : |
||
| 1921 | begin |
||
| 1922 | // RES b,(HL) |
||
| 1923 | MCycles = 3'b011; |
||
| 1924 | case (1'b1) // MCycle |
||
| 1925 | MCycle[0], MCycle[6] : |
||
| 1926 | Set_Addr_To = aXY; |
||
| 1927 | MCycle[1] : |
||
| 1928 | begin |
||
| 1929 | ALU_Op = 4'b1011; |
||
| 1930 | Read_To_Reg = 1'b1; |
||
| 1931 | Save_ALU = 1'b1; |
||
| 1932 | Set_Addr_To = aXY; |
||
| 1933 | TStates = 3'b100; |
||
| 1934 | end |
||
| 1935 | |||
| 1936 | MCycle[2] : |
||
| 1937 | Write = 1'b1; |
||
| 1938 | default :; |
||
| 1939 | endcase // case(MCycle) |
||
| 1940 | end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 |
||
| 1941 | |||
| 1942 | endcase // case(IR) |
||
| 1943 | end // case: 2'b01 |
||
| 1944 | |||
| 1945 | |||
| 1946 | default : |
||
| 1947 | begin : default_ed_block |
||
| 1948 | |||
| 1949 | //---------------------------------------------------------------------------- |
||
| 1950 | // |
||
| 1951 | // ED prefixed instructions |
||
| 1952 | // |
||
| 1953 | //---------------------------------------------------------------------------- |
||
| 1954 | |||
| 1955 | casez (IR) |
||
| 1956 | /* |
||
| 1957 | * Undocumented NOP instructions commented out to reduce size of mcode |
||
| 1958 | * |
||
| 1959 | 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111 |
||
| 1960 | ,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111 |
||
| 1961 | ,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111 |
||
| 1962 | ,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111 |
||
| 1963 | ,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111 |
||
| 1964 | ,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111 |
||
| 1965 | ,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111 |
||
| 1966 | ,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111 |
||
| 1967 | |||
| 1968 | |||
| 1969 | ,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111 |
||
| 1970 | ,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111 |
||
| 1971 | ,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111 |
||
| 1972 | ,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111 |
||
| 1973 | , 8'b10100100,8'b10100101,8'b10100110,8'b10100111 |
||
| 1974 | , 8'b10101100,8'b10101101,8'b10101110,8'b10101111 |
||
| 1975 | , 8'b10110100,8'b10110101,8'b10110110,8'b10110111 |
||
| 1976 | , 8'b10111100,8'b10111101,8'b10111110,8'b10111111 |
||
| 1977 | ,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111 |
||
| 1978 | ,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111 |
||
| 1979 | ,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111 |
||
| 1980 | ,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111 |
||
| 1981 | ,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111 |
||
| 1982 | ,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111 |
||
| 1983 | ,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111 |
||
| 1984 | ,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 : |
||
| 1985 | ; // NOP, undocumented |
||
| 1986 | |||
| 1987 | 8'b01111110,8'b01111111 : |
||
| 1988 | // NOP, undocumented |
||
| 1989 | ; |
||
| 1990 | */ |
||
| 1991 | |||
| 1992 | // 8 BIT LOAD GROUP |
||
| 1993 | 8'b01010111 : |
||
| 1994 | begin |
||
| 1995 | // LD A,I |
||
| 1996 | Special_LD = 3'b100; |
||
| 1997 | TStates = 3'b101; |
||
| 1998 | end |
||
| 1999 | |||
| 2000 | 8'b01011111 : |
||
| 2001 | begin |
||
| 2002 | // LD A,R |
||
| 2003 | Special_LD = 3'b101; |
||
| 2004 | TStates = 3'b101; |
||
| 2005 | end |
||
| 2006 | |||
| 2007 | 8'b01000111 : |
||
| 2008 | begin |
||
| 2009 | // LD I,A |
||
| 2010 | Special_LD = 3'b110; |
||
| 2011 | TStates = 3'b101; |
||
| 2012 | end |
||
| 2013 | |||
| 2014 | 8'b01001111 : |
||
| 2015 | begin |
||
| 2016 | // LD R,A |
||
| 2017 | Special_LD = 3'b111; |
||
| 2018 | TStates = 3'b101; |
||
| 2019 | end |
||
| 2020 | |||
| 2021 | // 16 BIT LOAD GROUP |
||
| 2022 | 8'b01001011,8'b01011011,8'b01101011,8'b01111011 : |
||
| 2023 | begin |
||
| 2024 | // LD dd,(nn) |
||
| 2025 | MCycles = 3'b101; |
||
| 2026 | case (1'b1) // MCycle |
||
| 2027 | MCycle[1] : |
||
| 2028 | begin |
||
| 2029 | Inc_PC = 1'b1; |
||
| 2030 | LDZ = 1'b1; |
||
| 2031 | end |
||
| 2032 | |||
| 2033 | MCycle[2] : |
||
| 2034 | begin |
||
| 2035 | Set_Addr_To = aZI; |
||
| 2036 | Inc_PC = 1'b1; |
||
| 2037 | LDW = 1'b1; |
||
| 2038 | end |
||
| 2039 | |||
| 2040 | MCycle[3] : |
||
| 2041 | begin |
||
| 2042 | Read_To_Reg = 1'b1; |
||
| 2043 | if (IR[5:4] == 2'b11 ) |
||
| 2044 | begin |
||
| 2045 | Set_BusA_To = 4'b1000; |
||
| 2046 | end |
||
| 2047 | else |
||
| 2048 | begin |
||
| 2049 | Set_BusA_To[2:1] = IR[5:4]; |
||
| 2050 | Set_BusA_To[0] = 1'b1; |
||
| 2051 | end |
||
| 2052 | Inc_WZ = 1'b1; |
||
| 2053 | Set_Addr_To = aZI; |
||
| 2054 | end // case: 4 |
||
| 2055 | |||
| 2056 | MCycle[4] : |
||
| 2057 | begin |
||
| 2058 | Read_To_Reg = 1'b1; |
||
| 2059 | if (IR[5:4] == 2'b11 ) |
||
| 2060 | begin |
||
| 2061 | Set_BusA_To = 4'b1001; |
||
| 2062 | end |
||
| 2063 | else |
||
| 2064 | begin |
||
| 2065 | Set_BusA_To[2:1] = IR[5:4]; |
||
| 2066 | Set_BusA_To[0] = 1'b0; |
||
| 2067 | end |
||
| 2068 | end // case: 5 |
||
| 2069 | |||
| 2070 | default :; |
||
| 2071 | endcase // case(MCycle) |
||
| 2072 | end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011 |
||
| 2073 | |||
| 2074 | |||
| 2075 | 8'b01000011,8'b01010011,8'b01100011,8'b01110011 : |
||
| 2076 | begin |
||
| 2077 | // LD (nn),dd |
||
| 2078 | MCycles = 3'b101; |
||
| 2079 | case (1'b1) // MCycle |
||
| 2080 | MCycle[1] : |
||
| 2081 | begin |
||
| 2082 | Inc_PC = 1'b1; |
||
| 2083 | LDZ = 1'b1; |
||
| 2084 | end |
||
| 2085 | |||
| 2086 | MCycle[2] : |
||
| 2087 | begin |
||
| 2088 | Set_Addr_To = aZI; |
||
| 2089 | Inc_PC = 1'b1; |
||
| 2090 | LDW = 1'b1; |
||
| 2091 | if (IR[5:4] == 2'b11 ) |
||
| 2092 | begin |
||
| 2093 | Set_BusB_To = 4'b1000; |
||
| 2094 | end |
||
| 2095 | else |
||
| 2096 | begin |
||
| 2097 | Set_BusB_To[2:1] = IR[5:4]; |
||
| 2098 | Set_BusB_To[0] = 1'b1; |
||
| 2099 | Set_BusB_To[3] = 1'b0; |
||
| 2100 | end |
||
| 2101 | end // case: 3 |
||
| 2102 | |||
| 2103 | MCycle[3] : |
||
| 2104 | begin |
||
| 2105 | Inc_WZ = 1'b1; |
||
| 2106 | Set_Addr_To = aZI; |
||
| 2107 | Write = 1'b1; |
||
| 2108 | if (IR[5:4] == 2'b11 ) |
||
| 2109 | begin |
||
| 2110 | Set_BusB_To = 4'b1001; |
||
| 2111 | end |
||
| 2112 | else |
||
| 2113 | begin |
||
| 2114 | Set_BusB_To[2:1] = IR[5:4]; |
||
| 2115 | Set_BusB_To[0] = 1'b0; |
||
| 2116 | Set_BusB_To[3] = 1'b0; |
||
| 2117 | end |
||
| 2118 | end // case: 4 |
||
| 2119 | |||
| 2120 | MCycle[4] : |
||
| 2121 | begin |
||
| 2122 | Write = 1'b1; |
||
| 2123 | end |
||
| 2124 | |||
| 2125 | default :; |
||
| 2126 | endcase // case(MCycle) |
||
| 2127 | end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011 |
||
| 2128 | |||
| 2129 | 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 : |
||
| 2130 | begin |
||
| 2131 | // LDI, LDD, LDIR, LDDR |
||
| 2132 | MCycles = 3'b100; |
||
| 2133 | case (1'b1) // MCycle |
||
| 2134 | MCycle[0] : |
||
| 2135 | begin |
||
| 2136 | Set_Addr_To = aXY; |
||
| 2137 | IncDec_16 = 4'b1100; // BC |
||
| 2138 | end |
||
| 2139 | |||
| 2140 | MCycle[1] : |
||
| 2141 | begin |
||
| 2142 | Set_BusB_To = 4'b0110; |
||
| 2143 | Set_BusA_To[2:0] = 3'b111; |
||
| 2144 | ALU_Op = 4'b0000; |
||
| 2145 | Set_Addr_To = aDE; |
||
| 2146 | if (IR[3] == 1'b0 ) |
||
| 2147 | begin |
||
| 2148 | IncDec_16 = 4'b0110; // IX |
||
| 2149 | end |
||
| 2150 | else |
||
| 2151 | begin |
||
| 2152 | IncDec_16 = 4'b1110; |
||
| 2153 | end |
||
| 2154 | end // case: 2 |
||
| 2155 | |||
| 2156 | MCycle[2] : |
||
| 2157 | begin |
||
| 2158 | I_BT = 1'b1; |
||
| 2159 | TStates = 3'b101; |
||
| 2160 | Write = 1'b1; |
||
| 2161 | if (IR[3] == 1'b0 ) |
||
| 2162 | begin |
||
| 2163 | IncDec_16 = 4'b0101; // DE |
||
| 2164 | end |
||
| 2165 | else |
||
| 2166 | begin |
||
| 2167 | IncDec_16 = 4'b1101; |
||
| 2168 | end |
||
| 2169 | end // case: 3 |
||
| 2170 | |||
| 2171 | MCycle[3] : |
||
| 2172 | begin |
||
| 2173 | NoRead = 1'b1; |
||
| 2174 | TStates = 3'b101; |
||
| 2175 | end |
||
| 2176 | |||
| 2177 | default :; |
||
| 2178 | endcase // case(MCycle) |
||
| 2179 | end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 |
||
| 2180 | |||
| 2181 | 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 : |
||
| 2182 | begin |
||
| 2183 | // CPI, CPD, CPIR, CPDR |
||
| 2184 | MCycles = 3'b100; |
||
| 2185 | case (1'b1) // MCycle |
||
| 2186 | MCycle[0] : |
||
| 2187 | begin |
||
| 2188 | Set_Addr_To = aXY; |
||
| 2189 | IncDec_16 = 4'b1100; // BC |
||
| 2190 | end |
||
| 2191 | |||
| 2192 | MCycle[1] : |
||
| 2193 | begin |
||
| 2194 | Set_BusB_To = 4'b0110; |
||
| 2195 | Set_BusA_To[2:0] = 3'b111; |
||
| 2196 | ALU_Op = 4'b0111; |
||
| 2197 | Save_ALU = 1'b1; |
||
| 2198 | PreserveC = 1'b1; |
||
| 2199 | if (IR[3] == 1'b0 ) |
||
| 2200 | begin |
||
| 2201 | IncDec_16 = 4'b0110; |
||
| 2202 | end |
||
| 2203 | else |
||
| 2204 | begin |
||
| 2205 | IncDec_16 = 4'b1110; |
||
| 2206 | end |
||
| 2207 | end // case: 2 |
||
| 2208 | |||
| 2209 | MCycle[2] : |
||
| 2210 | begin |
||
| 2211 | NoRead = 1'b1; |
||
| 2212 | I_BC = 1'b1; |
||
| 2213 | TStates = 3'b101; |
||
| 2214 | end |
||
| 2215 | |||
| 2216 | MCycle[3] : |
||
| 2217 | begin |
||
| 2218 | NoRead = 1'b1; |
||
| 2219 | TStates = 3'b101; |
||
| 2220 | end |
||
| 2221 | |||
| 2222 | default :; |
||
| 2223 | endcase // case(MCycle) |
||
| 2224 | end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 |
||
| 2225 | |||
| 2226 | 8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 : |
||
| 2227 | begin |
||
| 2228 | // NEG |
||
| 2229 | ALU_Op = 4'b0010; |
||
| 2230 | Set_BusB_To = 4'b0111; |
||
| 2231 | Set_BusA_To = 4'b1010; |
||
| 2232 | Read_To_Acc = 1'b1; |
||
| 2233 | Save_ALU = 1'b1; |
||
| 2234 | end |
||
| 2235 | |||
| 2236 | 8'b01000110,8'b01001110,8'b01100110,8'b01101110 : |
||
| 2237 | begin |
||
| 2238 | // IM 0 |
||
| 2239 | IMode = 2'b00; |
||
| 2240 | end |
||
| 2241 | |||
| 2242 | 8'b01010110,8'b01110110 : |
||
| 2243 | // IM 1 |
||
| 2244 | IMode = 2'b01; |
||
| 2245 | |||
| 2246 | 8'b01011110,8'b01110111 : |
||
| 2247 | // IM 2 |
||
| 2248 | IMode = 2'b10; |
||
| 2249 | |||
| 2250 | // 16 bit arithmetic |
||
| 2251 | 8'b01001010,8'b01011010,8'b01101010,8'b01111010 : |
||
| 2252 | begin |
||
| 2253 | // ADC HL,ss |
||
| 2254 | MCycles = 3'b011; |
||
| 2255 | case (1'b1) // MCycle |
||
| 2256 | MCycle[1] : |
||
| 2257 | begin |
||
| 2258 | NoRead = 1'b1; |
||
| 2259 | ALU_Op = 4'b0001; |
||
| 2260 | Read_To_Reg = 1'b1; |
||
| 2261 | Save_ALU = 1'b1; |
||
| 2262 | Set_BusA_To[2:0] = 3'b101; |
||
| 2263 | case (IR[5:4]) |
||
| 2264 | 0,1,2 : |
||
| 2265 | begin |
||
| 2266 | Set_BusB_To[2:1] = IR[5:4]; |
||
| 2267 | Set_BusB_To[0] = 1'b1; |
||
| 2268 | end |
||
| 2269 | default : |
||
| 2270 | Set_BusB_To = 4'b1000; |
||
| 2271 | endcase |
||
| 2272 | TStates = 3'b100; |
||
| 2273 | end // case: 2 |
||
| 2274 | |||
| 2275 | MCycle[2] : |
||
| 2276 | begin |
||
| 2277 | NoRead = 1'b1; |
||
| 2278 | Read_To_Reg = 1'b1; |
||
| 2279 | Save_ALU = 1'b1; |
||
| 2280 | ALU_Op = 4'b0001; |
||
| 2281 | Set_BusA_To[2:0] = 3'b100; |
||
| 2282 | case (IR[5:4]) |
||
| 2283 | 0,1,2 : |
||
| 2284 | begin |
||
| 2285 | Set_BusB_To[2:1] = IR[5:4]; |
||
| 2286 | Set_BusB_To[0] = 1'b0; |
||
| 2287 | end |
||
| 2288 | default : |
||
| 2289 | Set_BusB_To = 4'b1001; |
||
| 2290 | endcase // case(IR[5:4]) |
||
| 2291 | end // case: 3 |
||
| 2292 | |||
| 2293 | default :; |
||
| 2294 | endcase // case(MCycle) |
||
| 2295 | end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010 |
||
| 2296 | |||
| 2297 | 8'b01000010,8'b01010010,8'b01100010,8'b01110010 : |
||
| 2298 | begin |
||
| 2299 | // SBC HL,ss |
||
| 2300 | MCycles = 3'b011; |
||
| 2301 | case (1'b1) // MCycle |
||
| 2302 | MCycle[1] : |
||
| 2303 | begin |
||
| 2304 | NoRead = 1'b1; |
||
| 2305 | ALU_Op = 4'b0011; |
||
| 2306 | Read_To_Reg = 1'b1; |
||
| 2307 | Save_ALU = 1'b1; |
||
| 2308 | Set_BusA_To[2:0] = 3'b101; |
||
| 2309 | case (IR[5:4]) |
||
| 2310 | 0,1,2 : |
||
| 2311 | begin |
||
| 2312 | Set_BusB_To[2:1] = IR[5:4]; |
||
| 2313 | Set_BusB_To[0] = 1'b1; |
||
| 2314 | end |
||
| 2315 | default : |
||
| 2316 | Set_BusB_To = 4'b1000; |
||
| 2317 | endcase |
||
| 2318 | TStates = 3'b100; |
||
| 2319 | end // case: 2 |
||
| 2320 | |||
| 2321 | MCycle[2] : |
||
| 2322 | begin |
||
| 2323 | NoRead = 1'b1; |
||
| 2324 | ALU_Op = 4'b0011; |
||
| 2325 | Read_To_Reg = 1'b1; |
||
| 2326 | Save_ALU = 1'b1; |
||
| 2327 | Set_BusA_To[2:0] = 3'b100; |
||
| 2328 | case (IR[5:4]) |
||
| 2329 | 0,1,2 : |
||
| 2330 | Set_BusB_To[2:1] = IR[5:4]; |
||
| 2331 | default : |
||
| 2332 | Set_BusB_To = 4'b1001; |
||
| 2333 | endcase |
||
| 2334 | end // case: 3 |
||
| 2335 | |||
| 2336 | default :; |
||
| 2337 | |||
| 2338 | endcase // case(MCycle) |
||
| 2339 | end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010 |
||
| 2340 | |||
| 2341 | 8'b01101111 : |
||
| 2342 | begin |
||
| 2343 | // RLD |
||
| 2344 | MCycles = 3'b100; |
||
| 2345 | case (1'b1) // MCycle |
||
| 2346 | MCycle[1] : |
||
| 2347 | begin |
||
| 2348 | NoRead = 1'b1; |
||
| 2349 | Set_Addr_To = aXY; |
||
| 2350 | end |
||
| 2351 | |||
| 2352 | MCycle[2] : |
||
| 2353 | begin |
||
| 2354 | Read_To_Reg = 1'b1; |
||
| 2355 | Set_BusB_To[2:0] = 3'b110; |
||
| 2356 | Set_BusA_To[2:0] = 3'b111; |
||
| 2357 | ALU_Op = 4'b1101; |
||
| 2358 | TStates = 3'b100; |
||
| 2359 | Set_Addr_To = aXY; |
||
| 2360 | Save_ALU = 1'b1; |
||
| 2361 | end |
||
| 2362 | |||
| 2363 | MCycle[3] : |
||
| 2364 | begin |
||
| 2365 | I_RLD = 1'b1; |
||
| 2366 | Write = 1'b1; |
||
| 2367 | end |
||
| 2368 | |||
| 2369 | default :; |
||
| 2370 | endcase // case(MCycle) |
||
| 2371 | end // case: 8'b01101111 |
||
| 2372 | |||
| 2373 | 8'b01100111 : |
||
| 2374 | begin |
||
| 2375 | // RRD |
||
| 2376 | MCycles = 3'b100; |
||
| 2377 | case (1'b1) // MCycle |
||
| 2378 | MCycle[1] : |
||
| 2379 | Set_Addr_To = aXY; |
||
| 2380 | MCycle[2] : |
||
| 2381 | begin |
||
| 2382 | Read_To_Reg = 1'b1; |
||
| 2383 | Set_BusB_To[2:0] = 3'b110; |
||
| 2384 | Set_BusA_To[2:0] = 3'b111; |
||
| 2385 | ALU_Op = 4'b1110; |
||
| 2386 | TStates = 3'b100; |
||
| 2387 | Set_Addr_To = aXY; |
||
| 2388 | Save_ALU = 1'b1; |
||
| 2389 | end |
||
| 2390 | |||
| 2391 | MCycle[3] : |
||
| 2392 | begin |
||
| 2393 | I_RRD = 1'b1; |
||
| 2394 | Write = 1'b1; |
||
| 2395 | end |
||
| 2396 | |||
| 2397 | default :; |
||
| 2398 | endcase // case(MCycle) |
||
| 2399 | end // case: 8'b01100111 |
||
| 2400 | |||
| 2401 | 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 : |
||
| 2402 | begin |
||
| 2403 | // RETI, RETN |
||
| 2404 | MCycles = 3'b011; |
||
| 2405 | case (1'b1) // MCycle |
||
| 2406 | MCycle[0] : |
||
| 2407 | Set_Addr_To = aSP; |
||
| 2408 | |||
| 2409 | MCycle[1] : |
||
| 2410 | begin |
||
| 2411 | IncDec_16 = 4'b0111; |
||
| 2412 | Set_Addr_To = aSP; |
||
| 2413 | LDZ = 1'b1; |
||
| 2414 | end |
||
| 2415 | |||
| 2416 | MCycle[2] : |
||
| 2417 | begin |
||
| 2418 | Jump = 1'b1; |
||
| 2419 | IncDec_16 = 4'b0111; |
||
| 2420 | I_RETN = 1'b1; |
||
| 2421 | end |
||
| 2422 | |||
| 2423 | default :; |
||
| 2424 | endcase // case(MCycle) |
||
| 2425 | end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 |
||
| 2426 | |||
| 2427 | 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 : |
||
| 2428 | begin |
||
| 2429 | // IN r,(C) |
||
| 2430 | MCycles = 3'b010; |
||
| 2431 | case (1'b1) // MCycle |
||
| 2432 | MCycle[0] : |
||
| 2433 | Set_Addr_To = aBC; |
||
| 2434 | |||
| 2435 | MCycle[1] : |
||
| 2436 | begin |
||
| 2437 | IORQ = 1'b1; |
||
| 2438 | if (IR[5:3] != 3'b110 ) |
||
| 2439 | begin |
||
| 2440 | Read_To_Reg = 1'b1; |
||
| 2441 | Set_BusA_To[2:0] = IR[5:3]; |
||
| 2442 | end |
||
| 2443 | I_INRC = 1'b1; |
||
| 2444 | end |
||
| 2445 | |||
| 2446 | default :; |
||
| 2447 | endcase // case(MCycle) |
||
| 2448 | end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 |
||
| 2449 | |||
| 2450 | 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 : |
||
| 2451 | begin |
||
| 2452 | // OUT (C),r |
||
| 2453 | // OUT (C),0 |
||
| 2454 | MCycles = 3'b010; |
||
| 2455 | case (1'b1) // MCycle |
||
| 2456 | MCycle[0] : |
||
| 2457 | begin |
||
| 2458 | Set_Addr_To = aBC; |
||
| 2459 | Set_BusB_To[2:0] = IR[5:3]; |
||
| 2460 | if (IR[5:3] == 3'b110 ) |
||
| 2461 | begin |
||
| 2462 | Set_BusB_To[3] = 1'b1; |
||
| 2463 | end |
||
| 2464 | end |
||
| 2465 | |||
| 2466 | MCycle[1] : |
||
| 2467 | begin |
||
| 2468 | Write = 1'b1; |
||
| 2469 | IORQ = 1'b1; |
||
| 2470 | end |
||
| 2471 | |||
| 2472 | default :; |
||
| 2473 | endcase // case(MCycle) |
||
| 2474 | end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 |
||
| 2475 | |||
| 2476 | 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 : |
||
| 2477 | begin |
||
| 2478 | // INI, IND, INIR, INDR |
||
| 2479 | MCycles = 3'b100; |
||
| 2480 | case (1'b1) // MCycle |
||
| 2481 | MCycle[0] : |
||
| 2482 | begin |
||
| 2483 | Set_Addr_To = aBC; |
||
| 2484 | Set_BusB_To = 4'b1010; |
||
| 2485 | Set_BusA_To = 4'b0000; |
||
| 2486 | Read_To_Reg = 1'b1; |
||
| 2487 | Save_ALU = 1'b1; |
||
| 2488 | ALU_Op = 4'b0010; |
||
| 2489 | end |
||
| 2490 | |||
| 2491 | MCycle[1] : |
||
| 2492 | begin |
||
| 2493 | IORQ = 1'b1; |
||
| 2494 | Set_BusB_To = 4'b0110; |
||
| 2495 | Set_Addr_To = aXY; |
||
| 2496 | end |
||
| 2497 | |||
| 2498 | MCycle[2] : |
||
| 2499 | begin |
||
| 2500 | if (IR[3] == 1'b0 ) |
||
| 2501 | begin |
||
| 2502 | IncDec_16 = 4'b0110; |
||
| 2503 | end |
||
| 2504 | else |
||
| 2505 | begin |
||
| 2506 | IncDec_16 = 4'b1110; |
||
| 2507 | end |
||
| 2508 | TStates = 3'b100; |
||
| 2509 | Write = 1'b1; |
||
| 2510 | I_BTR = 1'b1; |
||
| 2511 | end // case: 3 |
||
| 2512 | |||
| 2513 | MCycle[3] : |
||
| 2514 | begin |
||
| 2515 | NoRead = 1'b1; |
||
| 2516 | TStates = 3'b101; |
||
| 2517 | end |
||
| 2518 | |||
| 2519 | default :; |
||
| 2520 | endcase // case(MCycle) |
||
| 2521 | end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 |
||
| 2522 | |||
| 2523 | 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 : |
||
| 2524 | begin |
||
| 2525 | // OUTI, OUTD, OTIR, OTDR |
||
| 2526 | MCycles = 3'b100; |
||
| 2527 | case (1'b1) // MCycle |
||
| 2528 | MCycle[0] : |
||
| 2529 | begin |
||
| 2530 | TStates = 3'b101; |
||
| 2531 | Set_Addr_To = aXY; |
||
| 2532 | Set_BusB_To = 4'b1010; |
||
| 2533 | Set_BusA_To = 4'b0000; |
||
| 2534 | Read_To_Reg = 1'b1; |
||
| 2535 | Save_ALU = 1'b1; |
||
| 2536 | ALU_Op = 4'b0010; |
||
| 2537 | end |
||
| 2538 | |||
| 2539 | MCycle[1] : |
||
| 2540 | begin |
||
| 2541 | Set_BusB_To = 4'b0110; |
||
| 2542 | Set_Addr_To = aBC; |
||
| 2543 | if (IR[3] == 1'b0 ) |
||
| 2544 | begin |
||
| 2545 | IncDec_16 = 4'b0110; |
||
| 2546 | end |
||
| 2547 | else |
||
| 2548 | begin |
||
| 2549 | IncDec_16 = 4'b1110; |
||
| 2550 | end |
||
| 2551 | end |
||
| 2552 | |||
| 2553 | MCycle[2] : |
||
| 2554 | begin |
||
| 2555 | if (IR[3] == 1'b0 ) |
||
| 2556 | begin |
||
| 2557 | IncDec_16 = 4'b0010; |
||
| 2558 | end |
||
| 2559 | else |
||
| 2560 | begin |
||
| 2561 | IncDec_16 = 4'b1010; |
||
| 2562 | end |
||
| 2563 | IORQ = 1'b1; |
||
| 2564 | Write = 1'b1; |
||
| 2565 | I_BTR = 1'b1; |
||
| 2566 | end // case: 3 |
||
| 2567 | |||
| 2568 | MCycle[3] : |
||
| 2569 | begin |
||
| 2570 | NoRead = 1'b1; |
||
| 2571 | TStates = 3'b101; |
||
| 2572 | end |
||
| 2573 | |||
| 2574 | default :; |
||
| 2575 | endcase // case(MCycle) |
||
| 2576 | end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 |
||
| 2577 | |||
| 2578 | default : ; |
||
| 2579 | |||
| 2580 | endcase // case(IR) |
||
| 2581 | end // block: default_ed_block |
||
| 2582 | endcase // case(ISet) |
||
| 2583 | |||
| 2584 | if (Mode == 1 ) |
||
| 2585 | begin |
||
| 2586 | if (MCycle[0] ) |
||
| 2587 | begin |
||
| 2588 | //TStates = 3'b100; |
||
| 2589 | end |
||
| 2590 | else |
||
| 2591 | begin |
||
| 2592 | TStates = 3'b011; |
||
| 2593 | end |
||
| 2594 | end |
||
| 2595 | |||
| 2596 | if (Mode == 3 ) |
||
| 2597 | begin |
||
| 2598 | if (MCycle[0] ) |
||
| 2599 | begin |
||
| 2600 | //TStates = 3'b100; |
||
| 2601 | end |
||
| 2602 | else |
||
| 2603 | begin |
||
| 2604 | TStates = 3'b100; |
||
| 2605 | end |
||
| 2606 | end |
||
| 2607 | |||
| 2608 | if (Mode < 2 ) |
||
| 2609 | begin |
||
| 2610 | if (MCycle[5] ) |
||
| 2611 | begin |
||
| 2612 | Inc_PC = 1'b1; |
||
| 2613 | if (Mode == 1 ) |
||
| 2614 | begin |
||
| 2615 | Set_Addr_To = aXY; |
||
| 2616 | TStates = 3'b100; |
||
| 2617 | Set_BusB_To[2:0] = SSS; |
||
| 2618 | Set_BusB_To[3] = 1'b0; |
||
| 2619 | end |
||
| 2620 | if (IR == 8'b00110110 || IR == 8'b11001011 ) |
||
| 2621 | begin |
||
| 2622 | Set_Addr_To = aNone; |
||
| 2623 | end |
||
| 2624 | end |
||
| 2625 | if (MCycle[6] ) |
||
| 2626 | begin |
||
| 2627 | if (Mode == 0 ) |
||
| 2628 | begin |
||
| 2629 | TStates = 3'b101; |
||
| 2630 | end |
||
| 2631 | if (ISet != 2'b01 ) |
||
| 2632 | begin |
||
| 2633 | Set_Addr_To = aXY; |
||
| 2634 | end |
||
| 2635 | Set_BusB_To[2:0] = SSS; |
||
| 2636 | Set_BusB_To[3] = 1'b0; |
||
| 2637 | if (IR == 8'b00110110 || ISet == 2'b01 ) |
||
| 2638 | begin |
||
| 2639 | // LD (HL),n |
||
| 2640 | Inc_PC = 1'b1; |
||
| 2641 | end |
||
| 2642 | else |
||
| 2643 | begin |
||
| 2644 | NoRead = 1'b1; |
||
| 2645 | end |
||
| 2646 | end |
||
| 2647 | end // if (Mode < 2 ) |
||
| 2648 | |||
| 2649 | end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle) |
||
| 2650 | endmodule // T80_MCode |