WebSVN – pentevo – Blame – /fpga/current/vga/vga

Rev	Author	Line No.	Line
134	ddp	1	`include "../include/tune.v"
		2
		3	// PentEvo project (c) NedoPC 2010
		4	//
		5	// generates horizontal vga sync, double the rate of TV horizontal sync
		6	//
		7	// KVIK PHEEKS just to double HSYNC not scan-doubling
		8	// beginning of every other vga_hsync coincides with beginning of tv_hsync
		9	// length is HSYNC_END clocks @ 28mhz
		10
		11	module vga_synch(
		12
		13	input clk,
		14
		15	output reg vga_hsync,
		16
		17	output reg scanout_start,
		18
		19	input wire hsync_start
		20	);
		21
		22
		23	// localparam HSYNC_BEG = 9'd00;
		24	// localparam HSYNC_END = 10'd96;
		25
		26	// localparam SCANOUT_BEG = 10'd112;
		27
		28	localparam HSYNC_END = 10'd106;
		29	localparam SCANOUT_BEG = 10'd159;
		30
		31	localparam HPERIOD = 10'd896;
		32
		33
		34	reg [9:0] hcount;
		35
		36
		37
		38
		39	initial
		40	begin
		41	hcount = 9'd0;
		42	vga_hsync = 1'b0;
		43	end
		44
		45
		46
		47	always @(posedge clk)
		48	begin
		49	if( hsync_start )
		50	hcount <= 10'd2;
		51	else if ( hcount==(HPERIOD-9'd1) )
		52	hcount <= 10'd0;
		53	else
		54	hcount <= hcount + 9'd1;
		55	end
		56
		57
		58	always @(posedge clk)
		59	begin
		60	if( !hcount )
		61	vga_hsync <= 1'b1;
		62	else if( hcount==HSYNC_END )
		63	vga_hsync <= 1'b0;
		64	end
		65
		66
		67	always @(posedge clk)
		68	begin
		69	if( hcount==SCANOUT_BEG )
		70	scanout_start <= 1'b1;
		71	else
		72	scanout_start <= 1'b0;
		73	end
		74
		75
		76	endmodule
		77

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