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668 lvd 1 
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
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//
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// generates horizontal vga sync, double the rate of TV horizontal sync
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/*
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    This file is part of ZX-Evo Base Configuration firmware.
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    ZX-Evo Base Configuration firmware is free software:
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    you can redistribute it and/or modify it under the terms of
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    the GNU General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    ZX-Evo Base Configuration firmware is distributed in the hope that
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    it will be useful, but WITHOUT ANY WARRANTY; without even
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    the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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    See the GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with ZX-Evo Base Configuration firmware.
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    If not, see <http://www.gnu.org/licenses/>.
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*/
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`include "../include/tune.v"
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module video_vga_sync_h(
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        input  wire clk,
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        input  wire [1:0] modes_raster,
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        output reg  vga_hsync,
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        output reg  scanout_start,
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        input  wire hsync_start
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);
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        localparam HSYNC_END    = 10'd106;
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        localparam SCANOUT_BEG  = 10'd156;
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        localparam HPERIOD_224 = 10'd896;
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        localparam HPERIOD_228 = 10'd912;
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        reg [9:0] hcount;
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        initial
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        begin
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                hcount = 9'd0;
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                vga_hsync = 1'b0;
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        end
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        always @(posedge clk)
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        begin
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                        if( hsync_start )
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                                hcount <= 10'd2;
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                        else if ( hcount==( (modes_raster==2'b11) ? (HPERIOD_228-10'd1) : (HPERIOD_224-10'd1) ) )
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                                hcount <= 10'd0;
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                        else
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                                hcount <= hcount + 9'd1;
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        end
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        always @(posedge clk)
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        begin
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                if( !hcount )
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                        vga_hsync <= 1'b1;
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                else if( hcount==HSYNC_END )
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                        vga_hsync <= 1'b0;
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        end
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        always @(posedge clk)
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        begin
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                if( hcount==SCANOUT_BEG )
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                        scanout_start <= 1'b1;
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                else
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                        scanout_start <= 1'b0;
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        end
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endmodule
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