WebSVN – ngs – Blame – /fpga/ramtest_05112008/mem_tester/mem

Rev	Author	Line No.	Line
3	lvd	1	/*
		2
		3	reset...init...save.start_write.stop_write.restore.start_read(compare).stop_read.loop
		4
		5	error...
		6
		7
		8
		9	*/
		10	module mem_tester(
		11
		12	clk,
		13
		14	rst_n,
		15
		16
		17	led, // LED flashing or not
		18
		19
		20	// SRAM signals
		21	SRAM_DQ, // sram inout databus
		22
		23	SRAM_ADDR, // sram address bus
		24
		25	SRAM_UB_N,
		26	SRAM_LB_N,
		27	SRAM_WE_N, //
		28	SRAM_CE_N, //
		29	SRAM_OE_N //
		30	);
		31
		32	parameter SRAM_DATA_SIZE = 8;
		33	parameter SRAM_ADDR_SIZE = 19;
		34
		35	inout [SRAM_DATA_SIZE-1:0] SRAM_DQ;
		36	wire [SRAM_DATA_SIZE-1:0] SRAM_DQ;
		37	output [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
		38	wire [SRAM_ADDR_SIZE-1:0] SRAM_ADDR;
		39	output SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
		40	wire SRAM_UB_N,SRAM_LB_N,SRAM_WE_N,SRAM_CE_N,SRAM_OE_N;
		41
		42
		43
		44
		45	input clk;
		46
		47	input rst_n;
		48
		49	output led; reg led;
		50
		51
		52	reg inc_pass_ctr; // increment passes counter (0000-9999 BCD)
		53	reg inc_err_ctr; // increment errors counter (10 red binary LEDs)
		54
		55
		56	reg check_in_progress; // when 1 - enables errors checking
		57
		58
		59	reg [19:0] ledflash;
		60
		61
		62
		63
		64	always @(posedge clk)
		65	begin
		66	if( inc_pass_ctr )
		67	ledflash <= 20'd0;
		68	else if( !ledflash[19] )
		69	ledflash <= ledflash + 20'd1;
		70	end
		71
		72	always @(posedge clk)
		73	begin
		74	led <= ledflash[19] ^ was_error;
		75	end
		76
		77
		78
		79	reg was_error;
		80	always @(posedge clk, negedge rst_n)
		81	begin
		82	if( !rst_n )
		83	was_error <= 1'b0;
		84	else if( inc_err_ctr )
		85	was_error <= 1'b1;
		86	end
		87
		88
		89
		90	reg rnd_init,rnd_save,rnd_restore; // rnd_vec_gen control
		91	wire [SRAM_DATA_SIZE-1:0] rnd_out; // rnd_vec_gen output
		92
		93	rnd_vec_gen my_rnd( .clk(clk), .init(rnd_init), .next(sram_ready), .save(rnd_save), .restore(rnd_restore), .out(rnd_out) );
		94	defparam my_rnd.OUT_SIZE = SRAM_DATA_SIZE;
		95	defparam my_rnd.LFSR_LENGTH = 41;
		96	defparam my_rnd.LFSR_FEEDBACK = 3;
		97
		98
		99
		100
		101	reg sram_start,sram_rnw;
		102	wire sram_stop,sram_ready;
		103	wire [SRAM_DATA_SIZE-1:0] sram_rdat;
		104
		105	sram_control my_sram( .clk(clk), .clk2(clk), .start(sram_start), .rnw(sram_rnw), .stop(sram_stop), .ready(sram_ready),
		106	.rdat(sram_rdat), .wdat(rnd_out),
		107	.SRAM_DQ(SRAM_DQ), .SRAM_ADDR(SRAM_ADDR),
		108	.SRAM_CE_N(SRAM_CE_N), .SRAM_OE_N(SRAM_OE_N), .SRAM_WE_N(SRAM_WE_N) );
		109	defparam my_sram.SRAM_DATA_SIZE = SRAM_DATA_SIZE;
		110	defparam my_sram.SRAM_ADDR_SIZE = SRAM_ADDR_SIZE;
		111
		112
		113
		114
		115
		116
		117
		118	// FSM states and registers
		119	reg [3:0] curr_state,next_state;
		120
		121	parameter RESET = 4'h0;
		122
		123	parameter INIT1 = 4'h1;
		124	parameter INIT2 = 4'h2;
		125
		126	parameter BEGIN_WRITE1 = 4'h3;
		127	parameter BEGIN_WRITE2 = 4'h4;
		128	parameter BEGIN_WRITE3 = 4'h5;
		129	parameter BEGIN_WRITE4 = 4'h6;
		130
		131	parameter WRITE = 4'h7;
		132
		133	parameter BEGIN_READ1 = 4'h8;
		134	parameter BEGIN_READ2 = 4'h9;
		135	parameter BEGIN_READ3 = 4'hA;
		136	parameter BEGIN_READ4 = 4'hB;
		137
		138	parameter READ = 4'hC;
		139
		140	parameter END_READ = 4'hD;
		141
		142	parameter INC_PASSES1 = 4'hE;
		143	parameter INC_PASSES2 = 4'hF;
		144
		145
		146	// FSM dispatcher
		147
		148	always @*
		149	begin
		150	case( curr_state )
		151
		152	RESET:
		153	next_state <= INIT1;
		154
		155	INIT1:
		156	if( sram_stop )
		157	next_state <= INIT2;
		158	else
		159	next_state <= INIT1;
		160
		161	INIT2:
		162	next_state <= BEGIN_WRITE1;
		163
		164	BEGIN_WRITE1:
		165	next_state <= BEGIN_WRITE2;
		166
		167	BEGIN_WRITE2:
		168	next_state <= BEGIN_WRITE3;
		169
		170	BEGIN_WRITE3:
		171	next_state <= BEGIN_WRITE4;
		172
		173	BEGIN_WRITE4:
		174	next_state <= WRITE;
		175
		176	WRITE:
		177	if( sram_stop )
		178	next_state <= BEGIN_READ1;
		179	else
		180	next_state <= WRITE;
		181
		182	BEGIN_READ1:
		183	next_state <= BEGIN_READ2;
		184
		185	BEGIN_READ2:
		186	next_state <= BEGIN_READ3;
		187
		188	BEGIN_READ3:
		189	next_state <= BEGIN_READ4;
		190
		191	BEGIN_READ4:
		192	next_state <= READ;
		193
		194	READ:
		195	if( sram_stop )
		196	next_state <= END_READ;
		197	else
		198	next_state <= READ;
		199
		200	END_READ:
		201	next_state <= INC_PASSES1;
		202
		203	INC_PASSES1:
		204	next_state <= INC_PASSES2;
		205
		206	INC_PASSES2:
		207	next_state <= BEGIN_WRITE1;
		208
		209
		210
		211
		212	default:
		213	next_state <= RESET;
		214
		215
		216	endcase
		217	end
		218
		219
		220	// FSM sequencer
		221
		222	always @(posedge clk,negedge rst_n)
		223	begin
		224	if( !rst_n )
		225	curr_state <= RESET;
		226	else
		227	curr_state <= next_state;
		228	end
		229
		230
		231	// FSM controller
		232
		233	always @(posedge clk)
		234	begin
		235	case( curr_state )
		236
		237	//////////////////////////////////////////////////
		238	RESET:
		239	begin
		240	// various initializings begin
		241
		242	inc_pass_ctr <= 1'b0;
		243
		244	check_in_progress <= 1'b0;
		245
		246	rnd_init <= 1'b1; //begin RND init
		247
		248	rnd_save <= 1'b0;
		249	rnd_restore <= 1'b0;
		250
		251	sram_start <= 1'b1;
		252	sram_rnw <= 1'b1; // start condition for sram controller, in read mode
		253	end
		254
		255	INIT1:
		256	begin
		257	sram_start <= 1'b0; // end sram start
		258	end
		259
		260	INIT2:
		261	begin
		262	rnd_init <= 1'b0; // end rnd init
		263	end
		264
		265
		266
		267	//////////////////////////////////////////////////
		268	BEGIN_WRITE1:
		269	begin
		270	rnd_save <= 1'b1;
		271	sram_rnw <= 1'b0;
		272	end
		273
		274	BEGIN_WRITE2:
		275	begin
		276	rnd_save <= 1'b0;
		277	sram_start <= 1'b1;
		278	end
		279
		280	BEGIN_WRITE3:
		281	begin
		282	sram_start <= 1'b0;
		283	end
		284
		285	/* BEGIN_WRITE4:
		286	begin
		287	rnd_save <= 1'b0;
		288	sram_start <= 1'b1;
		289	end
		290
		291	WRITE:
		292	begin
		293	sram_start <= 1'b0;
		294	end
		295	*/
		296
		297
		298
		299	//////////////////////////////////////////////////
		300	BEGIN_READ1:
		301	begin
		302	rnd_restore <= 1'b1;
		303	sram_rnw <= 1'b1;
		304	end
		305
		306	BEGIN_READ2:
		307	begin
		308	rnd_restore <= 1'b0;
		309	sram_start <= 1'b1;
		310	end
		311
		312	BEGIN_READ3:
		313	begin
		314	sram_start <= 1'b0;
		315	check_in_progress <= 1'b1;
		316	end
		317
		318	/* BEGIN_READ4:
		319	begin
		320	rnd_restore <= 1'b0;
		321	sram_start <= 1'b1;
		322	end
		323
		324	READ:
		325	begin
		326	sram_start <= 1'b0;
		327	check_in_progress <= 1'b1;
		328	end
		329	*/
		330	END_READ:
		331	begin
		332	check_in_progress <= 1'b0;
		333	end
		334
		335	INC_PASSES1:
		336	begin
		337	inc_pass_ctr <= 1'b1;
		338	end
		339
		340	INC_PASSES2:
		341	begin
		342	inc_pass_ctr <= 1'b0;
		343	end
		344
		345
		346
		347
		348	endcase
		349	end
		350
		351
		352
		353	// errors counter
		354
		355	always @(posedge clk)
		356	inc_err_ctr <= check_in_progress & sram_ready & ((sram_rdat==rnd_out)?0:1);
		357
		358
		359
		360	endmodule
		361
		362

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