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Rev | Author | Line No. | Line |
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255 | ddp | 1 | /* |
2 | |||
3 | reset...init...save.start_write.stop_write.restore.start_read(compare).stop_read.loop |
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4 | |||
5 | */ |
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6 | |||
7 | module mem_tester( |
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8 | |||
9 | clk, |
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10 | |||
11 | rst_n, |
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12 | |||
13 | // pass/fail counters |
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14 | pass_counter, |
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15 | fail_counter, |
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16 | |||
17 | // DRAM signals |
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18 | DRAM_DQ, |
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19 | |||
20 | DRAM_MA, |
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21 | |||
22 | DRAM_RAS0_N, |
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23 | DRAM_RAS1_N, |
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24 | DRAM_LCAS_N, |
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25 | DRAM_UCAS_N, |
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26 | DRAM_WE_N |
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27 | ); |
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28 | |||
29 | parameter DRAM_DATA_SIZE = 16; |
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30 | parameter DRAM_MA_SIZE = 10; |
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31 | |||
32 | inout [DRAM_DATA_SIZE-1:0] DRAM_DQ; |
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33 | output [DRAM_MA_SIZE-1:0] DRAM_MA; |
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34 | output DRAM_RAS0_N,DRAM_RAS1_N,DRAM_LCAS_N,DRAM_UCAS_N,DRAM_WE_N; |
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35 | |||
36 | input clk; |
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37 | |||
38 | input rst_n; |
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39 | |||
40 | |||
41 | |||
42 | reg inc_pass_ctr; |
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43 | reg inc_err_ctr; |
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44 | |||
45 | reg check_in_progress; // when 1 - enables errors checking |
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46 | |||
47 | |||
48 | //---- |
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49 | |||
50 | reg [15:0] pass_counter; |
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51 | output [15:0] pass_counter; |
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52 | reg [15:0] fail_counter; |
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53 | output [15:0] fail_counter; |
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54 | reg was_error; |
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55 | |||
56 | always @(posedge clk, negedge rst_n) |
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57 | begin |
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58 | if( !rst_n ) |
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59 | begin |
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60 | pass_counter <= 16'd0; |
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61 | fail_counter <= 16'd0; |
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62 | end |
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63 | else if( inc_pass_ctr ) |
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64 | begin |
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65 | if( (!was_error)&&(pass_counter!=16'hffff) ) |
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66 | pass_counter <= pass_counter + 16'd1; |
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67 | if( (was_error)&&(fail_counter!=16'hffff) ) |
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68 | fail_counter <= fail_counter + 16'd1; |
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69 | was_error <= 1'b0; |
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70 | end |
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71 | else if( inc_err_ctr ) |
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72 | was_error <= 1'b1; |
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73 | end |
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74 | |||
75 | //---- |
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76 | |||
77 | |||
78 | |||
79 | reg rnd_init,rnd_save,rnd_restore; // rnd_vec_gen control |
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80 | wire [DRAM_DATA_SIZE-1:0] rnd_out; // rnd_vec_gen output |
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81 | |||
82 | rnd_vec_gen my_rnd( .clk(clk), .init(rnd_init), .next(ram_ready), .save(rnd_save), .restore(rnd_restore), .out(rnd_out) ); |
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83 | defparam my_rnd.OUT_SIZE = DRAM_DATA_SIZE; |
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84 | |||
380 | ddp | 85 | defparam my_rnd.LFSR_LENGTH = 17; |
86 | defparam my_rnd.LFSR_FEEDBACK = 14; |
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255 | ddp | 87 | |
88 | |||
89 | |||
90 | |||
91 | reg ram_start,ram_rnw; |
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92 | wire ram_stop,ram_ready; |
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93 | wire [DRAM_DATA_SIZE-1:0] ram_rdat; |
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94 | |||
95 | dram_control my_ram( .clk(clk), .start(ram_start), .rnw(ram_rnw), .stop(ram_stop), .ready(ram_ready), |
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96 | .rdat(ram_rdat), .wdat(rnd_out), |
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97 | .DRAM_DQ(DRAM_DQ), .DRAM_MA(DRAM_MA), .DRAM_RAS0_N(DRAM_RAS0_N), .DRAM_RAS1_N(DRAM_RAS1_N), |
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98 | .DRAM_LCAS_N(DRAM_LCAS_N), .DRAM_UCAS_N(DRAM_UCAS_N), .DRAM_WE_N(DRAM_WE_N) ); |
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99 | |||
100 | |||
101 | |||
102 | |||
103 | |||
104 | |||
105 | |||
106 | // FSM states and registers |
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107 | reg [3:0] curr_state,next_state; |
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108 | |||
109 | parameter RESET = 4'h0; |
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110 | |||
111 | parameter INIT1 = 4'h1; |
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112 | parameter INIT2 = 4'h2; |
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113 | |||
114 | parameter BEGIN_WRITE1 = 4'h3; |
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115 | parameter BEGIN_WRITE2 = 4'h4; |
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116 | parameter BEGIN_WRITE3 = 4'h5; |
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117 | parameter BEGIN_WRITE4 = 4'h6; |
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118 | |||
119 | parameter WRITE = 4'h7; |
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120 | |||
121 | parameter BEGIN_READ1 = 4'h8; |
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122 | parameter BEGIN_READ2 = 4'h9; |
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123 | parameter BEGIN_READ3 = 4'hA; |
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124 | parameter BEGIN_READ4 = 4'hB; |
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125 | |||
126 | parameter READ = 4'hC; |
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127 | |||
128 | parameter END_READ = 4'hD; |
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129 | |||
130 | parameter INC_PASSES1 = 4'hE; |
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131 | parameter INC_PASSES2 = 4'hF; |
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132 | |||
133 | |||
134 | // FSM dispatcher |
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135 | |||
136 | always @* |
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137 | begin |
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138 | case( curr_state ) |
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139 | |||
140 | RESET: |
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141 | next_state <= INIT1; |
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142 | |||
143 | INIT1: |
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144 | next_state <= INIT2; |
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145 | |||
146 | INIT2: |
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147 | if( ram_stop ) |
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148 | next_state <= BEGIN_WRITE1; |
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149 | else |
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150 | next_state <= INIT2; |
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151 | |||
152 | BEGIN_WRITE1: |
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153 | next_state <= BEGIN_WRITE2; |
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154 | |||
155 | BEGIN_WRITE2: |
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156 | next_state <= BEGIN_WRITE3; |
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157 | |||
158 | BEGIN_WRITE3: |
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159 | next_state <= BEGIN_WRITE4; |
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160 | |||
161 | BEGIN_WRITE4: |
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162 | if( ram_stop ) |
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163 | next_state <= BEGIN_WRITE4; |
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164 | else |
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165 | next_state <= WRITE; |
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166 | |||
167 | WRITE: |
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168 | if( ram_stop ) |
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169 | next_state <= BEGIN_READ1; |
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170 | else |
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171 | next_state <= WRITE; |
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172 | |||
173 | BEGIN_READ1: |
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174 | next_state <= BEGIN_READ2; |
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175 | |||
176 | BEGIN_READ2: |
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177 | next_state <= BEGIN_READ3; |
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178 | |||
179 | BEGIN_READ3: |
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180 | next_state <= BEGIN_READ4; |
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181 | |||
182 | BEGIN_READ4: |
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183 | if( ram_stop ) |
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184 | next_state <= BEGIN_READ4; |
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185 | else |
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186 | next_state <= READ; |
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187 | |||
188 | READ: |
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189 | if( ram_stop ) |
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190 | next_state <= END_READ; |
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191 | else |
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192 | next_state <= READ; |
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193 | |||
194 | END_READ: |
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195 | next_state <= INC_PASSES1; |
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196 | |||
197 | INC_PASSES1: |
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198 | next_state <= INC_PASSES2; |
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199 | |||
200 | INC_PASSES2: |
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201 | next_state <= BEGIN_WRITE1; |
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202 | |||
203 | |||
204 | |||
205 | |||
206 | default: |
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207 | next_state <= RESET; |
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208 | |||
209 | |||
210 | endcase |
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211 | end |
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212 | |||
213 | |||
214 | // FSM sequencer |
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215 | |||
216 | always @(posedge clk,negedge rst_n) |
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217 | begin |
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218 | if( !rst_n ) |
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219 | curr_state <= RESET; |
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220 | else |
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221 | curr_state <= next_state; |
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222 | end |
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223 | |||
224 | |||
225 | // FSM controller |
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226 | |||
227 | always @(posedge clk) |
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228 | begin |
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229 | case( curr_state ) |
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230 | |||
231 | ////////////////////////////////////////////////// |
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232 | RESET: |
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233 | begin |
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234 | // various initializings begin |
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235 | |||
236 | inc_pass_ctr <= 1'b0; |
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237 | check_in_progress <= 1'b0; |
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238 | rnd_init <= 1'b1; //begin RND init |
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239 | rnd_save <= 1'b0; |
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240 | rnd_restore <= 1'b0; |
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241 | ram_start <= 1'b1; |
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242 | ram_rnw <= 1'b1; |
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243 | end |
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244 | |||
245 | INIT1: |
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246 | begin |
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247 | rnd_init <= 1'b0; // end rnd init |
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248 | ram_start <= 1'b0; |
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249 | end |
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250 | |||
251 | INIT2: |
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252 | begin |
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253 | end |
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254 | |||
255 | |||
256 | |||
257 | ////////////////////////////////////////////////// |
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258 | BEGIN_WRITE1: |
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259 | begin |
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260 | rnd_save <= 1'b1; |
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261 | end |
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262 | |||
263 | BEGIN_WRITE2: |
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264 | begin |
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265 | rnd_save <= 1'b0; |
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266 | ram_start <= 1'b1; |
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267 | ram_rnw <= 1'b0; |
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268 | end |
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269 | |||
270 | BEGIN_WRITE3: |
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271 | begin |
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272 | ram_start <= 1'b0; |
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273 | end |
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274 | |||
275 | /* BEGIN_WRITE4: |
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276 | begin |
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277 | rnd_save <= 1'b0; |
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278 | ram_start <= 1'b1; |
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279 | end |
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280 | */ |
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281 | /* WRITE: |
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282 | begin |
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283 | ram_start <= 1'b0; |
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284 | end |
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285 | */ |
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286 | |||
287 | |||
288 | |||
289 | ////////////////////////////////////////////////// |
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290 | BEGIN_READ1: |
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291 | begin |
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292 | rnd_restore <= 1'b1; |
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293 | end |
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294 | |||
295 | BEGIN_READ2: |
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296 | begin |
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297 | rnd_restore <= 1'b0; |
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298 | ram_start <= 1'b1; |
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299 | ram_rnw <= 1'b1; |
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300 | end |
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301 | |||
302 | BEGIN_READ3: |
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303 | begin |
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304 | ram_start <= 1'b0; |
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305 | end |
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306 | |||
307 | BEGIN_READ4: |
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308 | begin |
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309 | check_in_progress <= 1'b1; |
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310 | end |
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311 | /* |
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312 | READ: |
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313 | begin |
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314 | ram_start <= 1'b0; |
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315 | check_in_progress <= 1'b1; |
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316 | end |
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317 | */ |
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318 | END_READ: |
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319 | begin |
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320 | check_in_progress <= 1'b0; |
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321 | end |
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322 | |||
323 | INC_PASSES1: |
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324 | begin |
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325 | inc_pass_ctr <= 1'b1; |
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326 | end |
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327 | |||
328 | INC_PASSES2: |
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329 | begin |
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330 | inc_pass_ctr <= 1'b0; |
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331 | end |
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332 | |||
333 | |||
334 | |||
335 | |||
336 | endcase |
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337 | end |
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338 | |||
339 | |||
340 | |||
341 | |||
342 | |||
343 | always @(posedge clk) |
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344 | inc_err_ctr <= check_in_progress & ram_ready & ((ram_rdat==rnd_out) ? 1'b0: 1'b1); |
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345 | |||
346 | |||
347 | |||
348 | endmodule |
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349 | |||
350 |