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255 ddp 1
/*
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reset...init...save.start_write.stop_write.restore.start_read(compare).stop_read.loop
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*/
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module mem_tester(
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    clk,
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    rst_n,
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// pass/fail counters
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    pass_counter,
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    fail_counter,
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// DRAM signals
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    DRAM_DQ,
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    DRAM_MA,
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    DRAM_RAS0_N,
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    DRAM_RAS1_N,
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    DRAM_LCAS_N,
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    DRAM_UCAS_N,
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    DRAM_WE_N
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);
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parameter DRAM_DATA_SIZE = 16;
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parameter DRAM_MA_SIZE = 10;
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    inout [DRAM_DATA_SIZE-1:0] DRAM_DQ;
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    output [DRAM_MA_SIZE-1:0] DRAM_MA;
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    output DRAM_RAS0_N,DRAM_RAS1_N,DRAM_LCAS_N,DRAM_UCAS_N,DRAM_WE_N;
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    input clk;
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    input rst_n;
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    reg inc_pass_ctr;
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    reg inc_err_ctr;
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    reg check_in_progress; // when 1 - enables errors checking
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//----
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    reg [15:0] pass_counter;
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    output [15:0] pass_counter;
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    reg [15:0] fail_counter;
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    output [15:0] fail_counter;
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    reg was_error;
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    always @(posedge clk, negedge rst_n)
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    begin
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        if( !rst_n )
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        begin
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            pass_counter <= 16'd0;
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            fail_counter <= 16'd0;
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        end
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        else if( inc_pass_ctr )
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        begin
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            if( (!was_error)&&(pass_counter!=16'hffff) )
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                pass_counter <= pass_counter + 16'd1;
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            if( (was_error)&&(fail_counter!=16'hffff) )
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                fail_counter <= fail_counter + 16'd1;
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            was_error <= 1'b0;
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        end
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        else if( inc_err_ctr )
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            was_error <= 1'b1;
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    end
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//----
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    reg rnd_init,rnd_save,rnd_restore; // rnd_vec_gen control
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    wire [DRAM_DATA_SIZE-1:0] rnd_out; // rnd_vec_gen output
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    rnd_vec_gen my_rnd( .clk(clk), .init(rnd_init), .next(ram_ready), .save(rnd_save), .restore(rnd_restore), .out(rnd_out) );
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    defparam my_rnd.OUT_SIZE = DRAM_DATA_SIZE;
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380 ddp 85
    defparam my_rnd.LFSR_LENGTH = 17;
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    defparam my_rnd.LFSR_FEEDBACK = 14;
255 ddp 87
 
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    reg ram_start,ram_rnw;
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    wire ram_stop,ram_ready;
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    wire [DRAM_DATA_SIZE-1:0] ram_rdat;
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95
    dram_control my_ram( .clk(clk), .start(ram_start), .rnw(ram_rnw), .stop(ram_stop), .ready(ram_ready),
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                         .rdat(ram_rdat), .wdat(rnd_out),
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                         .DRAM_DQ(DRAM_DQ), .DRAM_MA(DRAM_MA), .DRAM_RAS0_N(DRAM_RAS0_N), .DRAM_RAS1_N(DRAM_RAS1_N),
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                         .DRAM_LCAS_N(DRAM_LCAS_N), .DRAM_UCAS_N(DRAM_UCAS_N), .DRAM_WE_N(DRAM_WE_N) );
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// FSM states and registers
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    reg [3:0] curr_state,next_state;
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parameter RESET        = 4'h0;
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parameter INIT1        = 4'h1;
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parameter INIT2        = 4'h2;
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parameter BEGIN_WRITE1 = 4'h3;
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parameter BEGIN_WRITE2 = 4'h4;
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parameter BEGIN_WRITE3 = 4'h5;
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parameter BEGIN_WRITE4 = 4'h6;
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parameter WRITE        = 4'h7;
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parameter BEGIN_READ1  = 4'h8;
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parameter BEGIN_READ2  = 4'h9;
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parameter BEGIN_READ3  = 4'hA;
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parameter BEGIN_READ4  = 4'hB;
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parameter READ         = 4'hC;
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parameter END_READ     = 4'hD;
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parameter INC_PASSES1  = 4'hE;
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parameter INC_PASSES2  = 4'hF;
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// FSM dispatcher
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    always @*
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    begin
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        case( curr_state )
139
 
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        RESET:
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            next_state <= INIT1;
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        INIT1:
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                next_state <= INIT2;
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        INIT2:
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            if( ram_stop )
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                next_state <= BEGIN_WRITE1;
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            else
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                next_state <= INIT2;
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        BEGIN_WRITE1:
153
            next_state <= BEGIN_WRITE2;
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        BEGIN_WRITE2:
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            next_state <= BEGIN_WRITE3;
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        BEGIN_WRITE3:
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            next_state <= BEGIN_WRITE4;
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        BEGIN_WRITE4:
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            if( ram_stop )
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                next_state <= BEGIN_WRITE4;
164
            else
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                next_state <= WRITE;
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        WRITE:
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            if( ram_stop )
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                next_state <= BEGIN_READ1;
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            else
171
                next_state <= WRITE;
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173
        BEGIN_READ1:
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            next_state <= BEGIN_READ2;
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        BEGIN_READ2:
177
            next_state <= BEGIN_READ3;
178
 
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        BEGIN_READ3:
180
            next_state <= BEGIN_READ4;
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        BEGIN_READ4:
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            if( ram_stop )
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                next_state <= BEGIN_READ4;
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            else
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                next_state <= READ;
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188
        READ:
189
            if( ram_stop )
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                next_state <= END_READ;
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            else
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                next_state <= READ;
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        END_READ:
195
            next_state <= INC_PASSES1;
196
 
197
        INC_PASSES1:
198
            next_state <= INC_PASSES2;
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200
        INC_PASSES2:
201
            next_state <= BEGIN_WRITE1;
202
 
203
 
204
 
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206
        default:
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            next_state <= RESET;
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209
 
210
        endcase
211
    end
212
 
213
 
214
// FSM sequencer
215
 
216
    always @(posedge clk,negedge rst_n)
217
    begin
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        if( !rst_n )
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            curr_state <= RESET;
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        else
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            curr_state <= next_state;
222
    end
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// FSM controller
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227
    always @(posedge clk)
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    begin
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        case( curr_state )
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231
//////////////////////////////////////////////////
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        RESET:
233
        begin
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            // various initializings begin
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            inc_pass_ctr <= 1'b0;
237
            check_in_progress <= 1'b0;
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            rnd_init <= 1'b1; //begin RND init
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            rnd_save <= 1'b0;
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            rnd_restore <= 1'b0;
241
            ram_start <= 1'b1;
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            ram_rnw   <= 1'b1;
243
        end
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245
        INIT1:
246
        begin
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            rnd_init <= 1'b0; // end rnd init
248
            ram_start <= 1'b0;
249
        end
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        INIT2:
252
        begin
253
        end
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255
 
256
 
257
//////////////////////////////////////////////////
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        BEGIN_WRITE1:
259
        begin
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            rnd_save <= 1'b1;
261
        end
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263
        BEGIN_WRITE2:
264
        begin
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            rnd_save   <= 1'b0;
266
            ram_start <= 1'b1;
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            ram_rnw   <= 1'b0;
268
        end
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270
        BEGIN_WRITE3:
271
        begin
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            ram_start <= 1'b0;
273
        end
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275
/*      BEGIN_WRITE4:
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        begin
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            rnd_save   <= 1'b0;
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            ram_start <= 1'b1;
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        end
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*/
281
/*      WRITE:
282
        begin
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            ram_start <= 1'b0;
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        end
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*/
286
 
287
 
288
 
289
//////////////////////////////////////////////////
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        BEGIN_READ1:
291
        begin
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            rnd_restore <= 1'b1;
293
        end
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        BEGIN_READ2:
296
        begin
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            rnd_restore <= 1'b0;
298
            ram_start <= 1'b1;
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            ram_rnw <= 1'b1;
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        end
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        BEGIN_READ3:
303
        begin
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                ram_start <= 1'b0;
305
        end
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307
        BEGIN_READ4:
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        begin
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                check_in_progress <= 1'b1;
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        end
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/*
312
        READ:
313
        begin
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            ram_start <= 1'b0;
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            check_in_progress <= 1'b1;
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        end
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*/
318
        END_READ:
319
        begin
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            check_in_progress <= 1'b0;
321
        end
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323
        INC_PASSES1:
324
        begin
325
            inc_pass_ctr <= 1'b1;
326
        end
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        INC_PASSES2:
329
        begin
330
            inc_pass_ctr <= 1'b0;
331
        end
332
 
333
 
334
 
335
 
336
        endcase
337
    end
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343
    always @(posedge clk)
344
        inc_err_ctr <= check_in_progress & ram_ready & ((ram_rdat==rnd_out) ? 1'b0: 1'b1);
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endmodule
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