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1126 savelij 1
		ifndef	__regm161inc
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__regm161inc	equ	1
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                save
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                listing off   ; no listing over this file
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6
;****************************************************************************
7
;*                                                                          *
8
;*   AS 1.42 - File REGM161.INC                                             *
9
;*                                                                          *
10
;*   Contains Bit & Register Definitions for ATmega161                      *
11
;*                                                                          *
12
;****************************************************************************
13
 
14
;----------------------------------------------------------------------------
15
; Memory Limits
16
 
17
E2END           equ	511
18
RAMSTART	equ	0x60,data
19
RAMEND		equ	0x45f,data
20
FLASHEND	label	0x3fff
21
 
22
;----------------------------------------------------------------------------
23
; Chip Configuration
24
 
25
MCUCR		port	0x35		; MCU General Control Register
26
SM1		avrbit	MCUCR,4
27
SE		avrbit	MCUCR,5		; Sleep Enable
28
SRW10		avrbit	MCUCR,6		; Wait State Select
29
SRE		avrbit	MCUCR,7		; Enable External SRAM
30
 
31
MCUSR		port	0x34		; MCU Status Register
32
WDRF		avrbit	MCUSR,3		; Watchdog Reset Occured
33
BORF		avrbit	MCUSR,2		; Brown-Out ResetOccured
34
EXTRF		avrbit	MCUSR,1		; External Reset Occured
35
PORF		avrbit	MCUSR,0		; Power-On Reset Occured
36
 
37
EMCUCR		port	0x36		; Extended MCU Control Register
38
SRW11		avrbit	EMCUCR,1	; Wait State Select
39
SRW00		avrbit	EMCUCR,2
40
SRW01		avrbit	EMCUCR,3
41
SRL0		avrbit	EMCUCR,4	; Wait State Sector Limit
42
SRL1		avrbit	EMCUCR,5
43
SRL2		avrbit	EMCUCR,6
44
SM0		avrbit	EMCUCR,7	; Sleep Mode Select
45
 
46
;----------------------------------------------------------------------------
47
; EEPROM/Program Memory Access
48
 
49
		include	"eem.inc"
50
 
51
SPMCR		port	0x37		; Store Program Memory Control Register
52
LBSET		avrbit	SPMCR,3		; Lock Bit Set
53
PGWRT		avrbit	SPMCR,2		; Page Write
54
PGERS		avrbit	SPMCR,1		; Page Erase
55
SPMEN		avrbit	SPMCR,0		; Store Program Memory Enable
56
 
57
;----------------------------------------------------------------------------
58
; GPIO
59
 
60
PINA		port	0x19		; Port A @ 0x19 (IO) ff.
61
PINB		port	0x16		; Port B @ 0x16 (IO) ff.
62
PINC		port	0x13		; Port C @ 0x13 (IO) ff.
63
PIND		port	0x10		; Port D @ 0x10 (IO) ff.
64
PINE		port	0x05		; Port E @ 0x05 (IO) ff.
65
 
66
;----------------------------------------------------------------------------
67
; Interrupt Vectors
68
 
69
		enumconf 2,code
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		enum	 INT0_vect=2		; External Interrupt Request 0
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		nextenum INT1_vect		; External Interrupt Request 1
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		nextenum INT2_vect		; External Interrupt Request 2
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		nextenum TIMER2_COMP_vect 	; Timer/Counter 2 Compare Match
74
		nextenum TIMER2_OVF_vect	; Timer/Counter 2 Overflow
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		nextenum TIMER1_CAPT_vect	; Timer/Counter 1 Capture
76
		nextenum TIMER1_COMPA_vect	; Timer/Counter 1 Compare Match A
77
		nextenum TIMER1_COMPB_vect	; Timer/Counter 1 Compare Match B
78
		nextenum TIMER1_OVF_vect	; Timer/Counter 1 Overflow
79
		nextenum TIMER0_COMP_vect	; Timer/Counter 0 Compare Match
80
		nextenum TIMER0_OVF_vect	; Timer/Counter 0 Overflow
81
		nextenum SPI_STC_vect		; SPI Transfer Complete
82
		nextenum UART0_RX_vect		; UART0 Rx Complete
83
		nextenum UART1_RX_vect		; UART1 Rx Complete
84
		nextenum UART0_UDRE_vect	; UART0 Data Register Empty
85
		nextenum UART1_UDRE_vect	; UART1 Data Register Empty
86
		nextenum UART0_TX_vect		; UART0 Tx Complete
87
		nextenum UART1_TX_vect		; UART1 Tx Complete
88
		nextenum EE_RDY_vect		; EEPROM Ready
89
		nextenum ANA_COMP_vect		; Analog Comparator
90
 
91
;----------------------------------------------------------------------------
92
; External Interrupts
93
 
94
ISC00		avrbit	MCUCR,0		; External Interrupt 0 Sense Control
95
ISC01		avrbit	MCUCR,1
96
ISC10		avrbit	MCUCR,2		; External Interrupt 1 Sense Control
97
ISC11		avrbit	MCUCR,3
98
 
99
ISC2		avrbit	EMCUCR,0	; External Interrupt 2 Sense Control
100
 
101
GIMSK		port	0x3b		; General Interrupt Mask Register
102
INT2		avrbit	GIMSK,5		; Enable External Interrupt 2
103
INT0		avrbit	GIMSK,6		; Enable External Interrupt 0
104
INT1		avrbit	GIMSK,7		; Enable External Interrupt 1
105
 
106
GIFR		port	0x3a		; External Interrupt-Flags:
107
INTF2		avrbit	GIFR,5		; External Interrupt 2 Occured
108
INTF0		avrbit	GIFR,6		; External Interrupt 0 Occured
109
INTF1	        avrbit	GIFR,7		; External Interrupt 1 Occured
110
 
111
;----------------------------------------------------------------------------
112
; Timers
113
 
114
SFIOR		port	0x30		; Special Function I/O Register
115
PSR10		avrbit	SFIOR,0		; Prescaler Reset T0/1
116
PSR2		avrbit	SFIOR,1		; Prescaler Reset T2
117
 
118
TCCR0		port	0x33		; Timer/Counter 0 Control Register
119
CS00		avrbit	TCCR0,0		; Timer/Counter 0 Clock Select
120
CS01		avrbit	TCCR0,1
121
CS02		avrbit	TCCR0,2
122
CTC0		avrbit	TCCR0,3		; Timer/Counter 0 Clear on Compare Match
123
COM00		avrbit	TCCR0,4		; Timer/Counter 0 Compare Mode
124
COM01		avrbit	TCCR0,5
125
PWM0		avrbit	TCCR0,6		; Timer/Counter 0 PWM Enable
126
FOC0		avrbit	TCCR0,7		; Timer/Counter 0 Force Output Compare Match
127
TCNT0		port	0x32		; Timer/Counter 0 Value
128
OCR0		port	0x31		; Timer/Counter 0 Output Compare Value
129
 
130
TCCR1A		port	0x2f		; Timer/Counter 1 Control Register A
131
PWM10		avrbit	TCCR1A,0	; Timer/Counter 1 PWM Mode
132
PWM11		avrbit	TCCR1A,1
133
FOC1B		avrbit	TCCR1A,2	; Timer/Counter 1 Force Output Compare B
134
FOC1A		avrbit	TCCR1A,3	; Timer/Counter 1 Force Output Compare A
135
COM1B0		avrbit	TCCR1A,4	; Timer/Counter 1 Compare Mode B
136
COM1B1		avrbit	TCCR1A,5
137
COM1A0		avrbit	TCCR1A,6	; Timer/Counter 1 Compare Mode A
138
COM1A1		avrbit	TCCR1A,7
139
TCCR1B		port	0x2e		; Timer/Counter 1 Control Register B
140
CS10		avrbit	TCCR1B,0	; Timer/Counter 1 Prescaler Setting
141
CS11		avrbit	TCCR1B,1
142
CS12		avrbit	TCCR1B,2
143
CTC1		avrbit	TCCR1B,3	; Timer/Counter 1 Clear on Compare Match
144
ICES1		avrbit	TCCR1B,6	; Timer/Counter 1 Capture Slope Selection
145
ICNC1		avrbit	TCCR1B,7	; Timer/Counter 1 Capture Noise Filter
146
TCNT1L		port	0x2c		; Timer/Counter 1 Value LSB
147
TCNT1H		port	0x2d		; Timer/Counter 1 Value MSB
148
OCR1AL		port	0x2a		; Timer/Counter 1 Output Compare Value A LSB
149
OCR1AH		port	0x2b		; Timer/Counter 1 Output Compare Value A MSB
150
OCR1BL		port	0x28		; Timer/Counter 1 Output Compare Value B LSB
151
OCR1BH		port	0x29		; Timer/Counter 1 Output Compare Value B MSB
152
ICR1L		port	0x24		; Timer/Counter 1 Input Capture Value LSB
153
ICR1H		port	0x25		; Timer/Counter 1 Input Capture Value MSB
154
 
155
TCCR2		port	0x27		; Timer/Counter 2 Control Register
156
CS20		avrbit	TCCR2,0		; Timer/Counter 2 Prescaler Setting
157
CS21		avrbit	TCCR2,1
158
CS22		avrbit	TCCR2,2
159
CTC2		avrbit	TCCR2,3		; Timer/Counter 2 Clear on Compare Match
160
COM20		avrbit	TCCR2,4		; Timer/Counter 2 Compare Mode
161
COM21		avrbit	TCCR2,5
162
PWM2		avrbit	TCCR2,6		; Timer/Counter 2 PWM Enable
163
FOC2		avrbit	TCCR2,7		; Timer/Counter 2 Force Output Compare
164
TCNT2		port	0x23		; Timer/Counter 2 Value
165
OCR2		port	0x22		; Timer/Counter 2 Output Compare Value
166
 
167
TIMSK		port	0x39		; Timer Interrupt Mask Register
168
OCIE0		avrbit	TIMSK,0		; Timer/Counter 0 Output Compare Interrupt Enable
169
TOIE0		avrbit	TIMSK,1		; Timer/Counter 0 Overflow Interrupt Enable
170
OCIE2		avrbit	TIMSK,2		; Timer/Counter 2 Output Compare Interrupt Enable
171
TICIE1		avrbit	TIMSK,3		; Timer/Counter 1 Input Capture Interrupt Enable
172
TOIE2		avrbit	TIMSK,4		; Timer/Counter 2 Overflow Interrupt Enable
173
OCIE1B		avrbit	TIMSK,5		; Timer/Counter 1 Output Compare Interrupt Enable A
174
OCIE1A		avrbit	TIMSK,6		; Timer/Counter 1 Output Compare Interrupt Enable B
175
TOIE1		avrbit	TIMSK,7		; Timer/Counter 1 Overflow Interrupt Enable
176
 
177
TIFR		port	0x38		; Timer Interrupt Flag Register
178
 
179
ASSR		port	0x26		; Asynchronous Status Register
180
TCR2UB		avrbit	ASSR,0		; Timer/Counter Control Register 2 Update Busy
181
OCR2UB		avrbit	ASSR,1		; Output Compare Register 2
182
TCN2UB		avrbit	ASSR,2		; Timer/Counter 2 Update Busy
183
AS2		avrbit	ASSR,3		; Asynchronous Timer/Counter 2
184
 
185
;----------------------------------------------------------------------------
186
; Watchdog Timer
187
 
188
		include	"wdm21.inc"
189
WDTOE		avrbit	WDTCR,4		; Turn-Off Enable
190
 
191
;----------------------------------------------------------------------------
192
; UART
193
 
194
UDR0		port	0x0c		; UART0 I/O Data Register
195
 
196
UCSR0A		port	0x0b		; UART0 Control/Status Register A
197
OR0		avrbit	UCSR0A,3	; UART0 Overrun
198
FE0		avrbit	UCSR0A,4	; UART0 Framing Error
199
UDRE0		avrbit	UCSR0A,5	; UART0 Data Register Empty
200
TXC0		avrbit	UCSR0A,6	; UART0 Transmit Complete
201
RXC0		avrbit	UCSR0A,7	; UART0 Receive Complete
202
 
203
UCSR0B		port	0x0a		; UART0 Control/Status Register B
204
TXB80		avrbit	UCSR0B,0	; UART0 Transmit Bit 8
205
RXB80		avrbit	UCSR0B,1	; UART0 Receive Bit 8
206
CHR90		avrbit	UCSR0B,2	; UART0 9 Bit Characters
207
TXEN0		avrbit	UCSR0B,3	; UART0 Enable Transmitter
208
RXEN0		avrbit	UCSR0B,4	; UART0 Enable Receiver
209
UDRIE0		avrbit	UCSR0B,5	; UART0 Enable Data Register Empty Interrupt
210
TXCIE0		avrbit	UCSR0B,6	; UART0 Enable Transmit Complete Interrupt
211
RXCIE0		avrbit	UCSR0B,7	; UART0 Enable Receive Complete Interrupt
212
 
213
UBRR0		port	0x09		; UART0 Baud Rate Register LSB
214
 
215
UDR1		port	0x03		; UART1 I/O Data Register
216
 
217
UCSR1A		port	0x02		; UART1 Control/Status Register
218
OR1		avrbit	UCSR1A,3	; UART1 Overrun
219
FE1		avrbit	UCSR1A,4	; UART1 Framing Error
220
UDRE1		avrbit	UCSR1A,5	; UART1 Data Register Empty
221
TXC1		avrbit	UCSR1A,6	; UART1 Transmit Complete
222
RXC1		avrbit	UCSR1A,7	; UART1 Receive Complete
223
 
224
UCSR1B		port	0x01		; UART1 Control/Status Register
225
TXB81		avrbit	UCSR1B,0	; UART1 Transmit Bit 8
226
RXB81		avrbit	UCSR1B,1	; UART1 Receive Bit 8
227
CHR91		avrbit	UCSR1B,2	; UART1 9 Bit Characters
228
TXEN1		avrbit	UCSR1B,3	; UART1 Enable Transmitter
229
RXEN1		avrbit	UCSR1B,4	; UART1 Enable Receiver
230
UDRIE1		avrbit	UCSR1B,5	; UART1 Enable Data Register Empty Interrupt
231
TXCIE1		avrbit	UCSR1B,6	; UART1 Enable Transmit Complete Interrupt
232
RXCIE1		avrbit	UCSR1B,7	; UART1 Enable Receive Complete Interrupt
233
 
234
UBRR1		port	0x00		; UART1 Baud Rate Register LSB
235
 
236
UBRRHI		port	0x20		; UART0/1 Baud Rate Register MSB
237
 
238
;----------------------------------------------------------------------------
239
; SPI
240
 
241
		include "spim.inc"
242
 
243
;----------------------------------------------------------------------------
244
; Analog Comparator
245
 
246
		include "acm2.inc"
247
 
248
		restore			; re-enable listing
249
 
250
		endif			; __regm161inc