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Rev | Author | Line No. | Line |
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1186 | savelij | 1 | ifndef __regm406inc |
2 | __regm406inc equ 1 |
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3 | save |
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4 | listing off ; no listing over this file |
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5 | |||
6 | ;**************************************************************************** |
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7 | ;* * |
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8 | ;* AS 1.42 - File REGM406.INC * |
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9 | ;* * |
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10 | ;* Contains Bit & Register Definitions for ATmega406 * |
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11 | ;* * |
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12 | ;**************************************************************************** |
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13 | |||
14 | ;---------------------------------------------------------------------------- |
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15 | ; Memory Limits |
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16 | |||
17 | E2END equ 511 |
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18 | RAMSTART equ 0x100,data |
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19 | RAMEND equ 0x8ff,data |
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20 | FLASHEND label 0x9fff |
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21 | |||
22 | ;---------------------------------------------------------------------------- |
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23 | ; Chip Control |
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24 | |||
25 | MCUCR port 0x35 ; MCU Control Register |
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26 | IVCE avrbit MCUCR,0 ; Interrupt Vector Change Enable |
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27 | IVSEL avrbit MCUCR,1 ; Interrupt Vector Select |
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28 | |||
29 | MCUSR port 0x34 ; MCU Status Register |
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30 | PORF avrbit MCUSR,0 ; Power-On Reset Occured |
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31 | EXTRF avrbit MCUSR,1 ; External Reset Occured |
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32 | BORF avrbit MCUSR,2 ; Brown-Out Reset Occured |
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33 | WDRF avrbit MCUSR,3 ; Watchdog Reset Occured |
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34 | |||
35 | SMCR port 0x33 ; Sleep Mode Control Register |
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36 | SE avrbit SMCR,0 ; Sleep Mode Enable |
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37 | SM0 avrbit SMCR,1 ; Sleep Mode Select |
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38 | SM1 avrbit SMCR,2 |
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39 | SM2 avrbit SMCR,3 |
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40 | |||
41 | PRR0 sfr 0x64 ; Power Reduction Register 0 |
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42 | PRVADC avrbit PRR0,0 ; Power Reduction Voltage ADC |
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43 | PRTIM0 avrbit PRR0,1 ; Power Reduction Timer/Counter 0 |
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44 | PRTIM1 avrbit PRR0,2 ; Power Reduction Timer/Counter 1 |
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45 | PRTWI avrbit PRR0,3 ; Power Reduction Two Wire Interface |
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46 | |||
47 | FOSCCAL sfr 0x66 ; Fast Oscillator Calibration |
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48 | |||
49 | CCSR sfr 0xc0 ; Clock Control and Status Register |
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50 | XOE avrbit CCSR,1 ; 32 kHz Crystal Oscillator Enable |
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51 | ACS avrbit CCSR,0 ; Asynchronous Clock Select |
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52 | |||
53 | WUTCSR sfr 0x62 ; Wake-up Timer Control and Status Register |
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54 | WUTIF avrbit WUTCSR,7 ; Wake-up Timer Interrupt Flag |
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55 | WUTIE avrbit WUTCSR,6 ; Wake-up Timer Interrupt Enable |
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56 | WUTCF avrbit WUTCSR,5 ; Wake-up Timer Calibration Flag |
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57 | WUTR avrbit WUTCSR,4 ; Wake-up Timer Reset |
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58 | WUTE avrbit WUTCSR,3 ; Wake-up Timer Enable |
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59 | WUTP2 avrbit WUTCSR,2 ; Wake-up Timer Prescaler 2, 1, and 0 |
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60 | WUTP1 avrbit WUTCSR,1 |
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61 | WUTP0 avrbit WUTCSR,0 |
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62 | |||
63 | BGCCR sfr 0xd0 ; Bandgap Calibration C Register |
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64 | BGEN avrbit BGCCR,7 ; reserved |
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65 | BGCC5 avrbit BGCCR,5 ; BG Calibration of PTAT Current |
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66 | BGCC4 avrbit BGCCR,4 |
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67 | BGCC3 avrbit BGCCR,3 |
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68 | BGCC2 avrbit BGCCR,2 |
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69 | BGCC1 avrbit BGCCR,1 |
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70 | BGCC0 avrbit BGCCR,0 |
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71 | |||
72 | BGCRR sfr 0xd1 ; Bandgap Calibration R Register |
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73 | BGCR7 avrbit BGCRR,7 ; BG Calibration of Resistor Ladder |
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74 | BGCR6 avrbit BGCRR,6 |
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75 | BGCR5 avrbit BGCRR,5 |
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76 | BGCR4 avrbit BGCRR,4 |
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77 | BGCR3 avrbit BGCRR,3 |
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78 | BGCR2 avrbit BGCRR,2 |
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79 | BGCR1 avrbit BGCRR,1 |
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80 | BGCR0 avrbit BGCRR,0 |
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81 | |||
82 | ;---------------------------------------------------------------------------- |
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83 | ; EEPROM/Program Memory Access |
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84 | |||
85 | include "eem2.inc" |
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86 | include "spmcsr37.inc" |
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87 | |||
88 | EEPM0 avrbit EECR,4 ; EEPROM Programming Mode |
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89 | EEPM1 avrbit EECR,5 |
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90 | |||
91 | SIGRD avrbit SPMCSR,5 ; Signature Row Read |
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92 | |||
93 | ;---------------------------------------------------------------------------- |
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94 | ; JTAG |
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95 | |||
96 | JTD avrbit MCUCR,7 ; JTAG Disable |
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97 | |||
98 | JTRF avrbit MCUSR,4 ; JTAG Reset Occured |
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99 | |||
100 | OCDR port 0x31 ; On-Chip Debug Register |
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101 | |||
102 | ;---------------------------------------------------------------------------- |
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103 | ; GPIO |
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104 | |||
105 | PINA port 0x00 ; Port A @ 0x00 (IO) ff. |
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106 | PINB port 0x03 ; Port B @ 0x03 (IO) ff. |
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107 | PORTC port 0x08 ; Port C @ 0x08 (Inp only) |
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108 | PIND port 0x09 ; Port D @ 0x09 (IO) ff. |
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109 | |||
110 | PCMSK0 sfr 0x6b ; Pin Change Mask Register 0 |
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111 | PCMSK1 sfr 0x6c ; Pin Change Mask Register 1 |
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112 | PCICR sfr 0x68 ; Pin Change Interrupt Control Register |
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113 | PCIFR port 0x1b ; Pin Change Interrupt Flag Register |
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114 | |||
115 | GPIOR0 port 0x1e ; General Purpose I/O Registers |
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116 | GPIOR1 port 0x2a |
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117 | GPIOR2 port 0x2b |
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118 | |||
119 | ;---------------------------------------------------------------------------- |
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120 | ; Interrupt Vectors |
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121 | |||
122 | enumconf 2,code |
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123 | enum BPINT_vect=2 ; battery protection Interrupt |
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124 | nextenum INT0_vect ; External Interrupt Request 0 |
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125 | nextenum INT1_vect ; External Interrupt Request 1 |
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126 | nextenum INT2_vect ; External Interrupt Request 2 |
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127 | nextenum INT3_vect ; External Interrupt Request 3 |
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128 | nextenum PCINT0_vect ; Pin Change Interrupt Request 0 |
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129 | nextenum PCINT1_vect ; Pin Change Interrupt Request 1 |
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130 | nextenum WDT_vect ; Watchdog Time-Out Interrupt |
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131 | nextenum WAKE_UP_vect ; Wake-Up Timer Overflow |
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132 | nextenum TIMER1_COMP_vect ; Timer/Counter 1 Compare Match |
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133 | nextenum TIMER1_OVF_vect ; Timer/Counter 1 Overflow |
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134 | nextenum TIMER0_COMPA_vect ; Timer/Counter 0 Compare Match A |
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135 | nextenum TIMER0_COMPB_vect ; Timer/Counter 0 Compare Match B |
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136 | nextenum TIMER0_OVF_vect ; Timer/Counter 0 Overflow |
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137 | nextenum TWI_BUS_CD_vect ; Two-Wire Bus Connect/Disconnect |
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138 | nextenum TWI_vect ; 2-Wire Transfer Complete |
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139 | nextenum VADC_vect ; Voltage ADC Conversion Complete |
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140 | nextenum CCADC_CONV_vect ; CC-ADC Instantaneous Current Conversion Complete |
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141 | nextenum CCADC_REG_CUR_vect ; CC-ADC Regular Current |
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142 | nextenum CCADC_ACC_vect ; CC-ADC Accumulate Current Conversion Complete |
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143 | nextenum EE_READY_vect ; EEPROM Ready |
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144 | nextenum SPM_READY_vect ; Store Program Memory Ready |
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145 | |||
146 | ;---------------------------------------------------------------------------- |
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147 | ; External Interrupts |
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148 | |||
149 | EICRA sfr 0x69 ; External Interrupt Control Register A |
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150 | ISC00 avrbit EICRA,0 ; External Interrupt 0 Sense Control |
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151 | ISC01 avrbit EICRA,1 |
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152 | ISC10 avrbit EICRA,2 ; External Interrupt 1 Sense Control |
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153 | ISC11 avrbit EICRA,3 |
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154 | ISC20 avrbit EICRA,4 ; External Interrupt 2 Sense Control |
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155 | ISC21 avrbit EICRA,5 |
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156 | ISC30 avrbit EICRA,6 ; External Interrupt 3 Sense Control |
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157 | ISC31 avrbit EICRA,7 |
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158 | |||
159 | EIMSK port 0x1d ; External Interrupt Mask Register |
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160 | INT0 avrbit EIMSK,0 ; Enable External Interrupt 0 |
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161 | INT1 avrbit EIMSK,1 ; Enable External Interrupt 1 |
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162 | INT2 avrbit EIMSK,2 ; Enable External Interrupt 2 |
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163 | INT3 avrbit EIMSK,3 ; Enable External Interrupt 3 |
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164 | |||
165 | EIFR port 0x1c ; External Interrupt Flag Register |
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166 | INTF0 avrbit EIFR,0 ; External Interrupt 0 Occured |
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167 | INTF1 avrbit EIFR,1 ; External Interrupt 1 Occured |
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168 | INTF2 avrbit EIFR,2 ; External Interrupt 2 Occured |
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169 | INTF3 avrbit EIFR,3 ; External Interrupt 3 Occured |
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170 | |||
171 | ;---------------------------------------------------------------------------- |
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172 | ; Timers |
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173 | |||
174 | GTCCR port 0x23 ; General Timer/Counter Control Register |
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175 | PSRSYNC avrbit GTCCR,0 ; Prescaler Reset |
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176 | TSM avrbit GTCCR,7 ; Timer/Counter Synchronization Mode |
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177 | |||
178 | TCCR0A port 0x24 ; Timer/Counter 0 Control Register A |
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179 | WGM00 avrbit TCCR0A,0 ; Timer/Counter 0 Waveform Generation Mode |
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180 | WGM01 avrbit TCCR0A,1 |
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181 | COM0B0 avrbit TCCR0A,4 ; Timer/Counter 0 Compare B Mode |
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182 | COM0B1 avrbit TCCR0A,5 |
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183 | COM0A0 avrbit TCCR0A,6 ; Timer/Counter 0 Compare A Mode |
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184 | COM0A1 avrbit TCCR0A,7 |
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185 | TCCR0B port 0x25 ; Timer/Counter 0 Control Register B |
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186 | CS00 avrbit TCCR0B,0 ; Timer/Counter 0 Clock Select |
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187 | CS01 avrbit TCCR0B,1 |
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188 | CS02 avrbit TCCR0B,2 |
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189 | WGM02 avrbit TCCR0B,3 ; Timer/Counter 0 Waveform Generation Mode |
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190 | FOC0B avrbit TCCR0B,6 ; Timer/Counter 0 Force Output Compare B |
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191 | FOC0A avrbit TCCR0B,7 ; Timer/Counter 0 Force Output Compare A |
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192 | TCNT0 port 0x26 ; Timer/Counter 0 |
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193 | OCR0A port 0x27 ; Timer/Counter 0 Output Compare Value A |
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194 | OCR0B port 0x28 ; Timer/Counter 0 Output Compare Value B |
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195 | |||
196 | TCCR1B sfr 0x81 ; Timer/Counter 1 Control Register B |
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197 | CS10 avrbit TCCR1B,0 ; Timer/Counter 1 Prescaler Setting |
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198 | CS11 avrbit TCCR1B,1 |
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199 | CS12 avrbit TCCR1B,2 |
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200 | CTC1 avrbit TCCR1B,3 ; Timer/Counter 1 Clear on Match |
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201 | TCNT1L sfr 0x84 ; Timer/Counter 1 Value LSB |
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202 | TCNT1H sfr 0x85 ; Timer/Counter 1 Value MSB |
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203 | OCR1AL sfr 0x88 ; Timer/Counter 1 Output Compare Value A LSB |
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204 | OCR1AH sfr 0x89 ; Timer/Counter 1 Output Compare Value A MSB |
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205 | |||
206 | TIMSK0 sfr 0x6e ; Timer/Counter 0 Interrupt Mask Register |
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207 | TOIE0 avrbit TIMSK0,0 ; Timer/Counter 0 Overflow Interrupt Enable |
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208 | OCIE0A avrbit TIMSK0,1 ; Timer/Counter 0 Output Compare Interrupt Enable A |
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209 | OCIE0B avrbit TIMSK0,2 ; Timer/Counter 0 Output Compare Interrupt Enable B |
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210 | TIMSK1 sfr 0x6f ; Timer/Counter 1 Interrupt Mask Register |
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211 | TOIE1 avrbit TIMSK1,0 ; Timer/Counter 1 Overflow Interrupt Enable |
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212 | OCIE1A avrbit TIMSK1,1 ; Timer/Counter 1 Output Compare Interrupt Enable A |
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213 | ICIE1 avrbit TIMSK1,5 ; Timer/Counter 1 Input Capture Event |
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214 | |||
215 | TIFR0 port 0x15 ; Timer/Counter 0 Interrupt Status Register |
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216 | TIFR1 port 0x16 ; Timer/Counter 1 Interrupt Status Register |
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217 | |||
218 | ;---------------------------------------------------------------------------- |
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219 | ; Watchdog Timer |
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220 | |||
221 | include "wdme.inc" |
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222 | |||
223 | ;---------------------------------------------------------------------------- |
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224 | ; TWI |
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225 | |||
226 | include "twimb8.inc" |
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227 | |||
228 | TWBCSR sfr 0xbe ; TWI Bus Control and Status Register |
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229 | TWBCIF avrbit TWBCSR,7 ; TWI Bus Connect/Disconnect Interrupt Flag |
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230 | TWBCIE avrbit TWBCSR,6 ; TWI Bus Connect/Disconnect Interrupt Enable |
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231 | TWBDT1 avrbit TWBCSR,2 ; TWI Bus Disconnect Time-Out Period |
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232 | TWBDT0 avrbit TWBCSR,1 |
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233 | TWBCIP avrbit TWBCSR,0 ; TWI Bus Connect/Disconnect Interrupt Polarity |
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234 | |||
235 | ;---------------------------------------------------------------------------- |
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236 | ; Coulomb Counter |
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237 | |||
238 | CADCSRA sfr 0xe4 ; CC-ADC Control and Status Register A |
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239 | CADSE avrbit CADCSRA,0 ; CC-ADC Current Sampling Enable |
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240 | CADIS0 avrbit CADCSRA,1 ; CC-ADC Current Sampling Interval |
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241 | CADIS1 avrbit CADCSRA,2 |
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242 | CADAS0 avrbit CADCSRA,3 ; CC-ADC Accumulate Current Select |
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243 | CADAS1 avrbit CADCSRA,4 |
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244 | CADUB avrbit CADCSRA,5 ; CADUB: CC-ADC Update Busy |
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245 | CADEN avrbit CADCSRA,7 ; CC-ADC Enable |
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246 | |||
247 | CADCSRB sfr 0xe5 ; CC-ADC Control and Status Register B |
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248 | CADACIE avrbit CADCSRB,6 ; CC-ADC Accumulate Current Interrupt Enable |
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249 | CADRCIE avrbit CADCSRB,5 ; CC-ADC Regular Current Interrupt Enable |
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250 | CADICIE avrbit CADCSRB,4 ; CC-ADC Instantaneous Current Interrupt Enable |
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251 | CADACIF avrbit CADCSRB,2 ; CC-ADC Accumulate Current Interrupt Flag |
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252 | CADRCIF avrbit CADCSRB,1 ; CC-ADC Regular Current Interrupt Flag |
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253 | CADICIF avrbit CADCSRB,0 ; CC-ADC Instantaneous Current Interrupt Flag |
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254 | |||
255 | CADICL sfr 0xe8 ; CC-ADC Instantaneous Current |
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256 | CADICH sfr 0xe9 |
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257 | |||
258 | CADAC0 sfr 0xe0 ; CC-ADC Accumulate Current |
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259 | CADAC1 sfr 0xe1 |
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260 | CADAC2 sfr 0xe2 |
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261 | CADAC3 sfr 0xe3 |
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262 | |||
263 | CADRCC sfr 0xe6 ; CC-ADC Regular Charge Current |
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264 | |||
265 | CADRDC sfr 0xe7 ; CC-ADC Regular Discharge Current |
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266 | |||
267 | ;---------------------------------------------------------------------------- |
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268 | ; Voltage A/D Converter |
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269 | |||
270 | VADMUX sfr 0x7c ; Multiplexer Selection Register |
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271 | VADMUX0 avrbit VADMUX,0 ; Channel Selection Bits |
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272 | VADMUX1 avrbit VADMUX,1 |
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273 | VADMUX2 avrbit VADMUX,2 |
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274 | VADMUX3 avrbit VADMUX,3 |
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275 | |||
276 | VADCSR sfr 0x7a ; Control and Status Register |
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277 | VADCCIE avrbit VADCSR,0 ; V-ADC Conversion Complete Interrupt Enable |
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278 | VADCCIF avrbit VADCSR,1 ; V-ADC Conversion Complete Interrupt Flag |
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279 | VADSC avrbit VADCSR,2 ; Voltage ADC Start Conversion |
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280 | VADEN avrbit VADCSR,3 ; V-ADC Enable |
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281 | |||
282 | VADCL sfr 0x78 ; V-ADC Data Register |
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283 | VADCH sfr 0x79 |
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284 | |||
285 | DIDR0 sfr 0x7e ; Digital Input Disable Register 0 |
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286 | VADC0D avrbit DIDR0,0 ; V-ADC0 Digital Input Disable |
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287 | VADC1D avrbit DIDR0,1 ; V-ADC1 Digital Input Disable |
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288 | VADC2D avrbit DIDR0,2 ; V-ADC2 Digital Input Disable |
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289 | VADC3D avrbit DIDR0,3 ; V-ADC3 Digital Input Disable |
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290 | |||
291 | ;---------------------------------------------------------------------------- |
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292 | ; FET Control |
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293 | |||
294 | FCSR sfr 0xf0 ; FET Control and Status Register |
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295 | PWMOC avrbit FCSR,5 ; Pulse Width Modulation of OC Output |
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296 | PWMOPC avrbit FCSR,4 ; Pulse Width Modulation of OPC Output |
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297 | CPS avrbit FCSR,3 ; Current Protection Status |
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298 | DFE avrbit FCSR,2 ; Discharge FET Enable |
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299 | CFE avrbit FCSR,1 ; Charge FET Enable |
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300 | PFD avrbit FCSR,0 ; Precharge FET Disable |
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301 | |||
302 | ;---------------------------------------------------------------------------- |
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303 | ; Cell Balancing |
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304 | |||
305 | CBCR sfr 0xf1 ; Cell Balancing Control Register |
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306 | CBE4 avrbit CBCR,3 ; Cell Balancing Enable 4 |
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307 | CBE3 avrbit CBCR,2 ; Cell Balancing Enable 3 |
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308 | CBE2 avrbit CBCR,1 ; Cell Balancing Enable 2 |
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309 | CBE1 avrbit CBCR,0 ; Cell Balancing Enable 1 |
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310 | |||
311 | ;---------------------------------------------------------------------------- |
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312 | ; Battery Protection |
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313 | |||
314 | BPPLR sfr 0xf8 ; Battery Protection Parameter Lock Register |
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315 | BPPLE avrbit BPPLR,1 ; Battery Protection Parameter Lock Enable |
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316 | BPPL avrbit BPPLR,0 ; Battery Protection Parameter Lock |
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317 | |||
318 | BPCR sfr 0xf7 ; Battery Protection Control Register |
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319 | DUVD avrbit BPCR,3 ; Deep Under-Voltage Protection Disable |
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320 | SCD avrbit BPCR,2 ; Short Circuit Protection Disabled |
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321 | DCD avrbit BPCR,1 ; Discharge Over-Current Protection Disable |
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322 | CCD avrbit BPCR,0 ; Charge Over-Current Protection Disable |
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323 | |||
324 | CBPTR sfr 0xf6 ; Current Battery Protection Timing Register |
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325 | SCPT3 avrbit CBPTR,7 ; Short-Circuit Protection Timing |
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326 | SCPT2 avrbit CBPTR,6 |
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327 | SCPT1 avrbit CBPTR,5 |
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328 | SCPT0 avrbit CBPTR,4 |
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329 | OCPT3 avrbit CBPTR,3 ; Over-Current Protection Timing |
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330 | OCPT2 avrbit CBPTR,2 |
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331 | OCPT1 avrbit CBPTR,1 |
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332 | OCPT0 avrbit CBPTR,0 |
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333 | |||
334 | BPOCD sfr 0xf5 ; Battery Protection Over-Current Detection Level Register |
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335 | DCDL3 avrbit BPOCD,7 ; Discharge Over-Current Detection Level |
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336 | DCDL2 avrbit BPOCD,6 |
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337 | DCDL1 avrbit BPOCD,5 |
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338 | DCDL0 avrbit BPOCD,4 |
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339 | CCDL3 avrbit BPOCD,3 ; Charge Over-Current Detection Level |
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340 | CCDL2 avrbit BPOCD,2 |
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341 | CCDL1 avrbit BPOCD,1 |
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342 | CCDL0 avrbit BPOCD,0 |
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343 | |||
344 | BPSCD sfr 0xf4 ; Battery Protection Short-Circuit Detection Level Register |
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345 | SCDL3 avrbit BPSCD,3 ; Short-Circuit Detection Level |
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346 | SCDL2 avrbit BPSCD,2 |
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347 | SCDL1 avrbit BPSCD,1 |
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348 | SCDL0 avrbit BPSCD,0 |
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349 | |||
350 | BPDUV sfr 0xf3 ; Battery Protection Deep Under Voltage Register |
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351 | DUVT1 avrbit BPDUV,5 ; Deep Under-Voltage Timing |
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352 | DUVT0 avrbit BPDUV,4 |
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353 | DUDL3 avrbit BPDUV,3 ; Deep Under-Voltage Detection Level |
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354 | DUDL2 avrbit BPDUV,2 |
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355 | DUDL1 avrbit BPDUV,1 |
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356 | DUDL0 avrbit BPDUV,0 |
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357 | |||
358 | BPIR sfr 0xf2 ; Battery Protection Interrupt Register |
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359 | DUVIF avrbit BPIR,7 ; Deep Under-Voltage Early Warning Interrupt Flag |
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360 | COCIF avrbit BPIR,6 ; Charge Over-Current Protection Activated Interrupt Flag |
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361 | DOCIF avrbit BPIR,5 ; Discharge Over-Current Protection Activated Interrupt Flag |
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362 | SCIF avrbit BPIR,4 ; Short-Circuit Protection Activated Interrupt Flag |
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363 | DUVIE avrbit BPIR,3 ; Deep Under-Voltage Early Warning Interrupt Enable |
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364 | COCIE avrbit BPIR,2 ; Charge Over-Current Protection Activated Interrupt Enable |
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365 | DOCIE avrbit BPIR,1 ; Discharge Over-Current Protection Activated Interrupt Enable |
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366 | SCIE avrbit BPIR,0 ; Short-Circuit Protection Activated Interrupt Enable |
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367 | |||
368 | restore ; re-enable listing |
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369 | |||
370 | endif ; __regm406inc |