WebSVN – pentevo – Blame – /tools/asl/asl-current/include/coldfire/mcf5329.inc

Rev	Author	Line No.	Line
1186	savelij	1	ifndef __mcf5329inc ; avoid multiple inclusion
		2	__mcf5329inc equ 1
		3
		4	save
		5	listing off ; no listing over this file
		6
		7	;****************************************************************************
		8	;* *
		9	;* AS 1.42 - File MCF5329.INC *
		10	;* *
		11	;* Contains SFR and Bit Definitions for ColdFire MCF5329 *
		12	;* *
		13	;****************************************************************************
		14
		15	MBAR equ $fc000000
		16
		17	;----------------------------------------------------------------------------
		18	; Clock Module
		19
		20	MBAR_CLK equ MBAR+$c0000
		21
		22	PODR equ MBAR_CLK+0 ; PLL Output Divider Register (8b)
		23	BUSDIV cffield PODR,0,4 ; Divider for generating the internal bus frequency
		24	CPUDIV cffield PODR,4,4 ; Divider for generating the core frequency
		25	PCR equ MBAR_CLK+4 ; PLL Control Register (8b)
		26	DITHEN cfbit PCR,7 ; Dithering enable bit
		27	DITHDEV cffield PCR,0,3 ; Dither Deviation
		28	PMDR equ MBAR_CLK+8 ; PLL Modulation Divider Register (8b)
		29	MODDIV cffield PMDR,0,8 ; Dither Modulation Divider
		30	PFDR equ MBAR_CLK+12 ; PLL Feedback Divider Register (8b)
		31	MFD cffield PFDR,0,8 ; Feedback Bits
		32
		33	;----------------------------------------------------------------------------
		34	; Power Management
		35
		36	WCR equ MBAR+$40013 ; Wakeup Control Register (8b)
		37	ENBWCR cfbit WCR,7 ; Enable low-power mode entry
		38	PRILVL cffield WCR,0,3 ; Exit low-power mode interrupt priority level
		39	PPMSR0 equ MBAR+$4002c ; Peripheral Power Management Set Register 0 (8b)
		40	SAMCD cfbit PPMSR0,6 ; Set all module clock disables
		41	SMCD cffield PPMSR0,0,6 ; Set module clock disable
		42	PPMCR0 equ MBAR+$4002d ; Peripheral Power Management Clear Register 0 (8b)
		43	CAMCD cfbit PPMCR0,6 ; Clear all module clock disables
		44	CMCD cffield PPMCR0,0,6 ; Clear module clock disable
		45	PPMSR1 equ MBAR+$4002e ; Peripheral Power Management Set Register 1 (8b)
		46	SAMCD cfbit PPMSR1,6 ; Set all module clock disables
		47	SMCD cffield PPMSR1,0,6 ; Set module clock disable
		48	PPMCR1 equ MBAR+$4002f ; Peripheral Power Management Clear Register 1 (8b)
		49	CAMCD cfbit PPMCR1,6 ; Clear all module clock disables
		50	CMCD cffield PPMCR1,0,6 ; Clear module clock disable
		51	PPMHR0 equ MBAR+$40030 ; Peripheral Power Management High Register 0 (32b)
		52	CD48 cfbit PPMHR0,16 ; PLL
		53	CD47 cfbit PPMHR0,15 ; SSI
		54	CD46 cfbit PPMHR0,14 ; SDRAM Controller
		55	CD45 cfbit PPMHR0,13 ; USB Host
		56	CD44 cfbit PPMHR0,12 ; USB On-the-Go
		57	CD43 cfbit PPMHR0,11 ; LCD Controller
		58	CD42 cfbit PPMHR0,10 ; Real Time Clock
		59	CD41 cfbit PPMHR0,9 ; GPIO Module
		60	CD40 cfbit PPMHR0,8 ; CCM, Reset Controller, Power Management
		61	CD38 cfbit PPMHR0,6 ; On-chip Watchdog Timer
		62	CD37 cfbit PPMHR0,5 ; Edge Port
		63	CD36 cfbit PPMHR0,4 ; PWM
		64	CD35 cfbit PPMHR0,3 ; PIT 3
		65	CD34 cfbit PPMHR0,2 ; PIT 2
		66	CD33 cfbit PPMHR0,1 ; PIT 1
		67	CD32 cfbit PPMHR0,0 ; PIT 0
		68	PPMLR0 equ MBAR+$40034 ; Peripheral Power Management Low Register 0 (32b)
		69	CD31 cfbit PPMLR0,31 ; DMA Timer 3
		70	CD30 cfbit PPMLR0,30 ; DMA Timer 2
		71	CD29 cfbit PPMLR0,29 ; DMA Timer 1
		72	CD28 cfbit PPMLR0,28 ; DMA Timer 0
		73	CD26 cfbit PPMLR0,26 ; UART2
		74	CD25 cfbit PPMLR0,25 ; UART1
		75	CD24 cfbit PPMLR0,24 ; UART0
		76	CD23 cfbit PPMLR0,23 ; QSPI
		77	CD22 cfbit PPMLR0,22 ; I2C
		78	CD21 cfbit PPMLR0,21 ; IACK
		79	CD19 cfbit PPMLR0,19 ; Interrupt Controller 1
		80	CD18 cfbit PPMLR0,18 ; Interrupt Controller 0
		81	CD17 cfbit PPMLR0,17 ; eDMA Controller
		82	CD12 cfbit PPMLR0,12 ; FEC
		83	CD8 cfbit PPMLR0,8 ; FlexCAN
		84	CD2 cfbit PPMLR0,2 ; FlexBus
		85	PPMHR1 equ MBAR+$40038 ; Peripheral Power Management High Register 1 (32b)
		86	CD34 cfbit PPMHR1,2 ; Random Number Generator
		87	CD33 cfbit PPMHR1,1 ; SKHA
		88	CD32 cfbit PPMHR1,0 ; MDHA
		89	LPCR equ MBAR+$a0007 ; Low-Power Control Register (8b)
		90	LPMD cffield LPCR,6,2 ; Low-power mode select
		91	FWKUP cfbit LPCR,5 ; Fast wake-up
		92	STPMD cffield LPCR,3,2 ; FB_CLK stop mode bits
		93	MISCCR equ MBAR+$a0010 ; Miscellaneous Control Register (16b)
		94	PLLLOCK cfbit MISCCR,13 ; PLL lock status
		95	LIMP cfbit MISCCR,12 ; Limp mode enable
		96	LCDCHEN cfbit MISCCR,8 ; LCDC internal clock enable.
		97	SSIPUE cfbit MISCCR,7 ; SSI RXD/TXD pull enable.
		98	SSIPUS cfbit MISCCR,6 ; SSI RXD/TXD pull select.
		99	TIMDMA cfbit MISCCR,5 ; Timer DMA mux selection.
		100	SSISRC cfbit MISCCR,4 ; SSI clock source.
		101	USBDIV cfbit MISCCR,1 ; USB clock divisor.
		102	USBSRC cfbit MISCCR,0 ; USB clock source.
		103	CDR equ MBAR+$a0012 ; Clock Divider Register (16b)
		104	LPDIV cffield CDR,8,4 ; Low power clock divider.
		105	SSIDIV cffield CDR,0,6 ; SSI baud clock divider.
		106
		107	;----------------------------------------------------------------------------
		108	; Chip Configuration Module
		109
		110	MBAR_CCM equ MBAR+$a0000
		111
		112	CCR equ MBAR_CCM+$4 ; Chip Configuration Register (16b)
		113	CSC cffield CCR,8,2 ; Chip select configuration field
		114	LIMP cfbit CCR,6 ; Limp mode
		115	LOAD cfbit CCR,5 ; Pad driver load
		116	BOOTPS cffield CCR,3,2 ; Boot port size
		117	OSCMODE cfbit CCR,2 ; Oscillator clock mode
		118	PLLMODE cfbit CCR,1 ; PLL clock mode
		119	RCON equ MBAR_CCM+$8 ; Reset Configuration Register (16b)
		120	CSC cfbit RCON,8,2 ; Chip select configuration field
		121	LIMP cfbit RCON,6 ; Limp mode
		122	LOAD cfbit RCON,5 ; Pad driver load
		123	BOOTPS cffield RCON,3,2 ; Boot port size
		124	OSCMODE cfbit RCON,2 ; Oscillator clock mode
		125	PLLMODE cfbit RCON,1 ; PLL clock mode
		126	CIR equ MBAR_CCM+$a ; Chip Identification Register (16b)
		127	PIN cffield CIR,6,10 ; Part identification number
		128	PRN cffield CIR,0,6 ; Part revision number
		129
		130	;----------------------------------------------------------------------------
		131	; Reset Controller Module
		132
		133	MBAR_RCM equ MBAR+$a0000
		134	RCR equ MBAR_RCM+0 ; Reset Control Register (8b)
		135	SOFTRST cfbit RCR,7 ; Allows software to request a reset
		136	FRCRSTOUT cfbit RCR,6 ; Allows software to assert or negate the external /RSTOUT pin
		137	RSR equ MBAR_RCM+1 ; Reset Status Register (8b)
		138	SOFT cfbit RSR,5 ; Software reset flag
		139	WDRCHIP cfbit RSR,4 ; On-chip watchdog timer reset flag
		140	POR cfbit RSR,3 ; Power-on reset flag
		141	EXT cfbit RSR,2 ; External reset flag
		142	WDRCORE cfbit RSR,1 ; Core watchdog timer reset flag
		143	LOL cfbit RSR,0 ; Loss-of-lock reset flag
		144
		145	;----------------------------------------------------------------------------
		146	; System Control Module
		147
		148	MBAR_SCM equ MBAR+$0000
		149
		150	__defprot macro {INTLABEL},Reg,Startbit
		151	__LABEL__ cffield Reg,Startbit,4
		152	__LABEL__.MTR cfbit Reg,Startbit+0 ; Master trusted for read
		153	__LABEL__.MTW cfbit Reg,Startbit+1 ; Master trusted for writes
		154	__LABEL__.MPL cfbit Reg,Startbit+2 ; Master privilege level
		155	endm
		156	MPR1 equ $ec000000 ; Master Privilege Register 1 (32b)
		157	MPROT0 __defprot MPR1,28 ; MDHA
		158	MPROT1 __defprot MPR1,24 ; SKHA
		159	MPROT2 __defprot MPR1,20 ; RNG
		160	MPROT4 __defprot MPR1,12
		161	MPROT5 __defprot MPR1,8
		162	MPROT6 __defprot MPR1,4
		163	MPR0 equ MBAR_SCM+0 ; Master Privilege Register 0 (32b)
		164	MPROT0 __defprot MPR0,28 ; ColdFire Core
		165	MPROT1 __defprot MPR0,24 ; eDMA Controller
		166	MPROT2 __defprot MPR0,20 ; FEC
		167	MPROT4 __defprot MPR0,12 ; LCD Controller
		168	MPROT5 __defprot MPR0,8 ; USB Host
		169	MPROT6 __defprot MPR0,4 ; USB On-the-Go
		170
		171	__defpacr macro {INTLABEL},Reg,Startbit
		172	__LABEL__ cffield Reg,Startbit,4
		173	__LABEL__.TP cfbit Reg,Startbit+0 ; Trusted Protect
		174	__LABEL__.WP cfbit Reg,Startbit+1 ; Write protect
		175	__LABEL__.SP cfbit Reg,Startbit+2 ; Supervisor protect.
		176	endm
		177	PACRA equ MBAR_SCM+$20 ; Peripheral Access Control Register A (32b)
		178	PACR0 __defpacr PACRA,28 ; SCM (MPR & PACRs)
		179	PACR1 __defpacr PACRA,24 ; Cross-Bar Switch
		180	PACR2 __defpacr PACRA,20 ; FlexBus
		181	PACRB equ MBAR_SCM+$24 ; Peripheral Access Control Register B (32b)
		182	PACR8 __defpacr PACRB,28 ; FlexCAN
		183	PACR12 __defpacr PACRB,12 ; FEC
		184	PACRC equ MBAR_SCM+$28 ; Peripheral Access Control Register C (32b)
		185	PACR16 __defpacr PACRC,28 ; SCM (CWT & Core Fault Registers)
		186	PACR17 __defpacr PACRC,24 ; eDMA Controller
		187	PACR18 __defpacr PACRC,20 ; Interrupt Controller 0
		188	PACR19 __defpacr PACRC,16 ; Interrupt Controller 1
		189	PACR21 __defpacr PACRC,8 ; Interrupt Controller IACK
		190	PACR22 __defpacr PACRC,4 ; I2C
		191	PACR23 __defpacr PACRC,0 ; QSPI
		192	PACRD equ MBAR_SCM+$2C ; Peripheral Access Control Register D (32b)
		193	PACR24 __defpacr PACRD,28 ; UART0
		194	PACR25 __defpacr PACRD,24 ; UART1
		195	PACR26 __defpacr PACRD,20 ; UART2
		196	PACR28 __defpacr PACRD,12 ; DMA Timer 0
		197	PACR29 __defpacr PACRD,8 ; DMA Timer 1
		198	PACR30 __defpacr PACRD,4 ; DMA Timer 2
		199	PACR31 __defpacr PACRD,0 ; DMA Timer 3
		200	PACRE equ MBAR_SCM+$40 ; Peripheral Access Control Register E (32b)
		201	PACR32 __defpacr PACRE,28 ; PIT 0
		202	PACR33 __defpacr PACRE,24 ; PIT 1
		203	PACR34 __defpacr PACRE,20 ; PIT 2
		204	PACR35 __defpacr PACRE,16 ; PIT 3
		205	PACR36 __defpacr PACRE,12 ; PWM
		206	PACR37 __defpacr PACRE,8 ; Edge Port
		207	PACR38 __defpacr PACRE,4 ; On-chip Watchdog Timer
		208	PACRF equ MBAR_SCM+$44 ; Peripheral Access Control Register F (32b)
		209	PACR40 __defpacr PACRF,28 ; CCM, Reset Controller, Power Management
		210	PACR41 __defpacr PACRF,24 ; GPIO Module
		211	PACR42 __defpacr PACRF,20 ; Real Time Clock
		212	PACR43 __defpacr PACRF,16 ; LCD Controller
		213	PACR44 __defpacr PACRF,12 ; USB On-the-Go
		214	PACR45 __defpacr PACRF,8 ; USB Host
		215	PCAR46 __defpacr PACRF,4 ; SDRAM Controller
		216	PACR47 __defpacr PACRF,0 ; SSI
		217	PACRG equ MBAR_SCM*48 ; Peripheral Access Control Register G (32b)
		218	PACR48 __defpacr PACRG,28 ; PLL
		219	PACRH equ $ec000040 ; Peripheral Access Control Register H (32b)
		220	PACR56 __defpacr PACRH,28 ; MDHA
		221	PACR57 __defpacr PACRH,24 ; SKHA
		222	PACR58 __defpacr PACRH,20 ; RNG
		223	BMT1 equ $ec000054 ; Bus Monitor Timeout 1 (32b)
		224	BMT cffield BMT1,0,3 ; Bus Monitor Timeout Period
		225	BME cfbit BMT1,3 ; Bus Monitor Timeout Enable
		226	BMT0 equ MBAR_SCM+$54 ; Bus Monitor Timeout 0 (32b)
		227	BMT cffield BMT0,0,3 ; Bus Monitor Timeout Period
		228	BME cfbit BMT0,3 ; Bus Monitor Timeout Enable
		229	CWCR equ MBAR_SCM+$40016 ; Core Watchdog Control Register (16b)
		230	RO cfbit CWCR,15 ; Read-Only Control
		231	CWRWH cfbit CWCR,8 ; Core Watchdog run while halted
		232	CWE cfbit CWCR,7 ; Core Watchdog Timer Enable
		233	CWRI cffield CWCR,5,2 ; Core Watchdog Reset/Interrupt
		234	CWT cffield CWCR,0,5 ; Core Watchdog Time-Out Period
		235	CWSR equ MBAR_SCM+$4001B ; Core Watchdog Service Register (8b)
		236	SCMISR equ MBAR_SCM+$4001F ; SCM Interrupt Status Register (8b)
		237	CFEI cfbit SCMISR,1 ; Core Fault Error Interrupt Flag
		238	CWIC cfbit SCMISR,0 ; Core Watchdog Interrupt Flag
		239	BCR equ MBAR_SCM+$40024 ; Burst Configuration Register (32b)
		240	GBR cfbit BCR,9 ; Global burst enable for reads.
		241	GBW cfbit BCR,8 ; Global burst enable for writes.
		242	SBE cffield BCR,0,8 ; Slave burst enable.
		243	CFADR equ MBAR_SCM+$40070 ; Core Fault Address Register (32b)
		244	CFIER equ MBAR_SCM+$40075 ; Core Fault Interrupt Enable Register (8b)
		245	ECFEI cfbit CFIER,0 ; Enable Core Fault Error Interrupt
		246	CFLOC equ MBAR_SCM+$40076 ; Core Fault Location Register (8b)
		247	LOC cfbit CFLOC,7 ; Location of the last captured fault
		248	CFATR equ MBAR_SCM+$40077 ; Core Fault Attributes Register (8b)
		249	WRITE cfbit CFATR,7 ; Direction of the last faulted core access
		250	SIZE cffield CFATR,4,2 ; Size of the last faulted core access
		251	CACHE cfbit CFATR,3 ; Indicates if last faulted core access was cacheable
		252	MODE cfbit CFATR,1 ; Indicates the mode the device was in during the last faulted core access
		253	TYPE cfbit CFATR,0 ; Defines the type of last faulted core access
		254	CFDTR equ MBAR_SCM+$4007C ; Core Fault Data Register (32b)
		255
		256	;----------------------------------------------------------------------------
		257	; Crossbar Switch
		258
		259	MBAR_XBS equ MBAR+$4000
		260	__defxbs macro n,Base
		261	XBS_PRS{n} equ Base+$00 ; Priority Register (32b)
		262	M7 cffield XBS_PRS{n},28,3 ; Master 7 (Factory Test) Priority
		263	M6 cffield XBS_PRS{n},24,3 ; Master 6 (USB OTG) Priority
		264	M5 cffield XBS_PRS{n},20,3 ; Master 5 (USB Host) Priority
		265	M4 cffield XBS_PRS{n},16,3 ; Master 4 (LCD Controller) Priority
		266	M2 cffield XBS_PRS{n},8,3 ; Master 2 (FEC) Priority
		267	M1 cffield XBS_PRS{n},4,3 ; Master 1 (eDMA) Priority
		268	M0 cffield XBS_PRS{n},0,3 ; Master 0 (ColdFire core) Priority
		269	XBS_CRS{n} equ Base+$10 ; Control Register (32b)
		270	RO cfbit XBS_CRS{n},31 ; Read Only
		271	ARB cfbit XBS_CRS{n},8 ; Arbitration Mode
		272	PCTL cffield XBS_CRS{n},4,2 ; Parking Control
		273	PARK cffield XBS_CRS{n},0,3 ; Park
		274	endm
		275	__defxbs "1",MBAR_XBS+$100
		276	__defxbs "4",MBAR_XBS+$400
		277	__defxbs "6",MBAR_XBS+$600
		278	__defxbs "7",MBAR_XBS+$700
		279
		280	;----------------------------------------------------------------------------
		281	; General Purpose I/O
		282
		283	MBAR_GPIO equ MBAR+$a4000
		284
		285	; Port Output Data Registers
		286
		287	PODR_FECH equ MBAR_GPIO+$000 ; FEC High Output Data Register (8b)
		288	PODR_FECL equ MBAR_GPIO+$001 ; FEC Low Output Data Register (8b)
		289	PODR_SSI equ MBAR_GPIO+$002 ; SSI Output Data Register (8b)
		290	PODR_BUSCTL equ MBAR_GPIO+$003 ; Bus Control Output Data Register (8b)
		291	PODR_BE equ MBAR_GPIO+$004 ; Byte Enable Output Data Register (8b)
		292	PODR_CS equ MBAR_GPIO+$005 ; Chip Select Output Data Register (8b)
		293	PODR_PWM equ MBAR_GPIO+$006 ; PWM Output Data Register (8b)
		294	PODR_FECI2C equ MBAR_GPIO+$007 ; FEC/I2C Output Data Register (8b)
		295	PODR_UART equ MBAR_GPIO+$009 ; UART Output Data Register (8b)
		296	PODR_QSPI equ MBAR_GPIO+$00a ; QSPI Output Data Register (8b)
		297	PODR_TIMER equ MBAR_GPIO+$00b ; Timer Output Data Register (8b)
		298	PODR_LCDDATAH equ MBAR_GPIO+$00d ; LCD Data Hi Output Data Register (8b)
		299	PODR_LCDDATAM equ MBAR_GPIO+$00e ; LCD Data Mid Output Data Register (8b)
		300	PODR_LCDDATAL equ MBAR_GPIO+$00f ; LCD Data Low Output Data Register (8b)
		301	PODR_LCDCTLH equ MBAR_GPIO+$010 ; LCD Hi Output Data Register (8b)
		302	PODR_LCDCTLL equ MBAR_GPIO+$011 ; LCD Low Output Data Register (8b)
		303
		304	; Port Data Direction Registers
		305
		306	PDDR_FECH equ MBAR_GPIO+$014 ; FEC High Data Direction Register (8b)
		307	PDDR_FECL equ MBAR_GPIO+$015 ; FEC Low Data Direction Register (8b)
		308	PDDR_SSI equ MBAR_GPIO+$016 ; SSI Data Direction Register (8b)
		309	PDDR_BUSCTL equ MBAR_GPIO+$017 ; Bus Control Data Direction Register (8b)
		310	PDDR_BE equ MBAR_GPIO+$018 ; Byte Enable Data Direction Register (8b)
		311	PDDR_CS equ MBAR_GPIO+$019 ; Chip Select Data Direction Register (8b)
		312	PDDR_PWM equ MBAR_GPIO+$01a ; PWM Data Direction Register (8b)
		313	PDDR_FECI2C equ MBAR_GPIO+$01b ; FEC/I2C Data Direction Register (8b)
		314	PDDR_UART equ MBAR_GPIO+$01d ; UART Data Direction Register (8b)
		315	PDDR_QSPI equ MBAR_GPIO+$01e ; QSPI Data Direction Register (8b)
		316	PDDR_TIMER equ MBAR_GPIO+$01f ; Timer Data Direction Register (8b)
		317	PDDR_LCDDATAH equ MBAR_GPIO+$021 ; LCD Data Hi Data Direction Register (8b)
		318	PDDR_LCDDATAM equ MBAR_GPIO+$022 ; LCD Data Mid Data Direction Register (8b)
		319	PDDR_LCDDATAL equ MBAR_GPIO+$023 ; LCD Data Low Data Direction Register (8b)
		320	PDDR_LCDCTLH equ MBAR_GPIO+$024 ; LCD Hi Output Data Data Direction Register (8b)
		321	PDDR_LCDCTLL equ MBAR_GPIO+$025 ; LCD Low Output Data Data Direction Register (8b)
		322
		323	; Port Pin Data/Set Data Registers
		324
		325	PPDSDR_FECH equ MBAR_GPIO+$028 ; FEC High Pin Data/Set Data Register (8b)
		326	PPDSDR_FECL equ MBAR_GPIO+$029 ; FEC Low Pin Data/Set Data Register (8b)
		327	PPDSDR_SSI equ MBAR_GPIO+$02a ; SSI Pin Data/Set Data Register (8b)
		328	PPDSDR_BUSCTL equ MBAR_GPIO+$02b ; Bus Control Pin Data/Set Data Register (8b)
		329	PPDSDR_BE equ MBAR_GPIO+$02c ; Byte Enable Pin Data/Set Data Register (8b)
		330	PPDSDR_CS equ MBAR_GPIO+$02d ; Chip Select Pin Data/Set Data Register (8b)
		331	PPDSDR_PWM equ MBAR_GPIO+$02e ; PWM Pin Data/Set Data Register (8b)
		332	PPDSDR_FECI2C equ MBAR_GPIO+$02f ; FEC/I2C Pin Data/Set Data Register (8b)
		333	PPDSDR_UART equ MBAR_GPIO+$031 ; UART Pin Data/Set Data Register (8b)
		334	PPDSDR_QSPI equ MBAR_GPIO+$032 ; QSPI Pin Data/Set Data Register (8b)
		335	PPDSDR_TIMER equ MBAR_GPIO+$033 ; Timer Pin Data/Set Data Register (8b)
		336	PPDSDR_LCDDATAH equ MBAR_GPIO+$035 ; LCD Data Hi Pin Data/Set Data Register (8b)
		337	PPDSDR_LCDDATAM equ MBAR_GPIO+$036 ; LCD Data Mid Pin Data/Set Data Register (8b)
		338	PPDSDR_LCDDATAL equ MBAR_GPIO+$037 ; LCD Data Low Pin Data/Set Data Register (8b)
		339	PPDSDR_LCDCTLH equ MBAR_GPIO+$038 ; LCD Hi Pin Data/Set Data Register (8b)
		340	PPDSDR_LCDCTLL equ MBAR_GPIO+$039 ; LCD Low Pin Data/Set Data Register (8b)
		341
		342	; Port Clear Output Data Registers
		343
		344	PCLRR_FECH equ MBAR_GPIO+$03c ; FEC High Clear Output Data Register (8b)
		345	PCLRR_FECL equ MBAR_GPIO+$03d ; FEC Low Clear Output Data Register (8b)
		346	PCLRR_SSI equ MBAR_GPIO+$03e ; SSI Output Data Register (8b)
		347	PCLRR_BUSCTL equ MBAR_GPIO+$03f ; Bus Control Clear Output Data Register (8b)
		348	PCLRR_BE equ MBAR_GPIO+$040 ; Byte Enable Clear Output Data Register (8b)
		349	PCLRR_CS equ MBAR_GPIO+$041 ; Chip Select Clear Output Data Register (8b)
		350	PCLRR_PWM equ MBAR_GPIO+$042 ; PWM Output Data Register (8b)
		351	PCLRR_FECI2C equ MBAR_GPIO+$043 ; FEC/I2C Clear Output Data Register (8b)
		352	PCLRR_UART equ MBAR_GPIO+$045 ; UART Clear Output Data Register (8b)
		353	PCLRR_QSPI equ MBAR_GPIO+$046 ; QSPI Clear Output Data Register (8b)
		354	PCLRR_TIMER equ MBAR_GPIO+$047 ; Timer Clear Output Data Register (8b)
		355	PCLRR_LCDDATAH equ MBAR_GPIO+$049 ; LCD Data Hi Output Data Register (8b)
		356	PCLRR_LCDDATAM equ MBAR_GPIO+$04a ; LCD Data Mid Output Data Register (8b)
		357	PCLRR_LCDDATAL equ MBAR_GPIO+$04b ; LCD Data Low Output Data Register (8b)
		358	PCLRR_LCDCTLH equ MBAR_GPIO+$04c ; LCD Hi Output Data Register (8b)
		359	PCLRR_LCDCTLL equ MBAR_GPIO+$04d ; LCD Low Output Data Register (8b)
		360
		361	; Pin Assignment Registers
		362
		363	PAR_FEC equ MBAR_GPIO+$050 ; FEC Pin Assignment (8b)
		364	PAR_FEC_7W cffield PAR_FEC,2,2 ; FEC 7-wire Pin Assignment
		365	PAR_FEC_MII cffield PAR_FEC,0,2 ; FEC MII Pin Assignment
		366	PAR_PWM equ MBAR_GPIO+$051 ; PWM Pin Assignment (8b)
		367	PAR_PWM7 cfbit PAR_PWM,5 ; PWM7 pin assignment.
		368	PAR_PWM5 cfbit PAR_PWM,4 ; PWM5 pin assignment.
		369	PAR_PWM3 cffield PAR_PWM,2,2 ; PWM3 pin assignment.
		370	PAR_PWM1 cffield PAR_PWM,0,2 ; PWM1 pin assignment.
		371	PAR_BUSCTL equ MBAR_GPIO+$052 ; External Bus Control Pin Assignment Register (8b)
		372	PAR_OE cfbit PAR_BUSCTL,7 ; /OE Pin Assignment
		373	PAR_TA cfbit PAR_BUSCTL,6 ; /TA Pin Assignment
		374	PAR_RWB cfbit PAR_BUSCTL,5 ; R/-W Pin Assignment
		375	PAR_TS cffield PAR_BUSCTL,3,2 ; /TS Pin Assignment
		376	PAR_FECI2C equ MBAR_GPIO+$053 ; FEC/I2C Pin Assignment (8b)
		377	PAR_MDC cffield PAR_FECI2C,6,2 ; MDC Pin Assignment
		378	PAR_MDIO cffield PAR_FECI2C,4,2 ; MDIO Pin Assignment
		379	PAR_SCL cffield PAR_FECI2C,2,2 ; SCL Pin Assignment
		380	PAR_SDA cffield PAR_FECI2C,0,2 ; SDA Pin Assignment
		381	PAR_BE equ MBAR_GPIO+$054 ; Byte Enable Pin Assignment Register (8b)
		382	PAR_BE cffield PAR_BE,0,4 ; Byte Enable Pin Assignment
		383	PAR_CS equ MBAR_GPIO+$055 ; Chip Select Pin Assignment Register (8b)
		384	PAR_CS3 cfbit PAR_CS,3 ; /FB_CS3 Pin Assignment
		385	PAR_CS2 cfbit PAR_CS,2 ; /FB_CS2 Pin Assignment
		386	PAR_CS1 cffield PAR_CS,0,2 ; /FB_CS1 Pin Assignment
		387	PAR_SSI equ MBAR_GPIO+$056 ; SSI Pin Assignment (16b)
		388	PAR_BCLK cffield PAR_SSI,14,2 ; BCLK Pin Assignment
		389	PAR_FS cffield PAR_SSI,12,2 ; FS Pin Assignment
		390	PAR_RXD cffield PAR_SSI,10,2 ; RxD Pin Assignment
		391	PAR_TXD cffield PAR_SSI,8,2 ; TxD Pin Assignment
		392	PAR_MCLK cfbit PAR_SSI,7 ; MCLK Pin Assignment
		393	PAR_UART equ MBAR_GPIO+$058 ; UART Pin Assignment (16b)
		394	PAR_U1CTS cffield PAR_UART,10,2 ; UART1 CTS Pin Assignment
		395	PAR_U1RTS cffield PAR_UART,8,2 ; UART1 RTS Pin Assignment
		396	PAR_U1RXD cffield PAR_UART,6,2 ; UART1 RXD Pin Assignment
		397	PAR_U1TXD cffield PAR_UART,4,2 ; UART1 TXD Pin Assignment
		398	PAR_U0CTS cfbit PAR_UART,3 ; UART0 CTS Pin Assignment
		399	PAR_U0RTS cfbit PAR_UART,2 ; UART0 RTS Pin Assignment
		400	PAR_U0RXD cfbit PAR_UART,1 ; UART0 RXD Pin Assignment
		401	PAR_U0TXD cfbit PAR_UART,0 ; UART0 TXD Pin Assignment
		402	PAR_QSPI equ MBAR_GPIO+$05a ; QSPI Pin Assignment (16b)
		403	PAR_PCS2 cffield PAR_QSPI,14,2 ; QSPI Pin Assignment
		404	PAR_PCS1 cffield PAR_QSPI,12,2
		405	PAR_PCS0 cffield PAR_QSPI,10,2
		406	PAR_DIN cffield PAR_QSPI,8,2
		407	PAR_DOUT cffield PAR_QSPI,6,2
		408	PAR_SCK cffield PAR_QSPI,4,2
		409	PAR_TIMER equ MBAR_GPIO+$05c ; Timer Pin Assignment (8b)
		410	PAR_T3IN cffield PAR_TIMER,6,2 ; DMA Timer 3 Pin Assignment
		411	PAR_T2IN cffield PAR_TIMER,4,2 ; DMA Timer 2 Pin Assignment
		412	PAR_T1IN cffield PAR_TIMER,2,2 ; DMA Timer 1 Pin Assignment
		413	PAR_T0IN cffield PAR_TIMER,0,2 ; DMA Timer 0 Pin Assignment
		414	PAR_LCDDATA equ MBAR_GPIO+$05d ; LCD Data Pin Assignment (8b)
		415	PAR_LD17 cffield PAR_LCDDATA,6,2 ; LCD data pin assignment.
		416	PAR_LD16 cffield PAR_LCDDATA,4,2
		417	PAR_LD15_8 cffield PAR_LCDDATA,2,2
		418	PAR_LD7_0 cffield PAR_LCDDATA,0,2
		419	PAR_LCDCTL equ MBAR_GPIO+$05e ; LCD Pin Assignment (16b)
		420	PAR_ACD_OE cfbit PAR_LCDCTL,8 ; LCD_ACD/OE pin assignment.
		421	PAR_FLM_VSYNC cfbit PAR_LCDCTL,7 ; LCD_FLM/VSYNC pin assignment.
		422	PAR_LP_HSYNC cfbit PAR_LCDCTL,6 ; LCD_LP/HSYNC pin assignment.
		423	PAR_LSCLK cfbit PAR_LCDCTL,5 ; LCD_LSCLK pin assignment.
		424	PAR_CONTRAST cfbit PAR_LCDCTL,4 ; LCD_CONTRAST pin assignment.
		425	PAR_SPL_SPR cfbit PAR_LCDCTL,3 ; LCD_SPL_SPR pin assignment.
		426	PAR_REV cfbit PAR_LCDCTL,2 ; LCD_REV pin assignment.
		427	PAR_PS cfbit PAR_LCDCTL,1 ; LCD_PS pin assignment.
		428	PAR_CLS cfbit PAR_LCDCTL,0 ; LCD_CLS pin assignment.
		429	PAR_IRQ equ MBAR_GPIO+$060 ; IRQ Pin Assignment (16b)
		430	PAR_IRQ6 cffield PAR_IRQ,12,2 ; /IRQ6 Pin Assignment
		431	PAR_IRQ5 cffield PAR_IRQ,10,2 ; /IRQ5 Pin Assignment
		432	PAR_IRQ4 cffield PAR_IRQ,8,2 ; /IRQ4 Pin Assignment
		433	PAR_IRQ2 cffield PAR_IRQ,6,2 ; /IRQ2 Pin Assignment
		434	PAR_IRQ1 cffield PAR_IRQ,4,2 ; /IRQ1 Pin Assignment
		435
		436	; Mode Select Control Registers
		437
		438	MSCR_FLEXBUS equ MBAR_GPIO+$064 ; FlexBus Mode Select Control Register (8b)
		439	MSCR_DUPPER cffield MSCR_FLEXBUS,4,2; FB_D[31:16] Mode Select Control
		440	MSCR_DLOWER cffield MSCR_FLEXBUS,2,2; FB_D[15:0] Mode Select Control
		441	MSCR_ADDRCTL cffield MSCR_FLEXBUS,0,2; FB_A[23:0], BE/BWE[3:0], OE, R/W, FB_CS[5:0], TA, and TS Mode Select Control
		442	MSCR_SDRAM equ MBAR_GPIO+$065 ; SDRAM Mode Select Control Register (8b)
		443	MSCR_SDCLKB cffield MSCR_SDRAM,4,2 ; SD_CLK Mode Select Control
		444	MSCR_SDCLK cffield MSCR_SDRAM,2,2 ; SD_CLK Mode Select Control
		445	MSCR_SDRAM cffield MSCR_SDRAM,0,2 ; SD_A10, SD_CAS, SD_CKE, SD_CS0, SD_DQS[3:2], SD_RAS, SD_SDRDQS, SD_WE Mode Select Control
		446
		447	; Drive Strength Control Registers
		448
		449	DSCR_I2C equ MBAR_GPIO+$068 ; I2C Drive Strength Control Register (8b)
		450	I2C_DSE cffield DSCR_I2C,0,2 ; I2C Drive Strength Control
		451	DSCR_PWM equ MBAR_GPIO+$069 ; PWM Drive Strength Control Register (8b)
		452	PWM_DSE cffield DSCR_PWM,0,2 ; PWM Drive Strength Control
		453	DSCR_FEC equ MBAR_GPIO+$06a ; FEC Drive Strength Control Register (8b)
		454	FEC_DSE cffield DSCR_FEC,0,2 ; FEC Drive Strength Control
		455	DSCR_UART equ MBAR_GPIO+$06b ; UART/IRQ Drive Strength Control Register (8b)
		456	UART1_DSE cffield DSCR_UART,2,2 ; UART1 Drive Strength Control
		457	UART0_DSE cffield DSCR_UART,0,2 ; UART0 Drive Strength Control
		458	DSCR_QSPI equ MBAR_GPIO+$06c ; QSPI Drive Strength Control Register (8b)
		459	QSPI_DSE cffield DSCR_QSPI,0,2 ; QSPI Drive Strength Control
		460	DSCR_TIMER equ MBAR_GPIO+$06d ; Timer Drive Strength Control Register (8b)
		461	TIMER_DSE cffield DSCR_TIMER,0,2 ; Timer Drive Strength Control
		462	DSCR_SSI equ MBAR_GPIO+$06e ; SSI Drive Strength Control Register (8b)
		463	SSI_DSE cffield DSCR_SSI,0,2 ; SSI Drive Strength Control
		464	DSCR_LCD equ MBAR_GPIO+$06f ; LCD Drive Strength Control Register (8b)
		465	LCD_DSE cffield DSCR_LCD,0,2 ; LCD Drive Strength Control
		466	DSCR_DEBUG equ MBAR_GPIO+$070 ; Debug Drive Strength Control Register (8b)
		467	DEBUG_DSE cffield DSCR_DEBUG,0,2 ; Debug Drive Strength Control
		468	DSCR_CLKRST equ MBAR_GPIO+$071 ; Clock/Reset Drive Strength Control Register (8b)
		469	RSTOUT_DSE cffield DSCR_CLKRST,2,2 ; /RSTOUT drive strength control.
		470	MSCR_FBCLK cffield DSCR_CLKRST,0,2 ; FB_CLK mode select control.
		471	DSCR_IRQ equ MBAR_GPIO+$072 ; IRQ Drive Strength Control Register (8b)
		472	IRW_DSE cffield DSCR_IRQ,0,2 ; IRQ Drive Strength Control
		473
		474	;----------------------------------------------------------------------------
		475	; Interrupt Controllers
		476
		477	MBAR_INTC0 equ MBAR+$48000
		478	MBAR_INTC1 equ MBAR+$4c000
		479	MBAR_INTC equ MBAR+$54000
		480	include "52xxintc.inc"
		481
		482	;----------------------------------------------------------------------------
		483	; Edge Port Module
		484
		485	MBAR_EPORT equ MBAR+$94000
		486	include "52xxeport.inc"
		487
		488	;----------------------------------------------------------------------------
		489	; Enhanced DMA Controller
		490
		491	MBAR_EDMA equ MBAR+$44000
		492	include "52xxedma.inc"
		493
		494	;----------------------------------------------------------------------------
		495	; FlexBus
		496
		497	MBAR_FBUS equ MBAR+$8000
		498	include "52xxfbus.inc"
		499
		500	;----------------------------------------------------------------------------
		501	; SDRAM Controller
		502
		503	MBAR_SDRAM equ MBAR+$b8000
		504	include "52xxdram.inc"
		505
		506	;----------------------------------------------------------------------------
		507	; Fast Ethernet Controller
		508
		509	MBAR_FEC equ MBAR+$30000
		510	include "52xxfec.inc"
		511
		512	;----------------------------------------------------------------------------
		513	; USB Host/On-the-Go
		514
		515	include "52xxusb.inc"
		516	MBAR_USB equ MBAR+$b4000
		517	__defusb "USB.",MBAR_USB
		518	MBAR_OTG equ MBAR+$b0000
		519	__defusb "OTG.",MBAR_OTG
		520
		521	;----------------------------------------------------------------------------
		522	; LCD Controller
		523
		524	MBAR_LCDC equ $ac000
		525	include "52xxlcdc.inc"
		526
		527	;----------------------------------------------------------------------------
		528	; FlexCAN
		529
		530	MBAR_CAN equ MBAR+$20000
		531
		532	include "52xxcan.inc"
		533
		534	;----------------------------------------------------------------------------
		535	; Synchronous Serial Interface
		536
		537	MBAR_SSI equ MBAR+$bc000
		538	include "52xxssi.inc"
		539
		540	;----------------------------------------------------------------------------
		541	; Real Time Clock
		542
		543	MBAR_RTC equ MBAR+$a8000
		544	include "52xxrtc.inc"
		545	XTL cffield RTC_CR,5,2 ; Crystal selection.
		546
		547	;----------------------------------------------------------------------------
		548	; Pulse-Width Modulation Module
		549
		550	MBAR_PWM equ MBAR+$90000
		551	include "52xxpwm.inc"
		552
		553	;----------------------------------------------------------------------------
		554	; Watchdog Timer
		555
		556	MBAR_WDT equ MBAR+$98000
		557	include "52xxwdt.inc"
		558
		559	;----------------------------------------------------------------------------
		560	; Programmable Interrupt Timer
		561
		562	include "52xxpit.inc"
		563	__defpit "0",MBAR+$80000
		564	__defpit "1",MBAR+$84000
		565	__defpit "2",MBAR+$88000
		566	__defpit "3",MBAR+$8c000
		567
		568	;----------------------------------------------------------------------------
		569	; DMA Timer
		570
		571	include "52xxdtim.inc"
		572	__defdtim "0",MBAR+$70000
		573	__defdtim "1",MBAR+$74000
		574	__defdtim "2",MBAR+$78000
		575	__defdtim "3",MBAR+$7c000
		576
		577	;----------------------------------------------------------------------------
		578	; Queued Serial Peripheral Interface
		579
		580	MBAR_QSPI equ MBAR+$5c000
		581	include "52xxqspi.inc"
		582
		583	;----------------------------------------------------------------------------
		584	; UARTs
		585
		586	include "52xxuart.inc"
		587	__defuart "0",MBAR+$60000
		588	__defuart "1",MBAR+$64000
		589	__defuart "2",MBAR+$68000
		590
		591	;----------------------------------------------------------------------------
		592	; I2C
		593
		594	MBAR_I2C equ MBAR+$58000
		595	include "52xxi2c.inc"
		596
		597	;----------------------------------------------------------------------------
		598	; Message Digest Hardware Accelerator
		599
		600	MBAR_MDHA equ $ec080000
		601	include "52xxmdha.inc"
		602
		603	;----------------------------------------------------------------------------
		604	; Random Number Generator
		605
		606	MBAR_RNG equ $ec088000
		607	include "52xxrng.inc"
		608
		609	;----------------------------------------------------------------------------
		610	; Symmetric Key Hardware Accelerator
		611
		612	MBAR_SKHA equ $ec084000
		613	include "52xxskha.inc"
		614
		615	;----------------------------------------------------------------------------
		616
		617	restore ; re-enable listing
		618
		619	endif ; __mcf5329inc

Subversion Repositories pentevo

(root)/tools/asl/asl-current/include/coldfire/mcf5329.inc – Rev 1186