WebSVN – pentevo – Blame – /tools/asl/asl-current/include/ez80/reg80190.inc

Rev	Author	Line No.	Line
1186	savelij	1	ifndef __reg80190inc
		2	__reg80190inc equ 1
		3	save
		4	listing off ; no listing over this file
		5
		6	;****************************************************************************
		7	;* *
		8	;* AS(L) - File REG80190.INC *
		9	;* *
		10	;* Contains Bit & Register Definitions for Zilog eZ80190 *
		11	;* *
		12	;****************************************************************************
		13
		14	include "spi.inc"
		15	include "uart.inc"
		16	include "i2c.inc"
		17	include "gpio.inc"
		18
		19	;----------------------------------------------------------------------------
		20	; Memory Limits
		21
		22	RAMSTART equ 0e000h ; assumes RAM_ADDR_U = 00h
		23	RAMEND equ RAMSTART+1fffh
		24
		25	;----------------------------------------------------------------------------
		26	; Timer
		27
		28	TMR0_CTL port 80h ; Timer 0 Control Register (r/w)
		29	PRT_IRQ equ 1 << 7 ; Timer Interrupt occured
		30	PRT_IRQ_EN equ 1 << 6 ; Interrupt Enable
		31	PRT_MODE equ 1 << 4 ; Continuous Mode
		32	CLK_DIV_S equ 2 ; Clock Divider
		33	CLK_DIV_M equ 3 << CLK_DIV_S
		34	CLK_DIV_2 equ 0 << CLK_DIV_S ; Source = Clock/2
		35	CLK_DIV_4 equ 1 << CLK_DIV_S ; Source = Clock/4
		36	CLK_DIV_8 equ 2 << CLK_DIV_S ; Source = Clock/8
		37	CLK_DIV_16 equ 3 << CLK_DIV_S ; Source = Clock/16
		38	RST_EN equ 1 << 1 ; Automatic Restart Enable
		39	PRT_EN equ 1 << 0 ; Timer Enable
		40	TMR0_DR_L port 81h ; Timer 0 Data Register Low (r)
		41	TMR0_RR_L port 81h ; Timer 0 Reload Register Low (w)
		42	TMR0_DR_H port 82h ; Timer 0 Data Register High (r)
		43	TMR0_RR_H port 82h ; Timer 0 Reload Register High (w)
		44
		45	IVEC_PRT0 equ 06h ; Timer 0 Interrupt Vector
		46
		47	TMR1_CTL port 83h ; Timer 1 Control Register (r/w)
		48	TMR1_DR_L port 84h ; Timer 1 Data Register Low (r)
		49	TMR1_RR_L port 84h ; Timer 1 Reload Register Low (w)
		50	TMR1_DR_H port 85h ; Timer 1 Data Register High (r)
		51	TMR1_RR_H port 85h ; Timer 1 Reload Register High (w)
		52
		53	IVEC_PRT1 equ 08h ; Timer 1 Interrupt Vector
		54
		55	TMR2_CTL port 86h ; Timer 2 Control Register (r/w)
		56	TMR2_DR_L port 87h ; Timer 2 Data Register Low (r)
		57	TMR2_RR_L port 87h ; Timer 2 Reload Register Low (w)
		58	TMR2_DR_H port 88h ; Timer 2 Data Register High (r)
		59	TMR2_RR_H port 88h ; Timer 2 Reload Register High (w)
		60
		61	IVEC_PRT2 equ 0ah ; Timer 2 Interrupt Vector
		62
		63	TMR3_CTL port 89h ; Timer 3 Control Register (r/w)
		64	TMR3_DR_L port 8ah ; Timer 3 Data Register Low (r)
		65	TMR3_RR_L port 8ah ; Timer 3 Reload Register Low (w)
		66	TMR3_DR_H port 8bh ; Timer 3 Data Register High (r)
		67	TMR3_RR_H port 8bh ; Timer 3 Reload Register High (w)
		68
		69	IVEC_PRT3 equ 0ch ; Timer 3 Interrupt Vector
		70
		71	TMR4_CTL port 8ch ; Timer 4 Control Register (r/w)
		72	TMR4_DR_L port 8dh ; Timer 4 Data Register Low (r)
		73	TMR4_RR_L port 8dh ; Timer 4 Reload Register Low (w)
		74	TMR4_DR_H port 8eh ; Timer 4 Data Register High (r)
		75	TMR4_RR_H port 8eh ; Timer 4 Reload Register High (w)
		76
		77	IVEC_PRT4 equ 0eh ; Timer 4 Interrupt Vector
		78
		79	TMR5_CTL port 8fh ; Timer 5 Control Register (r/w)
		80	TMR5_DR_L port 90h ; Timer 5 Data Register Low (r)
		81	TMR5_RR_L port 90h ; Timer 5 Reload Register Low (w)
		82	TMR5_DR_H port 91h ; Timer 5 Data Register High (r)
		83	TMR5_RR_H port 91h ; Timer 5 Reload Register High (w)
		84
		85	IVEC_PRT5 equ 10h ; Timer 5 Interrupt Vector
		86
		87	;----------------------------------------------------------------------------
		88	; Watchdog Timer
		89
		90	WDT_CTL port 93h ; Watchdog Timer Control Register (r/w)
		91	WDT_EN equ 1 << 7 ; Watchdog Timer Enable
		92	NMI_OUT equ 1 << 6 ; NMI instead of reset
		93	RST_FLAG equ 1 << 5 ; Reset caused by WDT
		94	WDT_PERIOD_S equ 0 ; WDT Period
		95	WDT_PERIOD_M equ 3 << WDT_PERIOD_S
		96	WDT_PERIOD_27 equ 0 << WDT_PERIOD_S ; WDT period is 2**27 clock cycles
		97	WDT_PERIOD_25 equ 1 << WDT_PERIOD_S ; WDT period is 2**25 clock cycles
		98	WDT_PERIOD_22 equ 2 << WDT_PERIOD_S ; WDT period is 2**22 clock cycles
		99	WDT_PERIOD_18 equ 3 << WDT_PERIOD_S ; WDT period is 2**18 clock cycles
		100
		101	WDT_RR port 94h ; Watchdog Timer Reset Register (w)
		102
		103	;----------------------------------------------------------------------------
		104	; General-Purpose Input/Output Ports
		105
		106	__defgpio "A",96h
		107
		108	IVEC_PA0 equ 16h ; Port A 0 Interrupt Vector
		109	IVEC_PA1 equ 18h ; Port A 1 Interrupt Vector
		110	IVEC_PA2 equ 1ah ; Port A 2 Interrupt Vector
		111	IVEC_PA3 equ 1ch ; Port A 3 Interrupt Vector
		112	IVEC_PA4 equ 1eh ; Port A 4 Interrupt Vector
		113	IVEC_PA5 equ 20h ; Port A 5 Interrupt Vector
		114	IVEC_PA6 equ 22h ; Port A 6 Interrupt Vector
		115	IVEC_PA7 equ 24h ; Port A 7 Interrupt Vector
		116
		117	__defgpio "B",9ah
		118
		119	IVEC_PB0 equ 26h ; Port B 0 Interrupt Vector
		120	IVEC_PB1 equ 28h ; Port B 1 Interrupt Vector
		121	IVEC_PB2 equ 2ah ; Port B 2 Interrupt Vector
		122	IVEC_PB3 equ 2ch ; Port B 3 Interrupt Vector
		123	IVEC_PB4 equ 2eh ; Port B 4 Interrupt Vector
		124	IVEC_PB5 equ 30h ; Port B 5 Interrupt Vector
		125	IVEC_PB6 equ 32h ; Port B 6 Interrupt Vector
		126	IVEC_PB7 equ 34h ; Port B 7 Interrupt Vector
		127
		128	__defgpio "C",9eh
		129
		130	IVEC_PC0 equ 36h ; Port C 0 Interrupt Vector
		131	IVEC_PC1 equ 38h ; Port C 1 Interrupt Vector
		132	IVEC_PC2 equ 3ah ; Port C 2 Interrupt Vector
		133	IVEC_PC3 equ 3ch ; Port C 3 Interrupt Vector
		134	IVEC_PC4 equ 3eh ; Port C 4 Interrupt Vector
		135	IVEC_PC5 equ 40h ; Port C 5 Interrupt Vector
		136	IVEC_PC6 equ 42h ; Port C 6 Interrupt Vector
		137	IVEC_PC7 equ 44h ; Port C 7 Interrupt Vector
		138
		139	__defgpio "D",0a2h
		140
		141	IVEC_PD0 equ 46h ; Port D 0 Interrupt Vector
		142	IVEC_PD1 equ 48h ; Port D 1 Interrupt Vector
		143	IVEC_PD2 equ 4ah ; Port D 2 Interrupt Vector
		144	IVEC_PD3 equ 4ch ; Port D 3 Interrupt Vector
		145	IVEC_PD4 equ 4eh ; Port D 4 Interrupt Vector
		146	IVEC_PD5 equ 50h ; Port D 5 Interrupt Vector
		147	IVEC_PD6 equ 52h ; Port D 6 Interrupt Vector
		148	IVEC_PD7 equ 54h ; Port D 7 Interrupt Vector
		149
		150	;----------------------------------------------------------------------------
		151	; Chip Select/Wait State Generator
		152
		153	CS0_LBR port 0a8h ; Chip Select 0 Lower Bound Register (r/w)
		154	CS0_UBR port 0a9h ; Chip Select 0 Upper Bound Register (r/w)
		155	CS0_CTL port 0aah ; Chip Select 0 Control Register (r/w)
		156	CS_WAIT_S equ 5 ; # of wait states
		157	CS_WAIT_M equ 7 << CS_WAIT_S
		158	CS_IO equ 1 << 4 ; Match I/O range
		159	CS_EN equ 1 << 3 ; Enable Chip Select
		160
		161	CS1_LBR port 0abh ; Chip Select 1 Lower Bound Register (r/w)
		162	CS1_UBR port 0ach ; Chip Select 1 Upper Bound Register (r/w)
		163	CS1_CTL port 0adh ; Chip Select 1 Control Register (r/w)
		164
		165	CS2_LBR port 0aeh ; Chip Select 2 Lower Bound Register (r/w)
		166	CS2_UBR port 0afh ; Chip Select 2 Upper Bound Register (r/w)
		167	CS2_CTL port 0b0h ; Chip Select 2 Control Register (r/w)
		168
		169	CS3_LBR port 0b1h ; Chip Select 3 Lower Bound Register (r/w)
		170	CS3_UBR port 0b2h ; Chip Select 3 Upper Bound Register (r/w)
		171	CS3_CTL port 0b3h ; Chip Select 3 Control Register (r/w)
		172
		173	;----------------------------------------------------------------------------
		174	; On-Chip RAM Control
		175
		176	RAM_CTL port 0b4h ; RAM Control Register (r/w)
		177	RAM_ADDR_U port 0b5h ; RAM Address Upper Byte (r/w)
		178
		179	;----------------------------------------------------------------------------
		180	; Universal Zilog Interface Blocks
		181
		182	__defspi "0",0b6h
		183
		184	__defspi "1",0bah
		185
		186	__defuart "0",0c0h
		187	BRG0_DLR_L port UART0_BRG_L ; Alias names
		188	BRG0_DLR_H port UART0_BRG_H
		189
		190	__defi2c "0",0c8h
		191
		192	UZI0_CTL port 0cfh ; UZI 0 Control Register (r/w)
		193	UZI_MODE_S equ 0 ; Mode
		194	UZI_MODE_M equ 3 << UZI_MODE_S
		195	UZI_MODE_DIS equ 0 << UZI_MODE_S ; All modes disabled
		196	UZI_MODE_UART equ 1 << UZI_MODE_S ; UART mode
		197	UZI_MODE_SPI equ 2 << UZI_MODE_S ; SPI mode
		198	UZI_MODE_I2C equ 3 << UZI_MODE_S ; I2C mode
		199
		200	IVEC_UZI0 equ 12h ; UZI 0 Interrupt Vector
		201
		202	__defuart "1",0d0h
		203	BRG1_DLR_L port UART1_BRG_L ; Alias names
		204	BRG1_DLR_H port UART1_BRG_H
		205
		206	__defi2c "1",0d8h
		207
		208	UZI1_CTL port 0dfh ; UZI 1 Control Register (r/w)
		209
		210	IVEC_UZI1 equ 14h ; UZI 1 Interrupt Vector
		211
		212	;----------------------------------------------------------------------------
		213	; Multiply-Accumulator
		214
		215	MACC_xSTART port 0e0h ; Multiply-Accumulator x Starting Address Register (r/w)
		216	MACC_xEND port 0e1h ; Multiply-Accumulator x Ending Address Register (r/w)
		217	MACC_xRELOAD port 0e2h ; Multiply-Accumulator x Reload Register (r/w)
		218	MACC_LENGTH port 0e3h ; Multiply-Accumulator Length Register (r/w)
		219	MACC_ySTART port 0e4h ; Multiply-Accumulator y Starting Address Register (r/w)
		220	MACC_yEND port 0e5h ; Multiply-Accumulator y Ending Address Register (r/w)
		221	MACC_yRELOAD port 0e6h ; Multiply-Accumulator y Reload Register (r/w)
		222	MACC_CTL port 0e7h ; Multiply-Accumulator Control Register (r/w)
		223	MACC_AC0 port 0e8h ; Multiply-Accumulator Byte 0 Register (r/w)
		224	MACC_AC1 port 0e9h ; Multiply-Accumulator Byte 1 Register (r/w)
		225	MACC_AC2 port 0eah ; Multiply-Accumulator Byte 2 Register (r/w)
		226	MACC_AC3 port 0ebh ; Multiply-Accumulator Byte 3 Register (r/w)
		227	MACC_AC4 port 0ech ; Multiply-Accumulator Byte 4 Register (r/w)
		228	MACC_STAT port 0edh ; Multiply-Accumulator Status Register (r/w)
		229	BANK equ 1 << 4 ; Select CALC/DATA Bank
		230	CALC_STAT_S equ 2 ; CALC Bank Status
		231	CALC_STAT_M equ 3 << CALC_STAT_S
		232	CALC_STAT_EMPTY equ 0 << CALC_STAT_S
		233	CALC_STAT_PROGRESS equ 2 << CALC_STAT_S
		234	CALC_STAT_DONE equ 3 << CALC_STAT_S
		235	DATA_STAT_S equ 0 ; DATA Bank Status
		236	DATA_STAT_M equ 3 << DATA_STAT_S
		237	DATA_STAT_EMPTY equ 0 << DATA_STAT_S
		238	DATA_STAT_READY equ 1 << DATA_STAT_S
		239	DATA_STAT_DONE equ 3 << DATA_STAT_S
		240
		241	IVEC_MACC equ 00h ; MACC Interrupt Vector
		242
		243	;----------------------------------------------------------------------------
		244	; DMA Controllers
		245
		246	DMA0_SAR_L port 0eeh ; DMA0 Source Address Register - Low Byte Register (r/w)
		247	DMA0_SAR_H port 0efh ; DMA0 Source Address Register - High Byte Register (r/w)
		248	DMA0_SAR_U port 0f0h ; DMA0 Source Address Register - Upper Byte Register (r/w)
		249	DMA0_DAR_L port 0f1h ; DMA0 Destination Address Register - Low Byte Register (r/w)
		250	DMA0_DAR_H port 0f2h ; DMA0 Destination Address Register - High Byte Register (r/w)
		251	DMA0_DAR_U port 0f3h ; DMA0 Destination Address Register - Upper Byte Register (r/w)
		252	DMA0_BC_L port 0f4h ; DMA0 Byte Count Register - Low Byte (r/w)
		253	DMA0_BC_H port 0f5h ; DMA0 Byte Count Register - High Byte (r/w)
		254	DMA0_CTL port 0f6h ; DMA0 Control Register (r/w)
		255	DMA_EN equ 1 << 7 ; Enable DMA channel
		256	IRQ_DMA equ 1 << 6 ; Enable Interrupt
		257	BURST equ 1 << 4 ; Use Burst Mode
		258	DAR_CTL_S equ 2 ; Destination Address:
		259	DAR_CTL_M equ 3 << DAR_CTL_S
		260	DAR_CTL_UNCH equ 0 << DAR_CTL_S ; unchanged after transfer
		261	DAR_CTL_INC equ 1 << DAR_CTL_S ; increment after transfer
		262	DAR_CTL_DEC equ 2 << DAR_CTL_S ; decrement after transfer
		263	SAR_CTL_S equ 2 ; Source Address:
		264	SAR_CTL_M equ 3 << SAR_CTL_S
		265	SAR_CTL_UNCH equ 0 << SAR_CTL_S ; unchanged after transfer
		266	SAR_CTL_INC equ 1 << SAR_CTL_S ; increment after transfer
		267	SAR_CTL_DEC equ 2 << SAR_CTL_S ; decrement after transfer
		268
		269	IVEC_DMA0 equ 02h ; DMA0 Interrupt Vector
		270
		271	DMA1_SAR_L port 0f7h ; DMA1 Source Address Register - Low Byte Register (r/w)
		272	DMA1_SAR_H port 0f8h ; DMA1 Source Address Register - High Byte Register (r/w)
		273	DMA1_SAR_U port 0f9h ; DMA1 Source Address Register - Upper Byte Register (r/w)
		274	DMA1_DAR_L port 0fah ; DMA1 Destination Address Register - Low Byte Register (r/w)
		275	DMA1_DAR_H port 0fbh ; DMA1 Destination Address Register - High Byte Register (r/w)
		276	DMA1_DAR_U port 0fch ; DMA1 Destination Address Register - Upper Byte Register (r/w)
		277	DMA1_BC_L port 0fdh ; DMA1 Byte Count Register - Low Byte (r/w)
		278	DMA1_BC_H port 0feh ; DMA1 Byte Count Register - High Byte (r/w)
		279	DMA1_CTL port 0ffh ; DMA1 Control Register (r/w)
		280
		281	IVEC_DMA1 equ 04h ; DMA0 Interrupt Vector
		282
		283	;----------------------------------------------------------------------------
		284
		285	restore
		286	endif ; __reg80190inc
		287

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(root)/tools/asl/asl-current/include/ez80/reg80190.inc – Rev 1186