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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef __reg6230inc ; avoid multiple inclusion |
| 2 | __reg6230inc equ 1 |
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| 3 | |||
| 4 | save |
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| 5 | listing off ; no listing over this file |
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| 6 | |||
| 7 | ;**************************************************************************** |
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| 8 | ;* * |
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| 9 | ;* AS 1.42 - File REG6230.INC * |
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| 10 | ;* * |
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| 11 | ;* contains SFR and Bit Definitions for ST6230/6232 * |
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| 12 | ;* * |
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| 13 | ;* Source: ST62T30B/E30B Data Sheet, Rev. 2.7, October 2003 * |
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| 14 | ;* ST62T32B/E32B Data Sheet, Rev. 2.5, September 1998 * |
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| 15 | ;* * |
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| 16 | ;**************************************************************************** |
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| 17 | |||
| 18 | ;---------------------------------------------------------------------------- |
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| 19 | ; Memory Addresses |
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| 20 | |||
| 21 | RAMSTART sfr 0000h ; Start Address Internal RAM |
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| 22 | ; area 00h..3fh maps to two banks |
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| 23 | ; area 40h..7fh is ROM read window |
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| 24 | RAMEND sfr 00bfh ; End Address Internal RAM |
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| 25 | |||
| 26 | EESTART sfr 0000h ; Start Address EEPROM (2 banks shared with RAM) |
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| 27 | EEEND sfr 003fh ; End " " |
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| 28 | |||
| 29 | ROMSTART label 0080h ; Start Address Internal ROM |
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| 30 | ROMEND label 1fffh ; End " " ROM |
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| 31 | |||
| 32 | ;---------------------------------------------------------------------------- |
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| 33 | ; Interrupt Vectors |
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| 34 | |||
| 35 | ADC_vect label 0ff0h ; A/D End Of Conversion, shared with... |
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| 36 | TIMER_vect label 0ff0h ; Timer Underflow, shared with... |
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| 37 | UART_vect label 0ff0h ; UART Tx/Rx Interrupt |
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| 38 | ARTIMER_vect label 0ff2h ; AR Timer Overflow/Capture |
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| 39 | PORTD_vect label 0ff4h ; Ext. Interrupt Port D, shared with... |
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| 40 | PORTB_vect label 0ff4h ; Ext. Interrupt Port B |
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| 41 | SPI_vect label 0ff6h ; SPI Interrupt, shared with... |
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| 42 | PORTA_vect label 0ff6h ; Ext. Interrupt Port A |
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| 43 | PORTC_vect label 0ffch ; Ext. Interrupt Port C, shared with... |
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| 44 | NMI_vect label 0ffch ; Non Maskable Interrupt |
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| 45 | RESET_vect label 0ffeh ; RESET |
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| 46 | |||
| 47 | ;---------------------------------------------------------------------------- |
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| 48 | ; GPIO |
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| 49 | |||
| 50 | include "gpio.inc" |
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| 51 | __defgpio "A",0c0h |
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| 52 | __defgpio "B",0c1h |
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| 53 | __defgpio "C",0c2h |
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| 54 | __defgpio "D",0c3h |
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| 55 | |||
| 56 | ;---------------------------------------------------------------------------- |
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| 57 | ; CPU |
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| 58 | |||
| 59 | include "ior.inc" |
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| 60 | |||
| 61 | DRBR sfr 0cbh ; Data RAM Bank Register |
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| 62 | DRBR4 bit 4,DRBR ; Map RAM Page 2 |
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| 63 | DRBR3 bit 3,DRBR ; Map RAM Page 1 |
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| 64 | DRBR1 bit 1,DRBR ; Map EEPROM Page 1 |
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| 65 | DRBR0 bit 0,DRBR ; Map EEPROM Page 0 |
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| 66 | |||
| 67 | IPR sfr 0dah ; Interrupt Polarity Register |
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| 68 | PortD bit 3,IPR ; Port D Interrupt Polarity |
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| 69 | PortC bit 2,IPR ; Port C Interrupt Polarity |
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| 70 | PortA bit 1,IPR ; Port A Interrupt Polarity |
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| 71 | PortB bit 0,IPR ; Port B Interrupt Polarity |
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| 72 | |||
| 73 | EECTL sfr 0dfh ; EEPROM Control Register |
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| 74 | E2OFF bit 6,EECTL ; Stand-by Enable Bit |
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| 75 | E2PAR1 bit 3,EECTL ; Parallel Start Bit |
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| 76 | E2PAR2 bit 2,EECTL ; Parallel Mode En |
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| 77 | E2BUSY bit 1,EECTL ; EEPROM Busy Bit |
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| 78 | E2ENA bit 0,EECTL ; EEPROM Enable Bit |
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| 79 | |||
| 80 | ;---------------------------------------------------------------------------- |
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| 81 | ; Clock System |
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| 82 | |||
| 83 | OSCR sfr 0dbh |
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| 84 | OSCOFF bit 0,OSCR ; Main Oscillator Turn-Off |
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| 85 | |||
| 86 | ;---------------------------------------------------------------------------- |
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| 87 | ; Watchdog |
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| 88 | |||
| 89 | include "wdg.inc" |
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| 90 | DWDR sfr WDGR ; alternate name in older data sheets |
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| 91 | |||
| 92 | ;---------------------------------------------------------------------------- |
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| 93 | ; Analog/Digital Converter |
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| 94 | |||
| 95 | include "adc.inc" |
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| 96 | CLSEL bit 2,ADCR ; Clock Selection |
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| 97 | |||
| 98 | ;---------------------------------------------------------------------------- |
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| 99 | ; Timer 1 |
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| 100 | |||
| 101 | include "timer.inc" |
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| 102 | __deftimer 0d2h,"" |
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| 103 | TOUT bit 5,TSCR ; Timer Output Control |
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| 104 | DOUT bit 4,TSCR ; Data Output |
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| 105 | |||
| 106 | ;---------------------------------------------------------------------------- |
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| 107 | ; Auto Reload Timer |
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| 108 | |||
| 109 | include "artim16.inc" |
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| 110 | |||
| 111 | ;---------------------------------------------------------------------------- |
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| 112 | ; UART |
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| 113 | |||
| 114 | include "uart.inc" |
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| 115 | DAT9 bit 0,UARTCR ; Alias for Parity/Data Bit 8 |
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| 116 | |||
| 117 | ;---------------------------------------------------------------------------- |
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| 118 | ; SPI |
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| 119 | |||
| 120 | include "spi.inc" |
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| 121 | |||
| 122 | restore |
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| 123 | endif ; __reg6230inc |