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Rev | Author | Line No. | Line |
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1186 | savelij | 1 | ifndef __reg6255inc ; avoid multiple inclusion |
2 | __reg6255inc equ 1 |
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3 | |||
4 | save |
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5 | listing off ; no listing over this file |
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6 | |||
7 | ;**************************************************************************** |
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8 | ;* * |
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9 | ;* AS 1.42 - File REG6255.INC * |
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10 | ;* * |
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11 | ;* contains SFR and Bit Definitions for ST6255/6265 * |
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12 | ;* * |
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13 | ;* Source: ST6255C ST6265C ST6265B Data Sheet, Rev. 3, March 2009 * |
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14 | ;* * |
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15 | ;**************************************************************************** |
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16 | |||
17 | ;---------------------------------------------------------------------------- |
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18 | ; Memory Addresses |
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19 | |||
20 | |||
21 | RAMSTART sfr 000h ; Start Address Internal RAM |
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22 | ; area 00h..3fh maps to one RAM bank |
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23 | ; area 40h..7fh is ROM read window |
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24 | RAMEND sfr 0bfh ; End Address Internal RAM |
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25 | |||
26 | switch MOMCPUNAME |
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27 | case "ST6255" |
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28 | case "ST6265" |
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29 | EESTART sfr 0000h ; Start Address EEPROM (tw banks shared with RAM) |
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30 | EEEND sfr 003fh ; End " " |
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31 | elsecase |
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32 | fatal "Huh?" |
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33 | endcase |
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34 | |||
35 | segment code |
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36 | |||
37 | ROMSTART label 0080h ; Start Address Internal ROM |
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38 | ROMEND label 0fffh ; End " " ROM |
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39 | |||
40 | ;---------------------------------------------------------------------------- |
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41 | ; Interrupt Vectors |
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42 | |||
43 | ADC_vect label 0ff0h ; A/D End Of Conversion, shared with... |
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44 | TIMER_vect label 0ff0h ; Timer Underflow |
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45 | ARTIMER_vect label 0ff2h ; AR Timer Overflow/Compare |
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46 | PORTC_vect label 0ff4h ; Ext. Interrupt Port C, shared with... |
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47 | SPI_vect label 0ff4h ; SPI Interrupt |
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48 | PORTA_vect label 0ff6h ; Ext. Interrupt Port A, shared with... |
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49 | PORTB_vect label 0ff6h ; Ext. Interrupt Port B |
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50 | NMI_vect label 0ffch ; Non Maskable Interrupt |
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51 | RESET_vect label 0ffeh ; RESET |
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52 | |||
53 | ;---------------------------------------------------------------------------- |
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54 | ; GPIO |
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55 | |||
56 | include "gpio.inc" |
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57 | __defgpio "A",0c0h |
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58 | __defgpio "B",0c1h |
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59 | __defgpio "C",0c2h |
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60 | |||
61 | ;---------------------------------------------------------------------------- |
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62 | ; CPU |
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63 | |||
64 | include "ior.inc" |
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65 | |||
66 | DRBR sfr 0e8h ; Data RAM Bank Register |
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67 | DRBR4 bit 4,DRBR ; Map RAM Page 2 |
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68 | ifdef EESTART |
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69 | DRBR1 bit 1,DRBR ; Map EEPROM Page 1 |
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70 | DRBR0 bit 0,DRBR ; Map EEPROM Page 0 |
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71 | endif |
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72 | |||
73 | ifdef EESTART |
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74 | EECTL sfr 0eah ; EEPROM Control Register |
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75 | E2OFF bit 6,EECTL ; Stand-by Enable Bit |
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76 | E2PAR1 bit 3,EECTL ; Parallel Start Bit |
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77 | E2PAR2 bit 2,EECTL ; Parallel Mode En |
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78 | E2BUSY bit 1,EECTL ; EEPROM Busy Bit |
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79 | E2ENA bit 0,EECTL ; EEPROM Enable Bit |
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80 | endif |
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81 | |||
82 | OSCCTL sfr 0dch ; Oscillator Control |
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83 | RS bfield OSCCTL,0,2 ; Division Ratio |
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84 | |||
85 | ;---------------------------------------------------------------------------- |
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86 | ; Watchdog |
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87 | |||
88 | include "wdg.inc" |
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89 | DWDR sfr WDGR ; alternate name in older data sheets |
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90 | |||
91 | ;---------------------------------------------------------------------------- |
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92 | ; Analog/Digital Converter |
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93 | |||
94 | include "adc.inc" |
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95 | OSCOFF bit 2,ADCR ; Disable Main Oscillator |
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96 | |||
97 | ;---------------------------------------------------------------------------- |
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98 | ; Timer |
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99 | |||
100 | include "timer.inc" |
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101 | __deftimer 0d2h,"" |
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102 | TOUT bit 5,TSCR ; Timer Output Control |
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103 | DOUT bit 4,TSCR ; Data Output |
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104 | |||
105 | ;---------------------------------------------------------------------------- |
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106 | ; AR Timer |
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107 | |||
108 | include "artimer.inc" |
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109 | __defartimer 0d0h |
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110 | |||
111 | ;---------------------------------------------------------------------------- |
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112 | ; SPI |
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113 | |||
114 | include "spi2.inc" |
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115 | |||
116 | restore |
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117 | endif ; __reg6255inc |