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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef __reglit2xinc ; avoid multiple inclusion |
| 2 | __reglit2xinc equ 1 |
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| 3 | |||
| 4 | save |
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| 5 | listing off ; no listing over this file |
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| 6 | |||
| 7 | ;**************************************************************************** |
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| 8 | ;* * |
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| 9 | ;* AS 1.42 - File REGLIT2X.INC * |
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| 10 | ;* * |
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| 11 | ;* contains SFR and Bit Definitions for ST7LITE2x * |
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| 12 | ;* * |
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| 13 | ;* Source: ST7LITE20 Data Sheet, Rev. 7, DocID8349, January 2014 * |
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| 14 | ;* * |
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| 15 | ;**************************************************************************** |
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| 16 | |||
| 17 | ;---------------------------------------------------------------------------- |
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| 18 | ; Memory Addresses |
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| 19 | |||
| 20 | RAMSTART label $0080 ; Start Address Internal RAM |
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| 21 | RAMEND label $01ff ; End " " " |
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| 22 | |||
| 23 | switch SUBSTR(MOMCPUNAME,STRLEN(MOMCPUNAME)-3,1) |
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| 24 | case "0","5" |
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| 25 | case "9" |
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| 26 | EESTART label $1000 ; Start Address Internal EEPROM |
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| 27 | EEEND label $10ff ; End " " " |
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| 28 | endcase |
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| 29 | |||
| 30 | RCCR0 label $1000 ; RC Oscillator Calibration Values |
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| 31 | RCCR1 label $1001 |
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| 32 | |||
| 33 | ;---------------------------------------------------------------------------- |
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| 34 | ; Interrupt Vectors |
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| 35 | |||
| 36 | SPI_vect label $ffe2 ; SPI Interrupt |
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| 37 | LT_RTC1_vect label $ffe4 ; Lite Timer RTC1 Interrupt |
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| 38 | LT_IC_vect label $ffe6 ; Lite Timer Input Capture Interrupt |
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| 39 | AT_OF1_vect label $ffe8 ; AT Timer Overflow 1 Interrupt |
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| 40 | AT_OC_vect label $ffea ; AT Timer Output Compare Interrupt, shared with... |
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| 41 | AT_IC_vect label $ffea ; AT Timer Input Capture Interrupt |
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| 42 | SI_vect label $ffec ; AVD Interrupt |
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| 43 | LT_RTC2_vect label $fff0 ; LITE TIMER RTC2 interrupt |
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| 44 | EI3_vect label $fff2 ; External Interrupt Vector EI3 |
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| 45 | EI2_vect label $fff4 ; External Interrupt Vector EI2 |
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| 46 | EI1_vect label $fff6 ; External Interrupt Vector EI1 |
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| 47 | EI0_vect label $fff8 ; External Interrupt Vector EI0 |
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| 48 | AWU_vect label $fffa ; Auto Wakeup Interrupt Vector |
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| 49 | TRAP_vect label $fffc ; TRAP (software) Interrupt Vector |
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| 50 | RESET_vect label $fffe ; RESET Vector |
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| 51 | |||
| 52 | ;---------------------------------------------------------------------------- |
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| 53 | ; GPIO |
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| 54 | |||
| 55 | include "gpio.inc" |
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| 56 | __defgpio "PA",$0000 |
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| 57 | __defgpio "PB",$0003 |
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| 58 | |||
| 59 | ;---------------------------------------------------------------------------- |
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| 60 | ; Lite Timer |
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| 61 | |||
| 62 | LTCSR2 label $0008 ; Lite Timer Control/Status Register 2 |
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| 63 | TB2IE bit LTCSR2,1 ; Timebase 2 Interrupt Enable Bit |
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| 64 | TB2F bit LTCSR2,0 ; Timebase 2 Interrupt Flag |
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| 65 | LTARR label $0009 ; Lite Timer Auto-reload Register |
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| 66 | LTCNTR label $000a ; Lite Timer Counter Register |
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| 67 | LTCSR1 label $000b ; Lite Timer Control/Status Register 1 |
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| 68 | TBICIE bit LTCSR1,7 ; Interrupt Enable Bit |
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| 69 | TBICF bit LTCSR1,6 ; Input Capture Flag |
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| 70 | TB bit LTCSR1,5 ; Timebase Period Selection Bit |
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| 71 | TB1IE bit LTCSR1,4 ; Timebase Interrupt Enable Bit |
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| 72 | TB1F bit LTCSR1,3 ; Timebase Interrupt Flag |
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| 73 | LTICR label $000c ; Lite Timer Input Capture Register |
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| 74 | |||
| 75 | ;---------------------------------------------------------------------------- |
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| 76 | ; Auto-Reload Timer |
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| 77 | |||
| 78 | ATCSR label $000d ; Timer Control/Status Register |
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| 79 | ICF bit ATCSR,6 ; Input Capture flag |
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| 80 | ICIE bit ATCSR,5 ; IC Interrupt Enable bit |
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| 81 | CK bfield ATCSR,3,2 ; Counter Clock Selection |
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| 82 | OVF1 bit ATCSR,2 ; Overflow flag |
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| 83 | OVFIE1 bit ATCSR,1 ; Overflow Interrupt Enable bit |
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| 84 | ATCMPIE bit ATCSR,0 ; Compare Interrupt Enable bit |
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| 85 | CNTRH label $000e ; Counter Register High |
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| 86 | CNTRL label $000f ; Counter Register Low |
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| 87 | ATRH label $0010 ; Auto-Reload Register 1 High |
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| 88 | ATRL label $0011 ; Auto-Reload Register 1 Low |
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| 89 | PWMCR label $0012 ; PWM Output Control Register |
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| 90 | OE3 bit PWMCR,6 ; PWM3 Output Enable |
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| 91 | OE2 bit PWMCR,4 ; PWM2 Output Enable |
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| 92 | OE1 bit PWMCR,2 ; PWM1 Output Enable |
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| 93 | OE0 bit PWMCR,0 ; PWM0 Output Enable |
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| 94 | PWM0CSR label $0013 ; PWM 0 Control/Status Register |
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| 95 | OP0 bit PWM0CSR,1 ; PWM0 Output Polarity Bit |
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| 96 | CMPF0 bit PWM0CSR,0 ; PWM0 Compare Flag |
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| 97 | PWM1CSR label $0014 ; PWM 1 Control/Status Register |
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| 98 | OP1 bit PWM1CSR,1 ; PWM1 Output Polarity Bit |
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| 99 | CMPF1 bit PWM1CSR,0 ; PWM1 Compare Flag |
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| 100 | PWM2CSR label $0015 ; PWM 2 Control/Status Register |
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| 101 | OP2 bit PWM2CSR,1 ; PWM2 Output Polarity Bit |
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| 102 | CMPF2 bit PWM2CSR,0 ; PWM2 Compare Flag |
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| 103 | PWM3CSR label $0016 ; PWM 3 Control/Status Register |
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| 104 | OP_EN bit PWM3CSR,3 ; One Pulse Mode Enable Bit |
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| 105 | OPEDGE bit PWM3CSR,2 ; One Pulse Edge Selection Bit |
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| 106 | OP3 bit PWM3CSR,1 ; PWM3 Output Polarity Bit |
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| 107 | CMPF3 bit PWM3CSR,0 ; PWM3 Compare Flag |
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| 108 | DCR0H label $0017 ; PWM 0 Duty Cycle Register High |
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| 109 | DCR0L label $0018 ; PWM 0 Duty Cycle Register Low |
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| 110 | DCR1H label $0019 ; PWM 1 Duty Cycle Register High |
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| 111 | DCR1L label $001a ; PWM 1 Duty Cycle Register Low |
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| 112 | DCR2H label $001b ; PWM 2 Duty Cycle Register High |
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| 113 | DCR2L label $001c ; PWM 2 Duty Cycle Register Low |
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| 114 | DCR3H label $001d ; PWM 3 Duty Cycle Register High |
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| 115 | DCR3L label $001e ; PWM 3 Duty Cycle Register Low |
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| 116 | ATICRH label $001f ; Input Capture Register High |
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| 117 | ATICRL label $0020 ; Input Capture Register Low |
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| 118 | TRANCR label $0021 ; Transfer Control Register |
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| 119 | TRAN bit TRANCR,0 ; Transfer enable |
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| 120 | BREAKCR label $0022 ; Break Control Register |
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| 121 | PWM bfield BREAKCR,0,4 ; Break Pattern bits |
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| 122 | BA bit BREAKCR,5 ; Break Active |
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| 123 | BPEN bit BREAKCR,4 ; Break Pin Enable |
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| 124 | |||
| 125 | ;---------------------------------------------------------------------------- |
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| 126 | ; Watchdog |
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| 127 | |||
| 128 | WDGCR label $002e ; Watchdog Control Register |
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| 129 | WDGA bit WDGCR,7 ; Activation bit |
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| 130 | |||
| 131 | ;---------------------------------------------------------------------------- |
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| 132 | ; Flash |
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| 133 | |||
| 134 | FCSR label $002f ; Flash Control/Status Register |
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| 135 | |||
| 136 | ;---------------------------------------------------------------------------- |
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| 137 | ; EEPROM |
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| 138 | |||
| 139 | ifdef EESTART |
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| 140 | EECSR label $0030 ; Data EEPROM Control/Status Register |
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| 141 | E2LAT bit EECSR,1 ; Latch Access Transfer |
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| 142 | E2PGM bit EECSR,0 ; Programming control and status |
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| 143 | endif |
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| 144 | |||
| 145 | ;---------------------------------------------------------------------------- |
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| 146 | ; SPI |
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| 147 | |||
| 148 | include "spi2.inc" |
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| 149 | __defspi $0031 |
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| 150 | |||
| 151 | ;---------------------------------------------------------------------------- |
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| 152 | ; Analog/Digital Converter |
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| 153 | |||
| 154 | include "adc10.inc" |
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| 155 | __defadc10 $0034 |
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| 156 | |||
| 157 | ;---------------------------------------------------------------------------- |
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| 158 | ; ITC |
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| 159 | |||
| 160 | EICR label $0037 ; External Interrupt Control Register |
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| 161 | IS3 bfield EICR,6,2 ; ei3 Sensitivity |
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| 162 | IS2 bfield EICR,4,2 ; ei2 Sensitivity |
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| 163 | IS1 bfield EICR,2,2 ; ei1 Sensitivity |
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| 164 | IS0 bfield EICR,0,2 ; ei0 Sensitivity |
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| 165 | EISR label $003c ; External Interrupt Selection Register |
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| 166 | EI3 bfield EISR,6,2 ; ei3 Pin Selection |
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| 167 | EI2 bfield EISR,4,2 ; ei2 Pin Selection |
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| 168 | EI1 bfield EISR,2,2 ; ei1 Pin Selection |
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| 169 | EI0 bfield EISR,0,2 ; ei0 Pin Selection |
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| 170 | |||
| 171 | ;---------------------------------------------------------------------------- |
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| 172 | ; MCC |
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| 173 | |||
| 174 | MCCSR label $0038 ; Main Clock Control / Status Register |
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| 175 | MCO bit MCCSR,1 ; Main Clock Out Enable Bit |
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| 176 | SMS bit MCCSR,0 ; Slow Mode Selection Bit |
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| 177 | |||
| 178 | ;---------------------------------------------------------------------------- |
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| 179 | ; RC Calibration |
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| 180 | |||
| 181 | RCCR label $0039 ; RC Calibration Control/Status Register |
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| 182 | SICSR label $003a ; System Integrity Control/Status Register |
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| 183 | LOCK32 bit SICSR,7 ; PLL 32Mhz Locked Flag |
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| 184 | WDGRF bit SICSR,4 ; Watchdog Reset Flag |
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| 185 | LOCKED bit SICSR,3 ; PLL Locked Flag |
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| 186 | LVDRF bit SICSR,2 ; LVD Reset Flag |
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| 187 | AVDF bit SICSR,1 ; Voltage Detector Flag |
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| 188 | AVDIE bit SICSR,0 ; Voltage Detector Interrupt Enable |
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| 189 | |||
| 190 | ;---------------------------------------------------------------------------- |
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| 191 | ; Auto Wakeup Unit |
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| 192 | |||
| 193 | AWUPR label $0049 ; AWU Preload Register |
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| 194 | AWUCSR label $004a ; AWU Control/Status Register |
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| 195 | AWUF bit AWUCSR,2 ; Auto Wakeup Flag |
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| 196 | AWUM bit AWUCSR,1 ; Auto Wakeup Measurement Bit |
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| 197 | AWUEN bit AWUCSR,0 ; Auto Wakeup From Halt Enabled Bit |
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| 198 | |||
| 199 | ;---------------------------------------------------------------------------- |
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| 200 | ; Debug Module |
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| 201 | |||
| 202 | include "dm.inc" |
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| 203 | __defdm $004b |
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| 204 | |||
| 205 | restore |
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| 206 | endif ; __reglit2xinc |