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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef stddef5xinc ; avoid multiple inclusion |
| 2 | stddef5xinc equ 1 |
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| 3 | |||
| 4 | save |
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| 5 | listing off ; no listing over this file |
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| 6 | |||
| 7 | ;**************************************************************************** |
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| 8 | ;* * |
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| 9 | ;* AS 1.42 - File STDDEF2X.INC * |
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| 10 | ;* * |
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| 11 | ;* Contains Global Register Definitions for TMS320C5x Processors * * |
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| 12 | ;* * |
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| 13 | ;**************************************************************************** |
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| 14 | |||
| 15 | if (MOMCPU<>3279952) && (MOMCPU<>3279953) && (MOMCPU<>3279955) |
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| 16 | fatal "wrong target selected: only 320C50, 320C51 und 320C53 supported" |
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| 17 | endif |
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| 18 | |||
| 19 | if MOMPASS=1 |
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| 20 | message "TMS320C5x Register Definitions (C) 1995 Thomas Sailer" |
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| 21 | endif |
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| 22 | |||
| 23 | ;---------------------------------------------------------------------------- |
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| 24 | segment data |
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| 25 | |||
| 26 | org 4 |
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| 27 | ;Core Processor Memory Mapped Registers |
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| 28 | IMR res 1 |
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| 29 | GREG res 1 |
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| 30 | IFR res 1 |
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| 31 | PMST res 1 |
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| 32 | RPTC res 1 |
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| 33 | BRCR res 1 |
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| 34 | PASR res 1 |
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| 35 | PAER res 1 |
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| 36 | TREG0 res 1 |
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| 37 | TREG1 res 1 |
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| 38 | TREG2 res 1 |
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| 39 | DBMR res 1 |
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| 40 | AR0 res 1 |
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| 41 | AR1 res 1 |
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| 42 | AR2 res 1 |
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| 43 | AR3 res 1 |
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| 44 | AR4 res 1 |
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| 45 | AR5 res 1 |
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| 46 | AR6 res 1 |
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| 47 | AR7 res 1 |
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| 48 | INDX res 1 |
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| 49 | ARCR res 1 |
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| 50 | CBSR1 res 1 |
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| 51 | CBER1 res 1 |
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| 52 | CBSR2 res 1 |
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| 53 | CBER2 res 1 |
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| 54 | CBCR res 1 |
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| 55 | BMAR res 1 |
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| 56 | |||
| 57 | org 32 |
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| 58 | ;Peripherial memory mapped registers |
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| 59 | DRR res 1 |
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| 60 | DXR res 1 |
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| 61 | SPC res 1 |
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| 62 | |||
| 63 | org 36 |
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| 64 | TIM res 1 |
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| 65 | PRD res 1 |
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| 66 | TCR res 1 |
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| 67 | |||
| 68 | org 40 |
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| 69 | PDWSR res 1 |
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| 70 | IOWSR res 1 |
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| 71 | CWSR res 1 |
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| 72 | |||
| 73 | org 48 |
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| 74 | TRCV res 1 |
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| 75 | TDXR res 1 |
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| 76 | TSPC res 1 |
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| 77 | TCSR res 1 |
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| 78 | TRTA res 1 |
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| 79 | TRAD res 1 |
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| 80 | |||
| 81 | org 80 |
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| 82 | PA0 res 1 |
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| 83 | PA1 res 1 |
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| 84 | PA2 res 1 |
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| 85 | PA3 res 1 |
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| 86 | PA4 res 1 |
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| 87 | PA5 res 1 |
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| 88 | PA6 res 1 |
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| 89 | PA7 res 1 |
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| 90 | PA8 res 1 |
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| 91 | PA9 res 1 |
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| 92 | PA10 res 1 |
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| 93 | PA11 res 1 |
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| 94 | PA12 res 1 |
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| 95 | PA13 res 1 |
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| 96 | PA14 res 1 |
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| 97 | PA15 res 1 |
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| 98 | |||
| 99 | |||
| 100 | ;--------------------------------------------------------------------------- |
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| 101 | |||
| 102 | restore ; allow listing again |
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| 103 | |||
| 104 | endif ; stddef5xinc |
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| 105 |