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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | ifndef __stm8lspi01inc ; avoid multiple inclusion |
| 2 | __stm8lspi01inc equ 1 |
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| 3 | |||
| 4 | save |
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| 5 | listing off ; no listing over this file |
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| 6 | |||
| 7 | ;**************************************************************************** |
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| 8 | ;* * |
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| 9 | ;* AS 1.42 - File SPI01.INC * |
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| 10 | ;* * |
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| 11 | ;* contains SFR and Bit Definitions for STM8Lx01 SPI * |
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| 12 | ;* * |
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| 13 | ;**************************************************************************** |
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| 14 | |||
| 15 | __defspi01 macro NAME,Base |
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| 16 | __NS set "\{NAME}_" |
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| 17 | {__NS}CR1 label Base+$00 ; control register 1 |
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| 18 | {__NS}LSBFIRST bit {__NS}CR1,7 ; Frame format |
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| 19 | {__NS}SPE bit {__NS}CR1,6 ; enable |
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| 20 | {__NS}BR bfield {__NS}CR1,3,3 ; Baud rate control |
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| 21 | {__NS}MSTR bit {__NS}CR1,2 ; Master selection |
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| 22 | {__NS}CPOL bit {__NS}CR1,1 ; Clock polarity |
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| 23 | {__NS}CPHA bit {__NS}CR1,0 ; Clock phase |
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| 24 | {__NS}CR2 label Base+$01 ; control register 2 |
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| 25 | {__NS}BDM bit {__NS}CR2,7 ; Bidirectional data mode enable |
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| 26 | {__NS}BDOE bit {__NS}CR2,6 ; Input/Output enable in bidirectional mode |
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| 27 | {__NS}CRCEN bit {__NS}CR2,5 ; Hardware CRC calculation enable |
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| 28 | {__NS}CRCNEXT bit {__NS}CR2,4 ; Transmit CRC next |
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| 29 | {__NS}RXONLY bit {__NS}CR2,2 ; Receive only |
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| 30 | {__NS}SSM bit {__NS}CR2,1 ; Software slave management |
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| 31 | {__NS}SSI bit {__NS}CR2,0 ; Internal slave select |
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| 32 | {__NS}ICR label Base+$02 ; interrupt control register |
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| 33 | {__NS}TXIE bit {__NS}ICR,7 ; Tx buffer empty interrupt enable |
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| 34 | {__NS}RXIE bit {__NS}ICR,6 ; RX buffer not empty interrupt enable |
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| 35 | {__NS}ERRIE bit {__NS}ICR,5 ; Error interrupt enable |
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| 36 | {__NS}WKIE bit {__NS}ICR,4 ; Wakeup interrupt enable |
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| 37 | {__NS}TXDMAEN bit {__NS}ICR,1 ; Tx Buffer DMA Enable |
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| 38 | {__NS}RXDMAEN bit {__NS}ICR,0 ; Rx Buffer DMA Enable |
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| 39 | {__NS}SR label Base+$03 ; status register |
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| 40 | {__NS}BSY bit {__NS}SR,7 ; Busy flag |
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| 41 | {__NS}OVR bit {__NS}SR,6 ; Overrun flag |
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| 42 | {__NS}MODF bit {__NS}SR,5 ; Mode fault |
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| 43 | {__NS}CRCERR bit {__NS}SR,4 ; CRC error flag |
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| 44 | {__NS}WKUP bit {__NS}SR,3 ; Wakeup flag |
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| 45 | {__NS}TXE bit {__NS}SR,1 ; Transmit buffer empty |
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| 46 | {__NS}RXNE bit {__NS}SR,0 ; Receive buffer not empty |
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| 47 | {__NS}DR label Base+$04 ; data register |
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| 48 | endm |
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| 49 | |||
| 50 | restore |
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| 51 | endif ; __stm8lspi01inc |